CN116868326A - Transistor circuits including edgeless transistors and methods of making the same - Google Patents

Abstract

The invention discloses that the first field effect transistor includes a first active region, a first gate dielectric covering the active region, and a first gate electrode covering the first gate dielectric. , the first active region includes a source region, a drain region and a channel region located between the source region and the drain region. The second field effect transistor includes a second active region, a second gate dielectric covering the active region, and a second gate electrode covering the second gate dielectric. The source region includes a source region, a drain region and a channel region located between the source region and the drain region. A trench isolation region surrounds the first active region and the second active region. The first field effect transistor includes an edge region, in which the first gate electrode extends through the active region perpendicular to the direction from the source region to the drain region, and the second field effect transistor does not include the edge zone.

Description

Transistor circuits including edgeless transistors and methods of making the same

Related applications

This application calls for U.S. Non-Provisional Application No. 17/316,015 filed on May 10, 2021, U.S. Non-Provisional Application No. 17/316,079 filed on May 10, 2021, and U.S. Non-Provisional Application No. 17 filed on October 14, 2021 /501,163, the entire contents of these applications are incorporated herein by reference.

Technical field

The present disclosure relates generally to the field of semiconductor devices, and particularly to transistor circuits including edgeless transistors and methods of fabricating the same.

Background technique

Peripheral (ie, driver) circuitry of a memory device includes multiple types of field effect transistors configured to operate at different operating voltages. Providing field effect transistors operating at different operating voltages at high device density is a challenge.

Contents of the invention

According to one aspect of the invention, a semiconductor structure includes: a first field effect transistor including a first active region, a first gate dielectric covering the active region, and a first gate dielectric covering the active region. A first gate electrode on a gate dielectric, the first active region includes a source region, a drain region and a channel region between the source region and the drain region; a second field effect A transistor, the second field effect transistor includes a second active region, a second gate dielectric covering the active region, and a second gate electrode covering the second gate dielectric, the The second active region includes a source region, a drain region and a channel region between the source region and the drain region; and a trench isolation region surrounding the first active region and the second active area. The first field effect transistor includes an edge region in which the first gate electrode extends across the active region in a second horizontal direction perpendicular to the first horizontal source region to drain region direction, and the The second field effect transistor does not include an edge region in which the second gate electrode extends through the active region in a second horizontal direction.

According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided, the method comprising: forming a hard mask over a semiconductor substrate; forming a shallow mask by etching an upper portion of the semiconductor substrate that is not shielded by the hard mask. An isolation trench, wherein the shallow isolation trench laterally surrounds a first active region located under a first hard mask in the hard mask; a shallow trench isolation structure is formed by depositing a dielectric fill material in the shallow isolation trench ; When shielding the field region of the shallow trench isolation structure that laterally surrounds the gap region, the gap region of the shallow trench isolation structure that laterally surrounds the first active region is vertically recessed, wherein the shallow trench isolation structure is located in the gap region forming a recessed horizontal surface in a portion of the structure, and wherein the recessed horizontal surface is vertically recessed relative to a topmost surface of the shallow trench isolation structure located in the field region; forming a first gate on the top surface of the first active region dielectric; forming a first gate electrode material portion over the first gate dielectric and over the recessed horizontal surface of the shallow trench isolation structure; and forming the first gate by patterning the first gate electrode material portion an electrode, wherein the first gate electrode includes a lower gate electrode portion and includes an upper gate electrode portion contacting a top surface of the first gate dielectric and a pair of sidewalls of the shallow trench isolation structure A section where the upper gate electrode portion contacts a first section of the recessed horizontal surface of the shallow trench isolation structure.

According to one aspect of the present disclosure, a semiconductor structure including a first field effect transistor is provided. The first field effect transistor includes a first active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting sidewalls of the first portion of the trench isolation structure and formed by the trench. A first portion of the trough isolation structure surrounds laterally. The first active region includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. A first gate structure including a first gate dielectric, a first gate electrode, a first planar dielectric spacer, and a first conductive gate cap structure overlies the first channel region. The first gate dielectric and the first gate electrode contact sidewalls of the protruding region of the first portion of the trench isolation structure, the sidewalls extending laterally along the first horizontal direction. A first planar dielectric spacer contacts a first portion of a top surface of the first gate electrode. The first conductive gate cap structure includes: a first section contacting a second portion of the top surface of the first gate electrode; a second section covering the first planar interface; above the electrical barrier; and a connection section contacting the first sidewall of the first planar dielectric barrier and connecting the first section and the second section.

According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a first gate dielectric layer and a semiconductor gate material layer above the semiconductor material layer; forming a trench isolation structure through the semiconductor gate material layer and the first gate dielectric layer, wherein the semiconductor gate The patterned portion of the material layer and the first gate dielectric layer includes a stack of a first gate dielectric plate and a first gate electrode material plate laterally surrounded by a first portion of the trench isolation structure; at the first gate electrode forming a planar dielectric spacer layer thereover; physically exposing a portion of the top surface of the first semiconductor gate material layer by patterning the planar dielectric spacer layer; and over the physically exposed portion of the top surface of the first gate electrode material plate forming a first conductive gate cap structure; and patterning a stack of first gate dielectric plates and first gate electrode material plates into a stack of first gate dielectric and first gate electrode.

According to yet another aspect of the present disclosure, a semiconductor structure including a first field effect transistor and a second field effect transistor is provided. The first field effect transistor and the second field effect transistor include first and second active regions respectively, wherein the first active region and the second active region contact sidewalls of the trench isolation structure and are isolated by the trench The structure surrounds laterally, wherein a laterally extending portion of the trench isolation structure is located between the first active region and the second active region. The stack of first gate dielectric and first gate electrode overlies the first channel region within the first active region and contacts the first sidewall of the laterally extending portion of the trench isolation structure. The stack of the second gate dielectric and the second gate electrode overlies the second channel region within the second active region and contacts the second sidewall of the laterally extending portion of the trench isolation structure. The conductive gate connection structure contacts a top surface of the first gate electrode, a top surface of the second gate electrode, and a portion of a top surface of a laterally extending portion of the trench isolation structure, and includes a a pair of transverse side walls and a pair of longitudinal side walls extending transversely along the second horizontal direction. The longitudinal sidewalls of the first gate electrode and the second gate electrode vertically coincide with the pair of longitudinal sidewalls of the conductive gate connection structure.

According to yet another aspect of the present disclosure, a semiconductor structure includes a first field effect transistor. The first field effect transistor includes a first active region, a first gate dielectric covering the active region, a first gate electrode covering the first gate dielectric, and a first gate electrode surrounding the first gate dielectric. The trench isolation region of the active region, the first active region includes a source region, a drain region and a channel region between the source region and the drain region; the first field effect transistor does not include an edge region, in the edge region, the first gate electrode extends through the active region in a horizontal direction perpendicular to the direction from the source region to the drain region; the first gate electrode does not cover the trench above a portion of the isolation region; and the entire occupied area of the first gate electrode is located above and within the lateral boundary of the first active region.

According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a gate dielectric layer and a semiconductor gate material layer above the semiconductor material layer; forming a trench isolation structure through the semiconductor gate material layer and the gate dielectric layer, wherein the semiconductor gate material layer and the gate The patterned portion of the gate dielectric layer includes a first stack of a first gate dielectric plate and a first gate electrode material overlying a first active region of the layer of semiconductor material, and a third plate overlying the layer of semiconductor material. a second stack of a second gate dielectric plate and a second gate electrode material plate over the two active areas; forming a conductive conductive layer over the first gate electrode material plate, the second gate electrode material plate and the trench isolation structure Gate connection material layer; patterning the conductive gate connection material layer into a conductive gate connection structure; anisotropically etching unused conductive gate connection structures of the first gate electrode material plate and the second gate electrode material plate a covered portion, wherein the patterned portions of the first gate electrode material plate and the second gate electrode material plate include the first gate electrode and the second gate electrode; and connecting the first gate dielectric plate and the second gate electrode The electrode dielectric plate is patterned into a first gate dielectric and a second gate dielectric respectively.

Description of the drawings

1A is a top view of a first exemplary structure after forming various doped wells according to a first embodiment of the present disclosure. Figure IB is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure IA. 1C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 1A. FIG. 1D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of FIG. 1A . 1E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 1A. FIG. 1F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 1A .

2A is a top view of a first exemplary structure after forming a gate dielectric layer and a semiconductor gate material layer according to the first embodiment of the present disclosure. 2B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of FIG. 2A. 2C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 2A. Figure 2D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 2A. 2E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 2A. 2F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 2A.

3A is a top view of a first exemplary structure after forming a patterned mask layer, shallow trenches, and deep trenches according to the first embodiment of the present disclosure. 3B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of FIG. 3A. 3C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 3A. Figure 3D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 3A. 3E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 3A. 3F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 3A.

4 is a vertical cross-sectional view of the first exemplary structure after forming a layer of trench fill material according to the first embodiment of the present disclosure.

5A is a top view of a first exemplary structure after forming a trench isolation structure according to the first embodiment of the present disclosure. Figure 5B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 5A. Figure 5C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of Figure 5A. Figure 5D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 5A. Figure 5E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of Figure 5A. Figure 5F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 5A.

6A is a top view of a first exemplary structure after forming a planar semiconductor spacer layer according to the first embodiment of the present disclosure. Figure 6B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 6A. Figure 6C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of Figure 6A. Figure 6D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 6A. 6E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 6A. Figure 6F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 6A.

7A is a top view of a first exemplary structure after patterning a planar semiconductor spacer layer according to a first embodiment of the present disclosure. Figure 7B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 7A. 7C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 7A. Figure 7D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 7A. Figure 7E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of Figure 7A. Figure 7F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 7A.

8A is a top view of a first exemplary structure after depositing a conductive gate cap layer and a gate cap dielectric layer according to a first embodiment of the present disclosure. 8B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of FIG. 8A. 8C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 8A. Figure 8D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 8A. 8E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 8A. Figure 8F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 8A.

9A is a top view of a first exemplary structure after patterning a gate cap dielectric layer, a conductive gate cap layer, and a planar semiconductor spacer layer in accordance with a first embodiment of the present disclosure. Figure 9B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 9A. 9C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 9A. Figure 9D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 9A. Figure 9E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of Figure 9A. 9F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 9A.

10A is a top view of a first exemplary structure after application and patterning of a photoresist layer for patterning a layer of semiconductor gate material in accordance with a first embodiment of the present disclosure. 10B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of FIG. 10A.

10C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 10A. 10D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of FIG. 10A. 10E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 10A. 10F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 10A.

11A is a top view of a first exemplary structure after applying and patterning a layer of semiconductor gate material and a gate dielectric layer in accordance with a first embodiment of the present disclosure. 11B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of FIG. 11A. 11C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 11A. 11D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of FIG. 11A. 11E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 11A. 11F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of FIG. 11A. 11G is a vertical cross-sectional view of the first exemplary structure taken along vertical plane GG' of FIG. 11A.

12A is a top view of a first exemplary structure after forming dielectric gate spacers according to the first embodiment of the present disclosure. Figure 12B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 12A. Figure 12C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of Figure 12A. Figure 12D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 12A. Figure 12E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of Figure 12A. Figure 12F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 12A. 12G is a vertical cross-sectional view of the first exemplary structure taken along vertical plane GG' of FIG. 12A.

13A is a top view of a first exemplary structure after forming source and drain regions according to the first embodiment of the present disclosure. Figure 13B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 13A. 13C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of FIG. 13A. Figure 13D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 13A. Figure 13E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of Figure 13A. Figure 13F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 13A. 13G is a vertical cross-sectional view of the first exemplary structure taken along vertical plane GG' of FIG. 13A.

14A is a top view of a first exemplary structure after forming a contact level dielectric layer and various contact via structures in accordance with the first embodiment of the present disclosure. Figure 14B is a vertical cross-sectional view of the first exemplary structure taken along the hinged vertical plane BB' of Figure 14A. Figure 14C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane CC' of Figure 14A. Figure 14D is a vertical cross-sectional view of the first exemplary structure taken along vertical plane DD' of Figure 14A. 14E is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane EE' of FIG. 14A. Figure 14F is a vertical cross-sectional view of the first exemplary structure taken along vertical plane FF' of Figure 14A.

15A is a top view of a second exemplary structure after forming a trench isolation structure according to a second embodiment of the present disclosure. Figure 15B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 15A. Figure 15C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 15A. Figure 15D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 15A. Figure 15E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 15A. Figure 15F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 15A.

16A is a top view of a second exemplary structure after implanting electrical dopants into a subset of the lower semiconductor gate material layer in accordance with a second embodiment of the present disclosure. Figure 16B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 16A. Figure 16C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 16A. Figure 16D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 16A. Figure 16E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 16A. Figure 16F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 16A.

17A is a top view of a second exemplary structure after forming a planar semiconductor spacer layer according to a second embodiment of the present disclosure. Figure 17B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 17A. Figure 17C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 17A. Figure 17D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 17A. Figure 17E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 17A. Figure 17F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 17A.

18A is a top view of a second exemplary structure after patterning a planar semiconductor spacer layer in accordance with a second embodiment of the present disclosure. Figure 18B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 18A. Figure 18C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 18A. Figure 18D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 18A. Figure 18E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 18A. Figure 18F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 18A.

19A is a top view of a second exemplary structure after depositing a conductive gate capping layer and a planar dielectric spacer layer in accordance with a second embodiment of the present disclosure. Figure 19B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 19A. Figure 19C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 19A. Figure 19D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 19A. Figure 19E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 19A. Figure 19F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 19A.

20A is a top view of a second exemplary structure after patterning a gate cap dielectric layer, a conductive gate cap layer, and a planar semiconductor spacer layer in accordance with a second embodiment of the present disclosure. 20B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of FIG. 20A. 20C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of FIG. 20A. 20D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of FIG. 20A. 20E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of FIG. 20A. 20F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of FIG. 20A.

21A is a top view of a second exemplary structure after application and patterning of a photoresist layer used to pattern a lower semiconductor gate material layer in accordance with a second embodiment of the present disclosure. 21B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of FIG. 21A. 21C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of FIG. 21A. 21D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of FIG. 21A. 21E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of FIG. 21A. 21F is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane FF' of FIG. 21A.

22A is a top view of a second exemplary structure after application and patterning of a lower semiconductor gate material layer and a gate dielectric layer in accordance with a second embodiment of the present disclosure. Figure 22B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 22A. Figure 22C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 22A. Figure 22D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 22A. Figure 22E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 22A.

Figure 22F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 22A. 22G is a vertical cross-sectional view of the second exemplary structure taken along vertical plane GG' of FIG. 22A.

23A is a top view of a second exemplary structure after forming dielectric gate spacers according to a second embodiment of the present disclosure. Figure 23B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 23A. Figure 23C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 23A. Figure 23D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 23A. Figure 23E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 23A. Figure 23F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 23A. 23G is a vertical cross-sectional view of the second exemplary structure taken along vertical plane GG' of FIG. 23A.

24A is a top view of a second exemplary structure after forming source and drain regions according to the second embodiment of the present disclosure. Figure 24B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 24A. Figure 24C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 24A. Figure 24D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 24A. Figure 24E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 24A. Figure 24F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 24A. Figure 24G is a vertical cross-sectional view of the second exemplary structure taken along vertical plane GG' of Figure 24A.

25A is a top view of a second exemplary structure after forming a contact level dielectric layer and various contact via structures in accordance with a second embodiment of the present disclosure. Figure 25B is a vertical cross-sectional view of the second exemplary structure taken along the hinged vertical plane BB' of Figure 25A. Figure 25C is a vertical cross-sectional view of the second exemplary structure taken along vertical plane CC' of Figure 25A. Figure 25D is a vertical cross-sectional view of the second exemplary structure taken along vertical plane DD' of Figure 25A. Figure 25E is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane EE' of Figure 25A. Figure 25F is a vertical cross-sectional view of the second exemplary structure taken along vertical plane FF' of Figure 25A.

26A is a top view of a third exemplary structure after forming a trench isolation structure according to a third embodiment of the present disclosure. Figure 26B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 26A.

27A is a top view of a third exemplary structure after forming a planar semiconductor spacer layer according to a third embodiment of the present disclosure. Figure 27B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 27A.

28A is a top view of a third exemplary structure after patterning a planar semiconductor spacer layer in accordance with a third embodiment of the present disclosure. Figure 28B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 28A.

29A is a top view of a third exemplary structure after depositing a layer of semiconductor gate material and a conductive gate capping layer in accordance with a third embodiment of the present disclosure. Figure 29B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 29A.

30A is a top view of a third exemplary structure after patterning a conductive gate capping layer and an upper semiconductor gate material layer in accordance with a third embodiment of the present disclosure. 30B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of FIG. 30A.

31A is a top view of a third exemplary structure after application and patterning of a photoresist layer for patterning a planar semiconductor spacer layer and a lower semiconductor gate material layer in accordance with a third embodiment of the present disclosure. 31B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of FIG. 31A.

32A is a top view of a third exemplary structure after applying and patterning a planar semiconductor spacer layer and a lower semiconductor gate material layer in accordance with a third embodiment of the present disclosure. Figure 32B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 32A. 32C is a vertical cross-sectional view of the third exemplary structure taken along vertical plane CC' of FIG. 32A.

Figure 32D is a vertical cross-sectional view of the third exemplary structure taken along vertical plane DD' of Figure 32A.

33A is a top view of a third exemplary structure after forming dielectric gate spacers according to a third embodiment of the present disclosure. 33B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of FIG. 33A.

34A is a top view of a third exemplary structure after forming source and drain regions according to a third embodiment of the present disclosure. 34B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of FIG. 34A. 34C is a vertical cross-sectional view of the third exemplary structure taken along vertical plane CC' of FIG. 34A. Figure 34D is a vertical cross-sectional view of the third exemplary structure taken along vertical plane DD' of Figure 34A.

35A is a top view of a third exemplary structure after forming a contact level dielectric layer and various contact via structures in accordance with a third embodiment of the present disclosure. Figure 35B is a vertical cross-sectional view of the third exemplary structure taken along the hinged vertical plane BB' of Figure 35A.

FIG. 36A is a top view of the transistor structure of the comparison sense amplifier. 36B is a vertical cross-sectional view of the comparative sense amplifier transistor structure taken along the vertical plane BB' of FIG. 36A.

Figure 37A is a top view of a fourth exemplary sense amplifier transistor structure according to a fourth embodiment of the present disclosure. Figure 37B is a vertical cross-sectional view of a fourth exemplary sense amplifier transistor structure taken along vertical plane BB' of Figure 37A.

FIG. 38 is a top view of the structures of two adjacent comparison sense amplifier transistors of FIG. 36A. 39 is a top view of two adjacent fourth exemplary sense amplifier transistor structures of FIG. 37A according to a fourth embodiment of the present disclosure.

40A is a top view of a first exemplary semiconductor structure according to a first embodiment of the present disclosure. 40B is a vertical cross-sectional view of the first exemplary semiconductor structure taken along vertical plane BB' of FIG. 40A.

Figure 41 is a top view of the structures of two adjacent transistors for comparison. 42 is a top view of two adjacent first exemplary transistor structures according to the first embodiment of the present disclosure. 43 is a top view of two adjacent second exemplary transistor structures according to a second embodiment of the present disclosure. 44 is a top view of an alternative configuration of a second exemplary transistor structure according to a second embodiment of the present disclosure.

Figure 45A is a top view of a third exemplary transistor structure according to a third embodiment of the present disclosure. Figure 45B is a vertical cross-sectional view of a third exemplary transistor structure taken along vertical plane BB' of Figure 45A.

Figure 46A is another top view of a third exemplary transistor structure according to a third embodiment of the present disclosure. 46B and 46C are vertical cross-sectional views of a third exemplary transistor structure taken along vertical planes BB' and CC', respectively, of FIG. 46A.

47A is a top view of a fifth exemplary structure after forming shallow trenches according to a fifth embodiment of the present disclosure. 47B, 47C, and 47D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 47A.

48A is a top view of a fifth exemplary structure after forming a shallow trench isolation structure according to a fifth embodiment of the present disclosure. 48B, 48C, and 48D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 48A.

49A is a top view of a fifth exemplary structure after vertically recessing a gap region of a shallow trench isolation structure according to a fifth embodiment of the present disclosure. 49B, 49C, and 49D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 49A.

50A is a top view of a fifth exemplary structure after removing the hard mask and forming a gate dielectric layer according to a fifth embodiment of the present disclosure. 50B, 50C, and 50D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 50A.

51A is a top view of a fifth exemplary structure after forming a gate electrode material portion according to a fifth embodiment of the present disclosure. 51B, 51C, and 51D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 51A.

52A is a top view of a fifth exemplary structure after forming a gate dielectric and a gate electrode according to a fifth embodiment of the present disclosure. 52B, 52C, and 52D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 52A.

53A is a top view of a fifth exemplary structure after forming a dielectric liner layer and source/drain extension regions according to a fifth embodiment of the present disclosure. 53B, 53C, and 53D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 53A.

54A is a top view of a fifth exemplary structure after forming main dielectric spacers and deep source/drain regions according to a fifth embodiment of the present disclosure. 54B, 54C, and 54D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 54A.

55A is a top view of a fifth exemplary structure after forming a metal-semiconductor alloy region according to a fifth embodiment of the present disclosure. 55B, 55C, and 55D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 55A.

56A is a top view of a fifth exemplary structure after forming a planarized dielectric layer according to a fifth embodiment of the present disclosure. 56B, 56C, and 56D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 56A.

57A is a top view of a fifth exemplary structure after forming various contact via structures according to a fifth embodiment of the present disclosure. 57B, 57C, and 57D are vertical cross-sectional views of the fifth exemplary structure taken along vertical planes BB', CC', and DD', respectively, of FIG. 57A.

Detailed ways

Embodiments of the present disclosure provide transistor circuits including edgeless transistors and methods of fabricating the same, various aspects of which are described below. Such high-density transistor circuits, including edgeless transistors, may be employed in a variety of applications, such as sense amplifiers and peripheral low-voltage driver circuits for memory devices such as three-dimensional memory arrays.

The drawings are not to scale. Where a single instance of an element is shown, multiple instances of an element may be repeated unless explicitly described or otherwise clearly indicates that there is no duplication of the element. Serial numbers such as "first," "second," and "third" are merely used to identify similar elements, and different serial numbers may be employed throughout the specification and claims of this disclosure. The same reference numbers indicate the same elements or similar elements. Unless stated otherwise, elements with the same reference number are assumed to have the same composition. As used herein, a first element positioned "on" a second element may be positioned on the outside of a surface of the second element or on the inside of the second element. As used herein, a first element is positioned "directly" on a second element if there is physical contact between the surface of the first element and the surface of the second element.

As used herein, "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying layer or overlying structure, or may have an extent that is less than the extent of the underlying layer or overlying structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above, and/or below it.

As used herein, a "layer stack" refers to a stack of layers. As used herein, a "line" or "line structure" refers to a layer having a primary direction of extension, ie, the direction in which the layer extends greatest.

As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 ^-6 S/cm to 1.0×10 ⁵ S/cm. As used herein, "semiconductor material" refers to a material that has an electrical conductivity in the range of 1.0×10 ^-6 S/cm to 1.0×10 ⁵ S/cm in the absence of electrical dopants and is capable of Suitable doping with electrical dopants results in a doped material having an electrical conductivity in the range of 1.0 S/cm to 1.0×10 ⁵ S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 ⁵ S/cm. As used herein, "insulator material,""insulatingmaterial," or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 ⁻⁶ S/cm. As used herein, "heavily doped semiconductor material" refers to a semiconductor material that is doped with an electrical dopant at a sufficiently high atomic concentration to become an electrically conductive material (i.e., has an electrical conductivity greater than 1.0×10 ⁵ S/cm) . "Doped semiconductor material" may be a heavily doped semiconductor material, or may include an electrical dopant at a concentration that provides a conductivity in the range of 1.0×10 ^-6 S/cm to 1.0×10 ⁵ S/cm (i.e., p-type dopants and/or n-type dopants) semiconductor materials. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials may be semiconducting or conductive, depending on the atomic concentration of electrical dopants therein. As used herein, "metallic material" refers to an electrically conductive material that includes at least one metallic element therein. All conductivity measurements were performed under standard conditions.

As used herein, "field effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows at a current density modulated by an external electric field. As used herein, "channel region" refers to a semiconductor region in which the mobility of charge carriers is affected by an applied electric field. "Gate electrode" refers to the portion of conductive material that controls electron mobility in the channel region through the application of an electric field. "Source region" refers to the doped semiconductor region that supplies charge carriers flowing through the channel region. "Drain region" refers to a doped semiconductor region that receives charge carriers supplied from the source region and flowing through the channel region. A "source/drain region" may be a source region or a drain region. "Active region" refers to the collective name of the source region, drain region and channel region of a field effect transistor. "Source extension region" refers to a doped semiconductor region that is part of the source region and has a lower dopant concentration than the remainder of the source region. "Drain extension region" refers to a doped semiconductor region that is part of the drain region and has a lower dopant concentration than the remainder of the drain region. "Active area extension" refers to a source extension area or a drain extension area.

Referring to FIGS. 1A-1F , a first exemplary structure according to an embodiment of the present disclosure is shown. The first exemplary structure includes semiconductor substrate 2 . As used herein, "semiconductor substrate" refers to a substrate that includes at least one portion of semiconductor material (ie, at least a portion of semiconductor material). Semiconductor substrate 2 includes a semiconductor material at least at its top portion. The semiconductor substrate 2 may optionally comprise at least one additional material layer at its bottom portion. In one embodiment, the semiconductor substrate 2 may be a bulk semiconductor substrate composed of a semiconductor material (e.g., a single crystal silicon wafer), or may be a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor substrate located on a semiconductor (e.g., A buried insulator layer (such as a silicon oxide layer) underlying the silicon) material portion and a handle substrate underlying the buried insulator layer.

The semiconductor substrate 2 may include a substrate semiconductor layer 4 including a lightly doped semiconductor material portion, on which at least one field effect transistor may be formed. In one embodiment, the entire semiconductor substrate 2 may be the substrate semiconductor layer 4 . In another embodiment, the substrate semiconductor layer 4 may comprise an upper portion of the semiconductor substrate 2, such as a doped well in a silicon wafer. The substrate semiconductor layer 4 may include a lightly doped semiconductor material, the lightly doped semiconductor material including an atomic concentration of 1.0×10 ¹⁴ /cm ³ to 1.0×10 ¹⁸ /cm ³ (such as 1.0×10 ¹⁵ /cm ³ to 1.0 ×10 ¹⁷ /cm ³ ), but lower and higher atomic concentrations can also be used.

The semiconductor material of the substrate semiconductor layer 4 may be an elemental semiconductor material (such as silicon) or an alloy of at least two elemental semiconductor materials (such as a silicon-germanium alloy), or may be a compound semiconductor material (such as a III-V compound semiconductor material or II- VI compound semiconductor material), or may be an organic semiconductor material. In the case where the semiconductor substrate 2 is a bulk semiconductor substrate, the thickness of the substrate semiconductor layer 4 may be in the range of 0.5 mm to 2 mm. In the case where the semiconductor substrate 2 is a semiconductor-on-insulator substrate, the thickness of the base semiconductor layer 4 may be in the range of 100 nm to 1,000 nm, but smaller and larger thicknesses may also be used.

Various doped wells (5, 6) may be formed in the upper part of the semiconductor substrate 2 (eg in the substrate semiconductor layer 4). The various doped wells (5,6) may include a p-type well 5 with corresponding p-type doping and an n-type well 6 with corresponding n-type doping. For example, the p-type well 5 may include a first p-type well 6A, a second p-type well 5B, a third p-type well 5C, and the like. The n-type well 6 may include a first n-type well 6A, a second n-type well 6B, a third n-type well 6C, a fourth n-type well 6D, and so on. Various semiconductor devices may be formed using regions including various doped wells (5,6). For example, the region including first n-type well 6A may include a first p-type field effect transistor region 100 in which a first p-type field effect transistor including p-doped source and drain regions will subsequently be formed. In the field effect transistor region; the region including the first p-type well 5A may include the first n-type field effect transistor region 200 in which a first n-type field effect transistor including n-doped source and drain regions will subsequently be formed. In the first n-type field effect transistor region; the region including the second n-type well 6B may include a second p-type field effect transistor region 300, followed by a second p-type field effect transistor including p-doped source and drain regions. will be formed in this second p-type field effect transistor region; the region including the second p-type well 5B may include a second n-type field effect transistor region 400, a second n-type including n-doped source and drain regions. Field effect transistors will then be formed in this second n-type field effect transistor region; the region including the third n-type well 6C may include the third p-type field effect transistor region 500, including p-doped source and drain regions. A third p-type field effect transistor will subsequently be formed in this third p-type field effect transistor region; and the region including the third p-type well 5C may include a third n-type field effect transistor region 600, including an n-doped source A second n-type field effect transistor and a drain region will then be formed in the third n-type field effect transistor region. Alternatively, the region including the fourth n-doped well 6D may include a first passive device region 700 in which a first passive device such as a resistor is subsequently formed. Alternatively, the region where the substrate semiconductor layer 4 is physically exposed may be used for a passive device region, such as the second passive device region 800, in which a second passive device such as a capacitor is subsequently formed. For example, regions 100 and 200 may include low voltage transistors, regions 300 and 400 may include ultra-low voltage transistors that operate at a lower voltage than low voltage transistors, and regions 500 and 600 may include regions that operate at a higher voltage than low voltage transistors. A high voltage transistor that operates under voltage.

Various device regions may be arranged on the top surface of semiconductor substrate 2 in any pattern. Although the present disclosure is described using an embodiment in which the direction of the semiconductor channel (ie, the direction of current flow in the channel region of the field effect transistor) is parallel to the first horizontal direction hd1 and perpendicular to the second horizontal direction hd2 , it should be understood that , the direction of the semiconductor channel can be oriented in any direction for each field effect transistor subsequently formed. The depth of each doped well (5,6) and the dopant concentration in each doped well (5,6) may be appropriately selected. For example, the dopant concentration in each doped well (5, 6) may be in the range of 1.0×10 ¹⁴ /cm ³ to 1.0×10 ¹⁸ /cm ³ (such as 1.0×10 ¹⁵ /cm ³ to 1.0×10 ¹⁷ / cm ³ ), but lower and higher atomic concentrations can also be used. The depth of each well (5,6) may range from 50 nm to 2,000 nm, although smaller and larger depths are also possible.

Referring to FIGS. 2A-2F , various gate dielectric layers ( 20L, 22L) may be formed on the top surface of semiconductor substrate 2 . For example, the first gate dielectric layer 22L may be formed in a region where low voltage field effect transistors and ultra-low voltage field effect transistors employing thinner gate dielectrics will subsequently be formed, and the second gate dielectric layer 22L 20L may be formed in areas where high voltage field effect transistors using thicker gate dielectrics will subsequently be formed. In an illustrative example, the first p-type field effect transistor region 100 may include a low voltage p-type field effect transistor, the first n-type field effect transistor region 200 may include a low voltage n-type field effect transistor, and the second p-type field effect transistor may include a low voltage p-type field effect transistor. Transistor region 300 may include ultra-low voltage p-type field effect transistors, second n-type field effect transistor region 400 may include ultra-low voltage n-type field effect transistors, and third p-type field effect transistor region 500 may include high voltage p-type field effect transistors. effect transistor, and the third n-type field effect transistor region 600 may include a high voltage n-type field effect transistor. The above transistors may be employed in peripheral (eg, driver) circuitry of the memory device. Additional transistors may be employed in the sense amplifier circuit of the memory device. In this case, the first gate dielectric layer 22L may be formed in the first p-type field effect transistor region 100, the first n-type field effect transistor region 200, the second p-type field effect transistor region 300 and the second n-type field effect transistor region 100. field effect transistor region 400 . The second gate dielectric layer 20L may be formed in the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600 . As needed, the first passive device region 700 and the second passive device region 800 may include a portion of the first gate dielectric layer 22L and/or a portion of the second gate dielectric layer 20L. In an illustrative example, the second gate dielectric layer 20L may be formed on the top surface of the semiconductor substrate 2 and may be patterned such that from the first p-type field effect transistor region 100 , the first n-type field effect transistor region 100 The transistor region 200, the second p-type field effect transistor region 300, and the second n-type field effect transistor region 400 remove portions of the second gate dielectric layer 20L. Subsequently, first gate dielectric layer 22L may be formed by thermally oxidizing a physically exposed surface portion of semiconductor substrate 2 and/or by depositing a dielectric material, such as silicon oxide. The thickness of first gate dielectric layer 22L may be in the range of 1 nm to 6 nm, such as 1.5 nm to 3 nm, although smaller and larger thicknesses may also be used. The first gate dielectric layer 22L may be thicker in the low voltage transistor regions 100 and 200 than in the ultra-low voltage transistor regions 300 and 400 . The thickness of the second gate dielectric layer 20L may be thicker than that of the first gate dielectric layer 22L, and may be in the range of 4 nm to 30 nm (such as 6 nm to 15 nm), but smaller and larger thicknesses may also be used. thickness of.

A polish stop pad layer 23L and a semiconductor gate material layer 24L may be formed on the first and second gate dielectric layers (22L, 20L). Polish stop pad layer 23L may include any suitable sacrificial material that may serve as a polish stop, such as silicon nitride and/or a bilayer of silicon nitride and silicon oxide. Semiconductor gate material layer 24L may include a heavily doped polysilicon layer. Alternatively, polish stop pad layer 23L may also be formed on top of semiconductor gate material layer 24L. The thickness of the layers (23L, 24L) may be in the range of 50 nm to 300 nm (such as 100 nm to 200 nm), although smaller and larger thicknesses may also be used.

Referring to Figures 3A-3F, a mask layer 29, such as a photoresist layer or a hard mask layer 29, may be deposited over layers (23L, 24L). Mask layer 29 is patterned to form a pattern of openings around each area in which a semiconductor device will subsequently be formed. For example, within the area of the field effect transistor regions (100, 200, 300, 400, 500, 600), the area of the opening in the mask layer 29 may be located outside the area of the active area (ie, source area, drain area area and channel area). Within the area of the passive device regions (700, 800), the area of the openings in each mask layer 29 may be located outside the area of the passive devices that will subsequently be formed. Anisotropic etching may be performed to transfer the pattern of openings in mask layer 29 through the underlying layer. For example, deep trenches 7D may be formed in regions 500, 600, 700, and 800 into the upper portion of semiconductor substrate 2 through polish stop pad layer 23L. The depth of deep trench 7D can range from 1,000nm to 2,000nm, but smaller and larger depths are also possible. Shallow trenches 7C may be formed in regions 100, 200, 300, and 400 through the semiconductor gate material layer 24L (and optionally through any portion of the polish stop pad layer located on the semiconductor gate material layer 24L) to the semiconductor in the upper part of substrate 2. The depth of the shallow trench 7S may be shallower than the depth of the deep trench 7D. The depth of shallow trench 7S can range from 150nm to 500nm, but smaller and larger depths are also possible. Masking layer 29 can then be removed. The combination of deep trench 7D and shallow trench 7S is collectively referred to as trench 7 . The trench 7 divides the layers (23L, 24L) into polishing stop plates 23 and gate electrode material plates 24. Additionally, trenches divide the gate dielectric layers (22L, 20L) into gate dielectric plates (22, 20), which may include, for example, a first gate dielectric plate 22 and a second gate dielectric plate 22, 20L. Dielectric plate 20.

Referring to FIG. 4 , at least one layer of trench fill material 8L may be conformally deposited in trench 7 and over polish stop plate 23 and gate electrode material plate 24 . The at least one trench fill material layer 8L may be composed of at least one dielectric fill material, such as silicon oxide, or may include a dielectric liner, such as a silicon oxide liner, and at least one semiconductor fill material, such as an amorphous silicon or polysilicon).

Referring to FIGS. 5A to 5F , excess portions of at least one trench filling material layer 8L may be removed from above the top surfaces of the polishing stop plate 23 and the gate electrode material plate 24 through a planarization process, which may include chemical mechanical Polishing (CMP) process. The CMP process stops at the polishing stop plates 23 and optionally at the gate electrode material plates 24 if they are exposed between the polishing stop plates 23 . The polish stop plate 23 located above the gate electrode material plate 24 may be removed during the CMP process and the polish stop plate 23 located in other areas may be thinned by the CMP process and/or by selective etching such as hot phosphoric acid etching. ) Completely or partially peel off these polish stop plates.

The remainder of the at least one trench fill material layer 8L filling the trench 7 constitutes trench isolation structures 8 which may be phases that bring the semiconductor material of the semiconductor substrate 2 into contact with the dielectric surface and will subsequently be formed. A continuous structure that provides electrical isolation between adjacent semiconductor devices. The trench isolation structure 8 includes a deep trench isolation structure 8D located in the deep trench 7D and a shallow trench isolation structure 8S located in the shallow trench 7S.

Generally speaking, trench isolation structure 8 may be formed through the plates (23L, 24L) and gate dielectric layers (22L, 20L). The patterned portions of semiconductor gate material layer 24L and first gate dielectric layer 22L include a stack of gate dielectric plates 22 and gate electrode material plates 24 laterally surrounded by corresponding portions of trench isolation structures 8 .

Referring to FIGS. 6A-6F , a planar dielectric spacer layer 30L and a planar semiconductor spacer layer 34L may be deposited over the gate electrode material plates (24, 23) and trench isolation structure 8. Planar dielectric spacer layer 30L includes a dielectric material such as silicon oxide, and may be formed by a conformal or non-conformal deposition process. The thickness of planar dielectric spacer layer 30L may be in the range of 3 nm to 30 nm, although smaller and larger thicknesses may also be used. The planar semiconductor spacer layer 34L includes a semiconductor material, such as polysilicon material, silicon germanium alloy material, or compound semiconductor material. The thickness of the planar semiconductor spacer layer 34L may be in the range of 30 nm to 300 nm, such as 60 nm to 150 nm, although smaller and larger thicknesses may also be used.

Referring to FIGS. 7A-7F , a photoresist layer (not shown) is applied over the first exemplary structure and may be photolithographically patterned to form a gap between the first p-type well 5A and the trench isolation structure 8 Openings are formed above the region of the interface between the first n-type well 6A and the trench isolation structure 8 . Specifically, the opening in the photoresist layer may be formed in a region including an interface between channel regions of a low voltage field effect transistor that will subsequently be formed in a first p-type field effect transistor. in region 100 and in first n-type field effect transistor region 200 . Additionally, regions in which high voltage field effect transistors employing thick gate dielectrics will subsequently be formed, such as the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600 , may be removed. Photoresist layer.

An anisotropic etching process may be performed to remove unmasked portions of planar semiconductor spacer layer 34L and planar dielectric spacer layer 30L. The top surface of the plate 23 and the trench isolation structure 8 may be physically exposed in the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600 . In one embodiment, openings through planar semiconductor spacer layer 34L and planar dielectric spacer layer 30L in first p-type field effect transistor region 100 and in first n-type field effect transistor region 200 may include shallow trench isolation. An area of a portion of structure 8S, an area of a portion of first gate electrode material plate 24 , and an area of a portion of another first gate electrode material plate 24 .

Generally speaking, planar semiconductor spacer layer 34L and planar dielectric spacer layer 30L may be patterned using an etching process using an etch mask, such as a patterned photoresist layer. A portion of the top surface of first semiconductor gate material layer 24L (including a portion of the top surface of first semiconductor gate material plate 24 ) is physically exposed by patterning planar semiconductor spacer layer 34L and planar dielectric spacer layer 30L. The photoresist layer can then be removed, for example by ashing.

Referring to FIGS. 8A to 8F , a conductive gate connection material layer including a metallic material may be deposited directly on the physically exposed top surface plate ( 23 , 24 ) and trench isolation structure 8 . In one embodiment, the conductive gate connection material layer may include conductive gate capping layer 40L. Conductive gate capping layer 40L may include metallic materials such as elemental metals (eg, tungsten and/or titanium), intermetallic alloys, conductive metal nitrides (eg, TiN or WN), conductive metal carbides, heavily doped semiconductors (eg, heavily doped polysilicon) and/or conductive metal semiconductor alloys (such as metal silicides). The thickness of conductive gate capping layer 40L may range from 20 nm to 200 nm, such as 40 nm to 100 nm, although smaller and larger thicknesses may also be used. Generally speaking, the conductive gate capping layer 40L may be deposited over the planar semiconductor spacer layer 34L and directly on the top surfaces of the remainder of the layers (23L, 24L), i.e. directly on top of the plates (23, 24) On the surface.

Gate cap dielectric layer 50L may then be deposited over conductive gate cap layer 40L. Gate cap dielectric layer 50L includes a dielectric material, such as silicon nitride. Gate cap dielectric layer 50L may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 50 nm, although smaller and larger thicknesses may also be used.

Referring to FIGS. 9A-9F , a first photoresist layer 53 may be applied over the first exemplary structure and may be photolithographically patterned to form discrete patterned photoresist material portions. The patterned portion of first photoresist layer 53 may include a first portion overlying an edge of planar semiconductor material layer 34L in first p-type field effect transistor region 100 and in first n-type field effect transistor region 200 . The patterned portion of the first photoresist layer 53 may include a second portion defining the shape of the gate electrode to be formed in the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600 . The patterned portion of the first photoresist layer 53 may include additional portions covering corresponding areas within the first passive device region 700 and the second passive device region 800 .

A first anisotropic etch process may be performed to transfer the pattern in first photoresist layer 53 through gate cap dielectric layer 5OL, conductive gate cap layer 4OL, planar semiconductor spacer layer 34L and portions of plate 23 located outside the area of planar dielectric spacer layer 30L, including portions of plate 23 located within third p-type field effect transistor region 500 and third n-type field effect transistor region 600 . Planar dielectric spacer layer 30L, second gate dielectric plate 20 and trench isolation structure 8 may serve as etch stop structures for the first anisotropic etching process. In the case where planar dielectric spacer layer 30L, second gate dielectric plate 20 and trench isolation structure 8 include silicon oxide, the etch chemistry of the termination step of the first anisotropic etch process may be selective to silicon oxide. The planar semiconductor spacer layer 34L and the semiconductor material of the plate 23 are etched.

Each patterned portion of gate cap dielectric layer 50L includes gate cap dielectric 50 . Each patterned portion of conductive gate cap layer 40L includes conductive gate cap structure 40 . Each patterned portion of planar semiconductor spacer layer 34L includes planar semiconductor spacer plate 34 .

A contiguous combination of first gate cap dielectric 50 , first conductive gate cap structure 40 and first planar semiconductor spacer 34 may be formed in first p-type field effect transistor region 100 and/or first n-type on the top surface of each gate electrode material plate 24 in field effect transistor region 200 . In this case, the first conductive gate cap structure 40 may be formed on a physically exposed top surface of a portion of the first plate of gate electrode material 24 . According to one aspect of the invention, the first conductive gate cap structure 40 in the first p-type field effect transistor region 100 or the first n-type field effect transistor region 200 includes: a first section contacting a portion of the top surface of the underlying plate of gate electrode material 24; a second section overlying the first planar dielectric spacer layer 34L; and a connection section contacting the first planar dielectric spacer 34L. The first sidewall of electrical isolation layer 34L connects the first section and the second section.

According to one aspect of the invention, a portion of the first conductive gate cap structure 40 covers a portion of the top surface of the lower portion of the shallow trench isolation structure 8 and a portion of the bottom surface of the first conductive gate cap structure 40 contacts This portion of the top surface of the underlying portion of the shallow trench isolation structure 8 . The first sidewall of the first planar semiconductor spacer 34 overlies, vertically coincides with the first sidewall of the planar dielectric spacer 30L, and contacts the first conductive gate. Connection section of cap structure 40 . First planar semiconductor spacer plate 34 may be formed on a top surface of planar dielectric spacer layer 30L, with semiconductor gate plate 24 (ie, a portion of semiconductor gate material layer 24L) covered by planar dielectric spacer layer 30L. The first conductive gate cap structure 40 is formed directly on the first planar semiconductor spacer plate 34 . The first photoresist layer 53 may then be removed, for example by ashing.

Referring to FIGS. 10A-10F , a second photoresist layer 57 may be applied over the first exemplary structure and may be photolithographically patterned to provide patterned photoresist material portions that pattern the photoresist material. The resist material portions will subsequently be formed in the first p-type field effect transistor region 100 , the first n-type field effect transistor region 200 , the second p-type field effect transistor region 300 , and the second n-type field effect transistor region 400 the shape of the gate electrode. In one embodiment, the area of the patterned portion of the second photoresist layer 57 may include all of the patterned portion of the first photoresist layer 53 employed in the processing steps of Figures 9A-9F. area. The second photoresist layer 57 may cover all areas of the third p-type field effect transistor region 500, the third n-type field effect transistor region 600, and the passive device regions (700, 800).

Referring to FIGS. 11A-11G , a second anisotropic etching process may be performed to transfer the pattern of the second photoresist layer 57 through the planar dielectric spacer layer 30L, the polish stop plate 23 , the gate electrode material plate 24 and first gate dielectric plate 22. Each patterned portion of planar dielectric spacer layer 30L constitutes planar dielectric spacer plate 30 . Each patterned portion of the polish stop plate 23 constitutes the dielectric portion 13 . Dielectric portion 13 may include silicon nitride portions used as part of the composite silicon nitride/silicon oxide gate dielectric (13, 20) in the high voltage transistors in regions 500 and 600. Each patterned portion of the plate of gate electrode material 24 includes a gate electrode 14 . Each patterned portion of first gate dielectric plate 22 constitutes first gate dielectric 12 . The terminal portion of the second anisotropic etching process may be selective to the semiconductor material of the semiconductor substrate 2 . The second photoresist layer 57 may then be removed, for example by ashing.

Generally speaking, the stack of first gate dielectric plate 22 and gate electrode material plate 24 may be patterned into a stack of first gate dielectric 12 and first gate electrode 14 . Plate 24 of gate electrode material is patterned into gate electrode 14 by a second anisotropic etching process using photoresist layer 57 as a patterning etch mask. First gate dielectric plate 22 and planar dielectric spacer layer 30L may be patterned into first gate dielectric 12 and first planar dielectric, respectively, by the same etch process, such as a second anisotropic etch process. Spacer plate 30.

When patterning the first sheet of gate electrode material 24 into the first gate electrode 14 , the first planar dielectric spacer 30 covers a first portion of the top surface of the gate electrode 14 . A first portion of the top surface of gate electrode 14 contacts the bottom surface of first planar dielectric spacer 30 . The first conductive gate cap structure 40 includes a first section contacting a second portion of the top surface of the gate electrode 14 and a second section covering the first planar intermediary. above the electrical spacer plate 30; and a connection section that contacts the first side wall of the first planar dielectric spacer plate 30 and connects the first section and the second section.

Referring to FIGS. 12A-12G , source/drain extension regions (not shown) may optionally be implanted using a corresponding patterned implant mask layer (such as a patterned photoresist layer) and a corresponding ion implantation process. It is formed by injecting p-type dopants and n-type dopants. The dielectric gate spacer material layer including the dielectric material may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The dielectric material of the dielectric gate spacer material layer may include, for example, silicon nitride and/or silicon oxide. An anisotropic etching process may be performed to etch horizontally extending portions of the dielectric gate spacer material layer. The remaining vertical extensions of the layer of dielectric gate spacer material constitute dielectric gate spacers 56 .

The anisotropic etching process can be extended to etch unmasked portions of the dielectric material of the second gate dielectric plate 20 and the trench isolation structure 8 selectively with respect to the material of the gate electrode 14 . In this case, second gate dielectric plate 20 may be patterned into second gate dielectric 10 (which may include composite silicon nitride/silicon oxide gates for the high voltage transistors in regions 500 and 600 portions of the polar dielectric (10, 13)), and the physically exposed top surface of the trench isolation structure 8 may be vertically recessed. In one embodiment, the outer sidewalls of each second gate dielectric 10 may vertically coincide with the outer sidewalls of a corresponding one of the gate spacers 56 . As used herein, if a first surface overlies or underlies a second surface or the second surface overlies or underlies the first surface, and the first and second surfaces lie in the same vertical plane , the first surface and the second surface coincide with each other in the vertical direction. In one embodiment, the recessed portion of the top surface of trench isolation structure 8 may be at or about the height of the top surface of the third doped well (5C, 5D) in the third field effect transistor region (500, 600).

In one embodiment, first dielectric gate spacer 56 located within first field effect transistor region (100 or 200) includes an upper portion that laterally surrounds and contacts first conductive gate cap structure 40 and Planar semiconductor spacer 34 and contacts a portion of the top surface of first planar dielectric spacer 30 . The first dielectric gate spacer 56 contacts the first sidewall of the first semiconductor spacer 34 that is vertically coincident with the first sidewall of the first planar dielectric spacer 30 and the first sidewall of the first planar semiconductor spacer 34 . The second sidewall of the first planar dielectric spacer plate 34 is laterally offset from the second sidewall. The outer sidewalls of the first dielectric gate spacers 56 may vertically coincide with the second sidewalls of the first planar dielectric spacer plate 30 .

The first planar semiconductor spacer 34 may contact the top surface of the first planar dielectric spacer 30 , may have a smaller area than the first planar dielectric spacer 30 , and may contact the first conductive gate cap structure 40 The bottom surface of the second section overlying the stack of first planar dielectric spacers 30 and first planar semiconductor spacers 34 . A portion of the first conductive gate cap structure 40 covers the top surface of the first portion of the shallow trench isolation structure 8 surrounding the portion of the first doped well (5A or 6A) located at the gate structure (12, 14, 30 , 34, 40, 50) and a portion below the first gate dielectric spacer 56. As shown in FIG. 12F , the section 8P1 of the first portion of the deep trench isolation structure 8D located below the first conductive gate cap structure 40 is on the horizontal top surface of the recessed region 8R1 of the first portion of the first trench isolation structure 8D. protrudes upward because the first conductive gate cap structure 40 masks the protrusion of the first portion of the deep trench isolation structure 8D during the anisotropic etching process that vertically recesses the unmasked portion of the trench isolation structure 8 Section 8P. Likewise, as shown in FIG. 12B , the section 8P2 of the first portion of the shallow trench isolation structure 8S below the first conductive gate cap structure 40 is at the level of the recessed region 8R2 of the first portion of the shallow trench isolation structure 8S. Project above the top surface.

A first gate structure (12, 14, 30, 34, including a first gate dielectric 12, a first gate electrode 14, a first planar dielectric spacer 30, and a first conductive gate cap structure 40, 40, 50) overlays the first channel region 15 of the first (eg, low voltage or ultra-low voltage) field effect transistor in regions 100 and 200, as shown in Figure 12C. The first channel region 15 may be a surface portion of the doped well (5, 6) having an area overlap with the first gate structure (12, 14, 30, 34, 40, 50) in plan view. In one embodiment, the first gate dielectric 12 and the first gate electrode 14 include sidewalls extending laterally along the first horizontal direction hd1, vertically coincident with each other, and laterally surrounding the doped well ( The sidewalls of the recessed region 8R2 of a portion of the trench isolation structure 8 of 5, 6) are laterally spaced apart and vertically coincident with the sidewalls of the other region of the trench isolation structure 8.

In one embodiment, the first gate dielectric 12 and the first gate electrode 14 contact the sidewalls of the protruding region (ie, protruding section) 8P2 of the portion of the trench isolation structure 8 . The side wall extends laterally along the first horizontal direction hd1. The first planar dielectric spacer 30 contacts a first portion of the top surface of the first gate electrode 14 and the first conductive gate cap structure 40 includes a first section contacting the first gate electrode 14 a second portion of the top surface of 14; a second section overlying the first planar dielectric spacer 30; and a connection section contacting the first planar dielectric spacer 30 The first side wall connects the first section and the second section.

In one embodiment, first gate dielectric 12 includes first sidewalls contacting sidewalls of protruding region 8P2 of the first portion of trench isolation structure 8 . The first gate electrode 14 includes a first sidewall contacting a sidewall of the protruding region 8P2 of the first portion of the trench isolation structure 8 . The second sidewall of the first gate dielectric 12 and the second sidewall of the first gate electrode 14 extending laterally along the first horizontal direction hd1 contact the side of the lower portion of the first dielectric gate spacer 56 wall. The additional sidewalls of the first gate dielectric 12 and the first gate electrode 14 contact the additional sidewalls of the lower portion of the first dielectric gate spacer 56 along a direction perpendicular to the first horizontal direction hd1 The second horizontal direction hd2 extends laterally.

Second gate structure (10,13) including a second composite silicon nitride/silicon oxide gate dielectric (13,10), a second gate electrode 40 including a second conductive gate cap structure 40 , 40, 50) overlays the second channel region 17 of the second (eg, high voltage) field effect transistor in regions 500 and 600, as shown in Figure 12F.

Referring to FIGS. 13A to 13G , a masked ion implantation process may be performed to inject p-type dopants into the unmasked surface portion of n-type well 6 and to inject n-type dopants into the unmasked surface portion of p-type well 5 . Patterned photoresist layer, gate structures {(12,10,14,13,30,34,40,50) and (10,13,40,50)} and dielectric gate spacers 56 The combination can be used as a composite implant mask during each ion implantation process. Source and drain regions are formed within implanted surface portions of p-doped well 5 and n-doped well 6 . The source and drain regions are collectively referred to as source/drain regions (65, 66), which include p-doped source/drain regions 65 formed within corresponding n-doped wells 6 and n-doped source/drain regions 66 formed within corresponding p-doped wells in p-doped well 5 .

In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high voltage field effect transistors are formed, such as third field effect transistor regions (500, 600). In this case, p-doped source/drain regions 65 may include inner p-doped source/drain regions 65I laterally spaced apart by additional trench isolation structures 8 (eg, deep trench isolation structures 8D) and external p-doped source/drain regions 65O, this additional trench isolation structure may be separate from the trench isolation structure 8 (eg, shallow trench isolation structure 8S) in the first field effect transistor region (100, 200). Additionally, n-doped source/drain regions 66 may include inner n-doped source/drain regions 66I and outer n-doped source/drain regions 66O laterally spaced apart by another additional trench isolation structure 8 . Alternatively, well contact source/drain regions 65W may be employed to facilitate biasing of the doped well.

In one embodiment, the gate electrode 14 located within the low and ultra-low voltage field effect transistor regions (100, 200, 300, 400) may be doped with p-type dopants or n-type dopants to form doped with p-type dopants. doped gate electrode with n-type dopants (25,26). The doped gate electrodes (25, 26) include a p-doped second gate electrode 25 formed in the p-type field effect transistor region (100, 300) and an n-doped second gate electrode 25 formed in the n-type field effect transistor region (200, 400). second gate electrode 26 . Alternatively or in addition, the polysilicon gate electrode 14 and/or the semiconductor may be heavily doped by forming metal on the polysilicon 14 and annealing the metal to form a metal suicide on the exposed top surface of the polysilicon. The conductive gate cap structure 40 is silicided (eg, heavily doped polysilicon).

Generally speaking, various field effect transistor regions (100, 200, 300, 400, 500, 600) can be formed with different gate dielectric thicknesses, different gate lengths (ie, different lateral distances between source and drain regions), and different textures. Various types of field effect transistors.

Referring to FIGS. 14A-14F, contact level dielectric layer 70 and various contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may subsequently be formed. Contact level dielectric layer 70 includes a dielectric material such as silicon oxide, and may be formed by a conformal or non-conformal deposition process. The top surface of contact level dielectric layer 70 may be planarized by a planarization process such as a chemical mechanical polishing (CMP) process. The vertical distance between the topmost surface of the gate cap dielectric 50 and the top surface of the contact level dielectric layer 70 may be in the range of 30 nm to 500 nm, although smaller and larger vertical distances may also be used. .

A contact level dielectric layer 70 overlies and laterally surrounds each of these field effect transistors. In one embodiment shown in Figure 13B, a first portion 14A of the top surface of the first gate electrode (14, 26) of the first field effect transistor in the first transistor region (100, 200) contacts the first planar dielectric spacer Plate 30, second portion 14B of the top surface of first gate electrode 14 contacts a lower portion of conductive gate cap structure 40, and contact level dielectric layer 70 may contact the top of first gate electrode (14, 26) The third part of the surface 14C. The third portion 14C of the top surface of the first gate electrode 14 may be laterally spaced apart from the second portion 14B of the top surface of the first gate electrode 14 by the first portion 14A of the top surface of the first gate electrode 14 .

The contact via structure (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) includes: a first source contacting the source/drain region (65, 66) in the first field effect transistor region (100, 200) The /drain region contacts via structure 76A, as shown in FIG. 14C; the first field effect transistor region (100, 200) contacts the top surface of the lower portion of the conductive gate cap structure 40 laterally offset from the semiconductor plate 34. A gate contact via structure 76G; a second source/drain region contact via structure 86A in the second field effect transistor region (300, 400) that contacts the source/drain region (65, 66); a second field effect transistor region (300, 400) The second gate contact via structure 86G in the transistor area (300,400) contacts the second gate electrode (25,26); the third field effect transistor area (500,600) contacts the source/drain area (65,66) a third source/drain region contact via structure 96A; and a third gate contact via structure 96G within the third field effect transistor region (500, 600) that contacts the top surface of the conductive gate cap structure 40. Additionally, the contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may include a first passive device contact via structure 96R that contacts a first passive device, such as a resistor, and a first passive device contact via structure 96R that contacts a first passive device, such as a resistor. A second passive device of the two passive devices, such as a capacitor, contacts via structure 96C.

Generally speaking, the first field effect transistor may be formed in the first field effect transistor region (100 or 200). The first field effect transistor includes a first active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting the sidewalls of the first portion of the trench isolation structure 8 and formed by A first portion of the trench isolation structure surrounds laterally. The first active region includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. The first field effect transistor may include a first gate structure (12, 14, 25 or 26, 30, 34, 40, 50).

A second field effect transistor may be formed in the second field effect transistor region (300 or 400). The second field effect transistor includes a second active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting the sidewalls of the second portion of the trench isolation structure 8 and laterally surrounded by a second portion of the trench isolation structure. A second gate structure (12, 25 or 26) including a second gate dielectric 12 and a second gate electrode (25 or 26) overlies the second active area. Contact level dielectric layer 70 overlies the first gate structure (12, 14, 25 or 26, 30, 34, 40, 50) and the second gate structure (12, 25 or 26). At least one gate contact structure, such as second gate contact via structure 86G, contacts a portion of the top surface of the second gate electrode (25 or 26). The entire top surface of the second gate electrode (25 or 26) that is not in contact with the at least one gate contact structure 86G is in contact with the contact level dielectric layer 70.

The first exemplary structure may include additional field effect transistors, such as a third field effect transistor formed in the third field effect transistor region (500 or 600). The additional field effect transistor includes an additional active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting the sidewalls of the additional portion of the trench isolation structure 8 and being isolated by the trench Additional parts of the structure surround it laterally. Additional field effect transistors include additional gate structures (10, 13, 40, 50) overlying the additional active regions. The additional gate structures (10, 13, 40, 50) may include an additional composite gate dielectric and an additional conductive gate cap structure 40, the additional composite gate dielectric having a higher density than the first gate dielectric. The additional conductive gate cap structure has the same thickness and the same material composition as the first section of the first conductive gate cap structure 40. The entire top surface of silicon nitride portion 13 is in contact with the bottom surface of additional conductive gate cap structure 40 .

In one embodiment, the first exemplary structure may also include a passive device, which may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device includes a layer stack that includes, from bottom to top, a first dielectric layer (such as another example of silicon oxide gate dielectric 12 and silicon nitride portion 13), a second dielectric layer (such as a planar dielectric spacers 30), semiconductor plates (such as planar semiconductor spacers 34), and metal plates (such as conductive gate cap structure 40). The second dielectric layer has the same material composition and the same thickness as the first planar dielectric spacer plate 30 . The metal plate has the same material composition and the same thickness as the first section of the first conductive gate cap structure 40 .

Referring to FIGS. 15A to 15F , a second embodiment according to the present disclosure may be obtained from the first exemplary structure of FIGS. 5A to 5F by rearranging and/or omitting a subset of the doped wells ( 5 , 6 ). Two exemplary structures. For example, in a first embodiment, first p-doped well 5A may extend into the area of region 100 occupied by first n-doped well 6A. Alternatively, in the first embodiment, the first n-doped well 6A may extend into the area of region 200 occupied by the first p-doped well 5A. In the configuration shown in FIG. 15B , the first p-doped well 5A may be formed such that a plurality of active regions laterally surrounded by corresponding portions of the trench isolation structure 8 are provided within the first n-type field effect transistor region 200 . The first p-type field effect transistor region 100 is not shown in the figure of the second exemplary structure, but may be present within the second exemplary structure. Although the present disclosure has been described in terms of embodiments in which there are multiple pairs of active regions within the first n-type field effect transistor region 200 , it is expressly contemplated herein that there are multiple pairs of active regions in the first p-type field effect transistor region 100 . source region and form an implementation of a field effect transistor with the same geometric characteristics in the first p-type field effect transistor region 100 . In other words, devices of the present disclosure may be formed with opposite conductivity types.

Generally speaking, at least one gate dielectric layer and at least one semiconductor gate material layer may be formed over the semiconductor material layer in the semiconductor substrate 2 and may pass through the at least one semiconductor gate material layer and the at least one gate material layer. The polar dielectric layer forms the trench isolation structure 8 . As shown in FIGS. 15A and 15B , the at least one semiconductor gate material layer and the patterned portion of the at least one gate dielectric layer include a first gate dielectric covering the first active region 51 of the semiconductor material layer. First stack (22A, 24A) of plate 22A and first gate electrode material plate 24A, and second gate dielectric plate 22B and second gate electrode overlying second active region 52 of semiconductor material layer Second stack (22B, 24B) of material sheets 24B.

The first stack (22A, 24A) and the second stack (22B, 24B) may be located within the same field effect transistor region, such as first n-type field effect transistor region 200. The trench isolation structure 8 includes a frame portion 8F that continuously and laterally surrounds the first active region 51 and the second active region 52 . The lateral extension portion 8L of the trench isolation structure 8 may be located between the first active region 51 and the second active region 52 .

Referring to Figures 16A-16F, a masked ion implantation process may be performed to dope any portion of the gate electrode material plate 24 to have a suitable conductivity type. In an illustrative example, a plate of n-doped gate electrode material 126 may be formed in the first and second n-type field effect transistor regions (200, 400), and a plate of p-doped gate electrode material 125 may be formed in the second p-type field effect transistor region (200, 400). p-type field effect transistor region 300 and a first p-type field effect transistor region (not shown).

Referring to Figures 17A-17F, the process steps of Figures 6A-6F may be performed to form planar dielectric spacers 30L and planar over the top surfaces of gate electrode material plates (125, 126), plate 23, and trench isolation structure 8 Semiconductor spacer layer 34L. The thickness and material composition of each of planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L may be the same as in the first exemplary structure.

Referring to Figures 18A-18F, the process steps of Figures 7A-7F may be performed to pattern planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L. In a second embodiment, planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L may be patterned such that planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L remain in the second field effect transistor region (300, 400) and in the passive device area (700,800) and removed from the first field effect transistor area (100,200) and the third field effect transistor area (500,600). In this case, the first active region and the second active region may be disposed within the first n-type field effect transistor region 200, and the remaining portions of the planar dielectric spacer layer 30L and the planar semiconductor spacer layer 34L may be located in the first n-type field effect transistor region 200. outside the area of the first active area 51 and the second active area 52 .

Referring to FIGS. 19A-19F , the processing steps of FIGS. 8A-8F may be performed directly on the physically exposed top surfaces of gate electrode material plate 126 , plate 23 and trench isolation structure 8 and on planar semiconductor spacer layer 34 A layer of conductive gate connection material including metallic material is deposited above. In one embodiment, the conductive gate connection material layer may include a conductive gate cap layer 40L, which may have the same material composition and the same thickness range as in the first exemplary structure. Gate cap dielectric layer 50L may then be deposited over conductive gate cap layer 40L. Gate cap dielectric layer 50L includes a dielectric material, such as silicon nitride.

Referring to Figures 20A-20F, a first photoresist layer 53 can be applied over the second example structure and can be photolithographically patterned to form discrete patterned photoresist material portions. The patterned portion of first photoresist layer 53 may include a first portion that defines the shape of a gate structure that will subsequently be formed in first field effect transistor region (100, 200). The patterned portion of the first photoresist layer 53 may include a second layer defining a shape of a gate electrode that will subsequently be formed in the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600 . part. The patterned portion of the first photoresist layer 53 may include additional portions covering corresponding areas within the first passive device region 700 and the second passive device region 800 .

A first anisotropic etch process may be performed to transfer the pattern in first photoresist layer 53 through gate cap dielectric layer 5OL, conductive gate cap layer 4OL, planar semiconductor spacer layer 34L and portions of plate 23 outside the area of planar dielectric spacer layer 30L, which portions are located within third p-type field effect transistor region 500 and third n-type field effect transistor region 600 . Planar dielectric spacer layer 30L, second gate dielectric plate 20 and trench isolation structure 8 may serve as etch stop structures for the first anisotropic etching process. In the case where planar dielectric spacer layer 30L, second gate dielectric plate 20 and trench isolation structure 8 include silicon oxide, the etch chemistry of the termination step of the first anisotropic etch process may be selective to silicon oxide. The planar semiconductor spacer layer 34L and the semiconductor material of the silicon nitride plate 23 are etched.

Each patterned portion of gate cap dielectric layer 50L includes gate cap dielectric 50 . Each patterned portion of conductive gate cap layer 40L includes conductive gate cap structure 40 . Each patterned portion of planar semiconductor spacer layer 34L includes planar semiconductor spacer plate 34 . Each patterned portion of the plate of gate electrode material 126 includes a gate electrode 116 .

Generally speaking, the first gate electrode material plate 126 may be disposed on the first active region 51 and the second gate electrode material plate 126 may be disposed on the second active region 52 through Portion 8L of trench isolation structure 8 is spaced apart from the first active region. Portions of the first gate electrode material plate 126 and the second gate electrode material plate 126 may be anisotropically etched. The patterned portions of the first and second gate electrode material plates 126 , 126 respectively include first and second gate electrodes 116 , 116 .

According to one aspect of the invention, the sidewalls of the conductive gate cap structure 40 may be formed adjacent the sidewalls of the planar semiconductor spacer layer 34L formed in the processing steps of FIGS. 18A-18F such that the conductive gate cap structure The vertically extending portion of structure 40 adjacent the sidewalls of planar semiconductor spacer layer 34L is included within conductive gate cap structure 40 . Generally speaking, the conductive gate cap structure 40 formed within the first field effect transistor region (100, 200) may be formed to have a vertical protruding portion, the vertical protruding portion being formed with the conductive gate cap layer 40L. The remainder of the vertically extending portion adjacent the sidewalls of the planar semiconductor spacer layer 34L formed in the processing steps of FIGS. 18A to 18F .

The contiguous combination of first gate cap dielectric 50, first conductive gate cap structure 40, first planar semiconductor spacer 34, and pair of first gate electrodes 116 may span the first n-type field effect transistor region A pair of active regions (51,52) in 200 is formed. Generally speaking, each first conductive gate cap structure 40 forms a conductive gate connection structure that provides a conductive path between an underlying pair of first gate electrodes 116 . A pole electrode overlies the pair of active regions (51, 52) separated by trench isolation structure 8L. Accordingly, the conductive gate connection material layer including the conductive gate cap layer 40L may be patterned into a conductive gate connection structure including the first conductive gate cap structure 40 . The first photoresist layer 53 may then be removed, for example by ashing.

Referring to FIGS. 21A-21F , a second photoresist layer 57 may be applied over the second exemplary structure and may be photolithographically patterned to provide patterned photoresist material portions that pattern the photoresist material portions. The resist material portion has the shape of the gate electrode that will subsequently be formed in the second p-type field effect transistor region 300 and the second n-type field effect transistor region 400 . The shape of the patterned portion of the second photoresist layer 57 can be selected as desired. In one embodiment, the patterned portion of second photoresist layer 57 may have raised sections adjacent the interface between the active area and trench isolation structure 8 .

22A-22G, a second anisotropic etch process may be performed to transfer the pattern of second photoresist layer 57 through planar dielectric spacer layer 30L, gate electrode material plates (126, 125), and Gate dielectric plate 22. Each patterned portion of planar dielectric spacer layer 30L constitutes planar dielectric spacer plate 30 . Each patterned portion of a plate of gate electrode material (126, 125) constitutes a gate electrode (116, 115). Each patterned portion of gate dielectric plate 22 constitutes gate dielectric 12 . The terminal portion of the second anisotropic etching process may be selective to the semiconductor material of the semiconductor substrate 2 . The second photoresist layer 57 may then be removed, for example by ashing.

Subsequently, another anisotropic etch process may optionally be performed to pattern the gate dielectric plate 22 within the first field effect transistor region (100, 200). Portions of the gate dielectric plate 22 that are not underlying the gate electrode 126 may be etched, and the remaining portions of the gate dielectric plate 22 in the first field effect transistor region ( 100 , 200 ) constitute the gate dielectric 12 .

The stack of first gate dielectric 12 and first gate electrode 116 overlies the first channel region within the first active region 51 in the first field effect transistor region (100 or 200) and contacts the trench. The first side wall of the laterally extending portion 8F of the slot isolation structure 8 . The stack of second gate dielectric 12 and second gate electrode 116 overlies the second channel region within second active region 52 and contacts the second side of lateral extension 8F of trench isolation structure 8 wall. The conductive gate connection structure (including the first conductive gate cap structure 40 ) contacts the top surface of the first gate electrode 116 , the top surface of the second gate electrode 116 and the top of the lateral extension 8F of the trench isolation structure 8 part of the surface. The conductive gate connection structure including the first conductive gate cap structure 40 includes a pair of lateral sidewalls extending transversely along the first horizontal direction hd1 and a pair of longitudinal sidewalls extending transversely along the second horizontal direction hd2.

Trench isolation structure 8 includes a frame portion 8F that continuously and laterally surrounds the first active region and the second active region. The conductive gate connection structure including the first conductive gate cap structure 40 includes a first end portion and a second end portion covering a top surface of the frame portion 8F of the trench isolation structure 8 above and in contact with the corresponding section. The longitudinal side walls of the first gate electrode 116 and the second gate electrode 116 vertically coincide with the pair of longitudinal side walls of the conductive gate connection structure extending laterally along the second horizontal direction hd2.

The first lateral sidewall of the first gate dielectric 12 (extending along the first horizontal direction hd1 ) and the first lateral sidewall of the first gate electrode 116 (extending along the first horizontal direction hd1 ) are perpendicular to each other. overlap and contact the first side wall of the lateral extension portion 8L of the trench isolation structure 8 . The first longitudinal sidewall of the second gate dielectric 12 (extending along the first horizontal direction hd1 ) and the first lateral sidewall (extending along the first horizontal direction hd1 ) of the second gate electrode 116 are perpendicular to each other. overlap and contact the second side wall of the laterally extending portion 8L of the trench isolation structure 8 .

The second longitudinal sidewall of the first gate dielectric 12 (extending along the first horizontal direction hd1 ) and the second lateral sidewall (extending along the first horizontal direction hd1 ) of the first gate electrode 116 are perpendicular to each other. overlap and contact the first side wall of the frame portion 8F of the trench isolation structure 8 . The second longitudinal sidewall of the second gate dielectric 12 (extending along the first horizontal direction hd1 ) and the second lateral sidewall (extending along the first horizontal direction hd1 ) of the second gate electrode 116 are perpendicular to each other. overlap and contact the second side wall of the frame portion 8F of the trench isolation structure 8 .

In one embodiment, the conductive gate connection structure includes a metal gate connection structure 40 over the main section of the first gate electrode 116 and over the lateral extension 8L of the trench isolation structure 8 and a first thickness over the entire area of second gate electrode 116 and a second thickness greater than the first thickness over complementary sections of first gate electrode 116 .

Referring to Figures 23A-23G, source/drain extension regions (not shown) may optionally be implanted using a corresponding patterned implant mask layer (such as a patterned photoresist layer) and a corresponding ion implantation process. It is formed by injecting p-type dopants and n-type dopants. The dielectric gate spacer material layer including the dielectric material may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The dielectric material of the dielectric gate spacer material layer may include, for example, silicon nitride and/or silicon oxide. An anisotropic etching process may be performed to etch horizontally extending portions of the dielectric gate spacer material layer. The remaining vertical extensions of the layer of dielectric gate spacer material constitute dielectric gate spacers 56 .

The anisotropic etching process can be extended to etch unmasked portions of the dielectric material of the second gate dielectric plate 20 and the trench isolation structure 8 selectively with respect to the material of the gate electrode 116 . The planar dielectric spacer 30 in the second field effect transistor region (300, 400) may be etched in parallel during the anisotropic etch process. In this case, the second gate dielectric plate 20 in the third field effect transistor region (500, 600) may be patterned with the second gate dielectric 10 and the top of the trench isolation structure 8 physically exposed The surface may be vertically concave. In one embodiment, the outer sidewalls of each second gate dielectric 10 may vertically coincide with the outer sidewalls of a corresponding one of the gate spacers 56 . In one embodiment, the recessed portion of the top surface of trench isolation structure 8 may be at or about the height of the top surface of the third doped well (5C, 6C) in the third field effect transistor region (500, 600).

In one embodiment, first dielectric gate spacer 56 located within first field effect transistor region (100 or 200) includes an upper portion laterally surrounding a conductive gate connection structure including first conductive gate cap structure 40 portion, and extends vertically between a horizontal plane including the top surface of the frame portion 8F of the trench isolation structure 8 and a horizontal plane including the top surface of the first active region and the second active region and contacts the first gate Four lower portions of respective longitudinal sidewalls of one of electrode 116 and second gate electrode 116 .

Referring to FIGS. 24A to 24G , a masked ion implantation process may be performed to inject p-type dopants into the unmasked surface portion of n-type well 6 and to inject n-type dopants into the unmasked surface portion of p-type well 5 . The combination of patterned photoresist layer, gate structure (12, 10, 116, 115, 13, 34, 40, 50) and dielectric gate spacer 56 can be used as a composite implant mask during each ion implantation process. Source and drain regions are formed within implanted surface portions of p-doped well 5 and n-doped well 6 . The source and drain regions are collectively referred to as source/drain regions (65, 66), which include p-doped source/drain regions 65 formed within corresponding n-doped wells 6 and n-doped source/drain regions 66 formed within corresponding p-doped wells in p-doped well 5 .

In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high voltage field effect transistors are formed, such as third field effect transistor regions (500, 600). In this case, p-doped source/drain regions 65 may include inner p-doped source/drain regions 65I and outer p-doped source/drain regions laterally spaced apart by additional trench isolation structures 8 Region 65O, this additional trench isolation structure may be separated from the trench isolation structure 8 in the first field effect transistor region (100, 200). Additionally, n-doped source/drain regions 66 may include inner n-doped source/drain regions 66I and outer n-doped source/drain regions 66O laterally spaced apart by another additional trench isolation structure 8 . Alternatively, well contact source/drain regions 65W may be employed to facilitate biasing of the doped well.

Referring to Figures 25A-25F, contact level dielectric layer 70 and various contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may subsequently be formed. Contact level dielectric layer 70 includes a dielectric material such as silicon oxide, and may be formed by a conformal or non-conformal deposition process. The top surface of contact level dielectric layer 70 may be planarized by a planarization process such as a chemical mechanical polishing (CMP) process. The vertical distance between the topmost surface of the gate cap dielectric 50 and the top surface of the contact level dielectric layer 70 may be in the range of 30 nm to 500 nm, although smaller and larger vertical distances may also be used. .

The contact via structure (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) includes: a first source contacting the source/drain region (65, 66) in the first field effect transistor region (100, 200) /Drain region contact via structure 76A; first gate contact via structure 76G in first field effect transistor region (100, 200) contacting the top surface of conductive gate cap structure 40; second field effect transistor region (300, 400 ) second source/drain region contact via structure 86A contacting the source/drain region (65, 66); second gate contact via structure 86G contacting the second gate electrode (25, 26) ;The third source/drain region contact via structure 96A in the third field effect transistor region (500,600) contacting the source/drain region (65,66); and the third field effect transistor region (500,600) in contact The third gate contact via structure 96G of the top surface of the conductive gate cap structure 40 . Additionally, the contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may include a first passive device contact via structure 96R that contacts a first passive device, such as a resistor, and a first passive device contact via structure 96R that contacts a first passive device, such as a resistor. A second passive device of the two passive devices, such as a capacitor, contacts via structure 96C.

Generally speaking, various field effect transistor regions (100, 200, 300, 400, 500, 600) can be formed with different gate dielectric thicknesses, different gate lengths (ie, different lateral distances between source and drain regions), and different textures. Various types of field effect transistors. Dielectric gate spacers 56 may overlie peripheral regions of the source/drain regions (65, 66) of the field effect transistors in the second field effect transistor region (300, 400) and contact corresponding portions of the trench isolation structure 8 part of the side wall.

The second exemplary structure may include a combination of first field effect transistors and second field effect transistors located in the first field effect transistor region (100 or 200). The first field effect transistor and the second field effect transistor include a first active region 51 and a second active region 52 respectively. The first active region and the second active region contact the sidewalls of the trench isolation structure 8 and are laterally surrounded by the trench isolation structure. The lateral extension portion 8L of the trench isolation structure 8 is located between the first active region 51 and the second active region 52 .

The second exemplary structure may include a third field effect transistor located in the second field effect transistor region (300 or 400). The third field effect transistor includes: a third active region laterally surrounded by an additional portion of the trench isolation structure 8; a third gate dielectric 12 and a third gate electrode (116 or 115) a stack having lateral sidewalls contacting additional portions of the trench isolation structure 8 and extending laterally along the first horizontal direction hd1; additional dielectric gate spacers 56 having A respective subset of the sidewalls having respective openings therethrough and contacting the additional portion of the trench isolation structure 8 and the respective longitudinal sidewalls of the third gate electrode (116 or 115) (extending laterally along the second horizontal direction hd2) .

The first gate electrode 116 and the second gate electrode 116 are not in contact with the contact level dielectric layer 70 and are connected through the first dielectric gate spacer 56 and the conductive gate connection structure (embodied as the conductive gate cap structure 40 ). Spaced apart from contact level dielectric layer 70 . The third gate electrode (116 or 115) may have the same thickness as the first gate electrode 116 and the second gate electrode 116. A portion of the top surface of the third gate electrode (116 or 115) is in direct contact with the contact level dielectric layer 70.

At least one gate contact structure, such as first gate contact via structure 76G, extends through contact level dielectric layer 70 and contacts a top surface of the portion of the conductive gate connection structure that includes at least a portion of conductive gate cap structure 40 groundly overlying underlying first gate electrode 116 and at least one additional gate contact structure (such as second gate contact via structure 86G) extending through contact level dielectric layer 70 and contacts a portion of the top surface of the third gate electrode 116 . The entire top surface of third gate electrode 116 is in contact with at least one additional gate contact structure or contact level dielectric layer 70 .

The second example structure may include additional field effect transistors, such as a fourth field effect transistor formed in the third field effect transistor region (500 or 600). The additional field effect transistor includes an additional active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting the sidewalls of the additional portion of the trench isolation structure 8 and being isolated by the trench Additional parts of the structure surround it laterally. Additional field effect transistors include additional gate structures (10, 13, 40, 50) overlying the additional active regions. The additional gate structures (10, 13, 40, 50) may include an additional composite gate dielectric (10, 13) and an additional conductive gate cap structure 40, the additional composite gate dielectric having a higher conductivity than the first A greater thickness of the silicon oxide sub-layer 10 and a silicon nitride sub-layer 13 of the gate dielectric 12, the additional conductive gate cap structure having the same thickness and the same material composition. The entire top surface of silicon nitride sub-layer 13 is in contact with the bottom surface of additional conductive gate cap structure 40 .

In one embodiment, the second exemplary structure may include a passive device that may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device includes a layer stack that includes, from bottom to top, a first dielectric layer (such as another example of silicon oxide gate dielectric 12 and silicon nitride gate dielectric 13 ), a second dielectric layer layer (such as planar dielectric spacer plate 30), a second semiconductor plate (such as planar semiconductor spacer plate 34), and a metal plate (such as conductive gate cap structure 40). The first dielectric layer has the same material composition and the same thickness as the first gate dielectric 12 . The first semiconductor plate may have the same thickness as the first gate electrode (14, 25 or 26). The second dielectric layer has the same material composition and the same thickness as the first planar dielectric spacer plate 30 . The metal plate has the same material composition and the same thickness as the first section of the first conductive gate cap structure 40 .

Referring to FIGS. 26A-26B , a third embodiment according to the present disclosure may be obtained from the first exemplary structure of FIGS. 5A-5F by rearranging and/or omitting a subset of the doped wells ( 5 , 6 ). Three exemplary structures. For example, the first p-doped well 5A may be formed such that a plurality of active regions laterally surrounded by corresponding portions of the trench isolation structure 8 are provided within the first n-type field effect transistor region 200 . The second field effect transistor region (300 or 400) may be formed adjacent to the first field effect transistor region (100 or 200). The first p-type field effect transistor region 100 and the second n-type field effect transistor region 400 are not shown in the drawings of the third exemplary structure, but may be present within the third exemplary structure. Although the present disclosure has been described in terms of embodiments in which there are multiple pairs of active regions within the first n-type field effect transistor region 200 , it is expressly contemplated herein that there are multiple pairs of active regions in the first p-type field effect transistor region 100 . source region and form an implementation of a field effect transistor with the same geometric characteristics in the first p-type field effect transistor region 100 . In other words, devices of the present disclosure may be formed with opposite conductivity types.

Generally speaking, at least one gate dielectric layer and at least one semiconductor gate material layer may be formed over the semiconductor material layer in the semiconductor substrate 2 and may pass through the at least one semiconductor gate material layer and the at least one gate material layer. The polar dielectric layer forms the trench isolation structure 8 . The at least one semiconductor gate material layer and the patterned portion of the at least one gate dielectric layer include a first gate dielectric plate 22 and a first gate electrode material overlying the first active region of the semiconductor material layer. a first stack (22, 24) of plates 24, and a second stack (22, 22, 24) of a second gate dielectric plate 22 and a second gate electrode material plate 24 overlying the second active region of the semiconductor material layer. twenty four). The first stack (22, 24) and the second stack (22, 24) may be located within the same field effect transistor region, such as first n-type field effect transistor region 200. Trench isolation structure 8 includes a frame portion 8F that continuously and laterally surrounds the first active region and the second active region. Laterally extending portion 8L of trench isolation structure 8 may be located between the first active region and the second active region. Alternatively, a masked ion implantation process may be performed to dope any portion of the gate electrode material plate 24 to have a suitable conductivity type.

Referring to FIGS. 27A and 27B , the process steps of FIGS. 6A through 6F may be performed to form planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L over the top surface of gate electrode material plate 24 and trench isolation structure 8 . The thickness and material composition of each of planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L may be the same as in the first exemplary structure.

Referring to Figures 28A-28F, the process steps of Figures 7A-7F may be performed to pattern planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L. In a third embodiment, planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L may be patterned such that sidewalls of the patterned remaining portions of planar dielectric spacer layer 30L and planar semiconductor spacer layer 34L are formed in the second field effect transistor area (300 or 400). Planar interposers may be removed from peripheral areas of the first field effect transistor area (100,200), the third field effect transistor area (500,600), and the second field effect transistor area (300,400) adjacent to the first field effect transistor area (100,200). Electrical spacer layer 30L and planar semiconductor spacer layer 34L. In this case, the first active region and the second active region may be disposed within the first n-type field effect transistor region 200, and the remaining portions of the planar dielectric spacer layer 30L and the planar semiconductor spacer layer 34L may be located in the first n-type field effect transistor region 200. outside the area of the first active area and the second active area. In one embodiment, the sidewalls of the planar semiconductor spacer layer 34L may be perpendicular to the direction of the gate electrode to be patterned in the second field effect transistor region (300, 400). For example, the sidewalls of the planar semiconductor spacer layer 34L may be parallel to the first horizontal direction hd1.

Referring to FIGS. 29A-29F , the process steps of FIGS. 8A-8F may be performed to deposit conductive materials directly on the gate electrode material plate 24 and the physically exposed top surface of the trench isolation structure 8 and above the planar semiconductor spacer layer 34 Gate connection material layers (234L, 236L). In one embodiment, the conductive gate connection material layers (236L, 240L) may include a vertical stack including, from bottom to top, a semiconductor gate capping layer 236L and an optional conductive gate capping layer 240L, The semiconductor gate capping layer includes heavily doped semiconductor material. The heavily doped semiconductor material may include a doped semiconductor material such as polysilicon, and may have the same type of doping as the underlying gate electrode material plate 24 . If multiple gate electrode material plates 24 with different conductivity types are employed, different portions of the semiconductor gate capping layer 236L may be doped with electrical dopants of different conductivity types to match the corresponding underlying gate electrode materials. The conductivity type of plate 24. The thickness of semiconductor gate capping layer 236L may be in the range of 30 nm to 300 nm, such as 40 nm to 100 nm, although smaller and larger thicknesses may also be used. The conductive gate cap layer 240L may have the same material composition and the same thickness range as the conductive gate cap layer 40 in the first exemplary structure. Conductive gate capping layer 240L may include a metal suicide layer. Alternatively, the conductive gate capping layer 240L may be omitted in this step and then formed by silicide of the upper surface of the gate electrode in a subsequent step. Optionally, a gate cap dielectric layer (not shown) may be subsequently deposited over conductive gate cap layer 240L. The gate cap dielectric layer includes a dielectric material such as silicon nitride. The gate cap dielectric layer, if present, may have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 50 nm), although smaller and larger thicknesses may also be used.

Referring to Figures 30A-30B, a first photoresist layer 53 may be applied over the third example structure and may be photolithographically patterned to form discrete patterned photoresist material portions. The patterned portion of first photoresist layer 53 may include openings in the second field effect transistor region (300 and/or 400). A first anisotropic etch process may be performed to transfer the pattern in first photoresist layer 53 through the optional gate cap dielectric layer (if present), conductive gate cap layer 240L , a semiconductor gate capping layer 236L and a planar semiconductor spacer layer 34L. The first anisotropic etch process may be selective to the dielectric material of planar dielectric spacer layer 30L.

Referring to FIGS. 31A and 31B , a second photoresist layer 57 may be applied over the third exemplary structure and may be photolithographically patterned to provide shapes with gate electrodes and passive devices that will subsequently be formed. part of the patterned photoresist material. The shape of the patterned portion of the second photoresist layer 57 can be selected as desired. In one embodiment, the patterned portion of the second photoresist layer 57 may have extended across the edge of the planar semiconductor spacer layer 34L and across the edge of a portion of the conductive gate connection material layers (234L, 240L), This portion overlies the peripheral portion of the planar semiconductor spacer layer 34L within the second field effect transistor region (300 and/or 400).

Referring to FIGS. 32A-32D , a second anisotropic etch process may be performed to transfer the pattern of second photoresist layer 57 through the dielectric gate capping layer (if present), the conductive gate connections Material layers (234L, 240L), planar semiconductor spacer layer 34L, planar dielectric spacer layer 30L, gate electrode material plate 24 and gate dielectric plate 22. Each patterned portion of conductive gate cap layer 240L constitutes conductive gate cap structure 240 . Each patterned portion of semiconductor gate cap layer 236L constitutes semiconductor gate cap structure 236 . Each patterned portion of the planar semiconductor spacer layer 34L constitutes the planar semiconductor spacer plate 34 . Each patterned portion of planar dielectric spacer layer 30L constitutes planar dielectric spacer plate 30 . Each patterned portion of the plate of gate electrode material 24 includes a gate electrode 14 . Each patterned portion of gate dielectric plate 22 constitutes gate dielectric 12 . The terminal portion of the second anisotropic etching process may be selective to the semiconductor material of the semiconductor substrate 2 . The second photoresist layer 57 may then be removed, for example by ashing.

The stack of first gate dielectric 12 and first gate electrode 14 overlies the first channel region within the first active region 51 in the first field effect transistor region (100 or 200) and contacts the trench. The first side wall of the laterally extending portion 8F of the slot isolation structure 8 . The stack of second gate dielectric 12 and second gate electrode 14 overlies the second channel region within second active region 52 and contacts the second side of lateral extension 8F of trench isolation structure 8 wall. The first conductive gate connection structure including the semiconductor gate cap structure 236 and the conductive gate cap structure 240 contacts the top surface of the first gate electrode 14 , the top surface of the second gate electrode 14 and the trench isolation structure 8 A portion of the top surface of the laterally extending portion 8F. The first conductive gate connection structure including the first conductive gate cap structure 240 includes a pair of lateral sidewalls extending transversely along the first horizontal direction hd1 and a pair of longitudinal sidewalls extending transversely along the second horizontal direction hd2 . The entire top surface of the first gate electrode 14 and the entire top surface of the second gate electrode 14 contact the bottom surface of the conductive gate connection structure (236, 240), such as the bottom surface of the semiconductor gate cap structure 236.

The trench isolation structure 8 includes a frame portion 8F that continuously and laterally surrounds the first active region 51 and the second active region 52 . The first conductive gate connection structure included as a stack of semiconductor gate cap structure 236 and conductive gate cap structure 240 includes a first end portion and a third end portion covering the trench. Above and in contact with a corresponding section of the top surface of the frame portion 8F of the isolation structure 8, as shown in Figure 32A. The longitudinal side walls of the first gate electrode 14 and the second gate electrode 14 vertically coincide with the pair of longitudinal side walls of the first conductive gate connection structure extending laterally along the second horizontal direction hd2.

The first lateral sidewall of the first gate dielectric 12 (extending along the first horizontal direction hd1 ) and the first lateral sidewall of the first gate electrode 14 (extending along the first horizontal direction hd1 ) are perpendicular to each other. overlap and contact the first side wall of the lateral extension portion 8L of the trench isolation structure 8 . The first longitudinal sidewall of the second gate dielectric 12 (extending along the first horizontal direction hd1 ) and the first lateral sidewall (extending along the first horizontal direction hd1 ) of the second gate electrode 14 are perpendicular to each other. overlap and contact the second side wall of the laterally extending portion 8L of the trench isolation structure 8 .

The second longitudinal sidewall of the first gate dielectric 12 (extending along the first horizontal direction hd1 ) and the second lateral sidewall of the first gate electrode 14 (extending along the first horizontal direction hd1 ) are perpendicular to each other. overlap and contact the first side wall of the frame portion 8F of the trench isolation structure 8 . The second longitudinal sidewall of the second gate dielectric 12 (extending along the first horizontal direction hd1 ) and the second lateral sidewall (extending along the first horizontal direction hd1 ) of the second gate electrode 14 are perpendicular to each other. directly coincide with and contact the second side wall of the frame portion 8F of the trench isolation structure 8 .

In one embodiment, the first conductive gate connection structure includes a metal gate connection structure included over the entire first gate electrode 14 including a major section of the first gate electrode 14 , a conductive gate cap structure 240 having a uniform thickness over the lateral extension 8L of the trench isolation structure 8 and over the entire second gate electrode 14 .

In one embodiment, the first conductive gate connection structure further includes a semiconductor gate connection structure including a semiconductor gate cap structure 236 having a uniform thickness overall and contacting the first A gate electrode 14 , a lateral extension of the trench isolation structure 8L and a top surface of the second gate electrode 14 . In one embodiment, the first conductive gate connection structure further includes a metal gate connection structure including a conductive gate cap structure 240 that contacts the semiconductor gate connection structure. the entire top surface and has the same area as the semiconductor gate structure.

According to an aspect of the present disclosure, a second conductive gate connection structure may be disposed within the second field effect transistor region (300 and/or 400). The second conductive gate connection structure includes a stack of a second semiconductor gate cap structure 236 and a second conductive gate cap structure 240 . The second semiconductor gate cap structure 236 includes a first section contacting a portion of the top surface of the underlying gate electrode 14 and a second section overlying a planar dielectric spacer. above the plate 34; and a connection section that contacts the first side wall of the planar dielectric spacer plate 34 and connects the first section and the second section.

Referring to FIGS. 33A-33B , the source/drain extension regions (not shown) may optionally be implanted using a corresponding patterned implant mask layer (such as a patterned photoresist layer) and a corresponding ion implantation process. It is formed by injecting p-type dopants and n-type dopants. The dielectric gate spacer material layer including the dielectric material may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The dielectric material of the dielectric gate spacer material layer may include, for example, silicon nitride and/or silicon oxide. An anisotropic etching process may be performed to etch horizontally extending portions of the dielectric gate spacer material layer. The remaining vertical extensions of the layer of dielectric gate spacer material constitute dielectric gate spacers 56 .

The anisotropic etch process can be extended to etch unmasked portions of the dielectric material of the first gate dielectric 12 , the second gate dielectric plate 20 and the trench isolation structure 8 selectively to the material of the gate electrode 14 . The planar dielectric spacer 30 in the second field effect transistor region (300, 400) may be etched in parallel during the anisotropic etch process. In this case, the second gate dielectric plate 20 in the third field effect transistor region (500, 600) may be patterned with the second gate dielectric 10 and the top of the trench isolation structure 8 physically exposed The surface may be vertically concave. In one embodiment, the outer sidewalls of each second gate dielectric 10 may vertically coincide with the outer sidewalls of a corresponding one of the gate spacers 56 . In one embodiment, the recessed portion of the top surface of trench isolation structure 8 may be at or about the height of the top surface of the third doped well (5C, 6C) in the third field effect transistor region (500, 600).

In one embodiment, the first dielectric gate spacer 56 located within the first field effect transistor region (100 or 200) includes a lateral surround including the semiconductor gate cap structure 236 and the conductive gate cap structure 240. an upper portion of the conductive gate connection structure of the stack), and between a horizontal plane including the top surface of the frame portion 8F of the trench isolation structure 8 and a horizontal plane including the top surface of the first active region and the second active region extending vertically between each other, contacting the respective longitudinal sidewalls of one of the first gate electrode 14 and the second gate electrode 14 and contacting the top surface of the respective one of the first and second active regions Four lower sections.

Referring to FIGS. 34A to 34D , a masked ion implantation process may be performed to inject p-type dopants into the unmasked surface portion of n-type well 6 and to inject n-type dopants into the unmasked surface portion of p-type well 5 . The combination of patterned photoresist layer, gate structure (12, 10, 14, 30, 34, 236, 240) and dielectric gate spacer 56 can be used as a composite implant mask during each ion implantation process. Source and drain regions are formed within implanted surface portions of p-doped well 5 and n-doped well 6 . The source and drain regions are collectively referred to as source/drain regions (65, 66), which include p-doped source/drain regions 65 formed within corresponding n-doped wells 6 and n-doped source/drain regions 66 formed within corresponding p-doped wells in p-doped well 5 .

In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high voltage field effect transistors are formed, such as third field effect transistor regions (500, 600). In this case, p-doped source/drain regions 65 may include inner p-doped source/drain regions 65I and outer p-doped source/drain regions laterally spaced apart by additional trench isolation structures 8 Region 65O, this additional trench isolation structure may be separated from the trench isolation structure 8 in the first field effect transistor region (100, 200). Additionally, n-doped source/drain regions 66 may include inner n-doped source/drain regions 66I and outer n-doped source/drain regions 66O laterally spaced apart by another additional trench isolation structure 8 . Alternatively, well contact source/drain regions 65W may be employed to facilitate biasing of the doped well.

Referring to Figures 35A and 35B, contact level dielectric layer 70 and various contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may subsequently be formed. Contact level dielectric layer 70 includes a dielectric material such as silicon oxide, and may be formed by a conformal or non-conformal deposition process. The top surface of contact level dielectric layer 70 may be planarized by a planarization process such as a chemical mechanical polishing (CMP) process. The vertical distance between the topmost surface of the gate cap dielectric 50 and the top surface of the contact level dielectric layer 70 may be in the range of 30 nm to 500 nm, although smaller and larger vertical distances may also be used. .

The contact via structure (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) includes: a first contact source/drain region (65, 66) in the first field effect transistor region (100 or 200) Source/drain region contact via structure 76A; first gate contact via structure 76G within first field effect transistor region (100 or 200) contacting the top surface of conductive gate cap structure 240; second field effect transistor region (100 or 200) contacting the top surface of conductive gate cap structure 240; The second source/drain region contacting the source/drain region (65, 66) in the transistor region (300 or 400) contacts the via structure 86A; the second gate contacting the second gate electrode (25, 26) pole contact via structure 86G; a third source/drain region contact via structure 96A in the third field effect transistor region (500, 600) contacting the source/drain region (65, 66); and a third field effect transistor A third gate contact via structure 96G contacts the top surface of conductive gate cap structure 240 in region (500, 600). Additionally, the contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) may include a first passive device contact via structure 96R that contacts a first passive device, such as a resistor, and a first passive device contact via structure 96R that contacts a first passive device, such as a resistor. A second passive device of the two passive devices, such as a capacitor, contacts via structure 96C.

Generally speaking, various field effect transistor regions (100, 200, 300, 400, 500, 600) can be formed with different gate dielectric thicknesses, different gate lengths (ie, different lateral distances between source and drain regions), and different textures. Various types of field effect transistors. Dielectric gate spacers 56 may overlie peripheral regions of the source/drain regions (65, 66) of the field effect transistors in the second field effect transistor region (300 or 400) and contact the trench isolation structure 8 corresponding part of the side wall.

The third exemplary structure may include a combination of first field effect transistors and second field effect transistors located in the first field effect transistor region (100 or 200). The first field effect transistor and the second field effect transistor include a first active region 51 and a second active region 52 respectively. The first active region and the second active region contact the sidewalls of the trench isolation structure 8 and are laterally surrounded by the trench isolation structure. The lateral extension portion 8L of the trench isolation structure 8 is located between the first active region 51 and the second active region 52 .

The third exemplary structure may include a third field effect transistor located in the second field effect transistor region (300 or 400). The third field effect transistor includes: a third active region laterally surrounded by additional portions of trench isolation structure 8; a stack of third gate dielectric 12 and third gate electrode 14, The stack has lateral sidewalls contacting additional portions of the trench isolation structure 8 and extending laterally along the first horizontal direction hd1; additional dielectric gate spacers 56 having therethrough A respective subset of the sidewalls of the additional portion of the trench isolation structure 8 and a respective longitudinal sidewall of the third gate electrode 14 (extending laterally along the second horizontal direction hd2 ) are respectively opened and contacted.

A portion of the top surface of the third gate electrode 14 of the third field effect transistor may be in contact with the contact level dielectric material layer 70 . An additional conductive gate cap structure including a stack of semiconductor gate cap structure 236 and conductive gate cap structure 240 may contact another portion of the top surface of third gate electrode 14 . The additional conductive gate cap structure may comprise the same set of materials as the conductive gate connection structure in the first field effect transistor region (100 and/or 200). At least one gate contact structure, such as first gate contact via structure 76G, may extend vertically through contact level dielectric layer 70 and may contact the conductive gate in the first field effect transistor region (100 and/or 200) The top surface of the electrode connection structure (236, 240) and at least one additional gate contact structure (such as the second gate contact via structure 86G) can extend vertically through the contact level dielectric layer 70 and can contact the additional conductive gate cap The top surface of the cover structure (236,240).

The first gate electrode 14 and the second gate electrode 14 do not contact the contact level dielectric layer 70 and are contacted by the first dielectric gate spacer 56 and the conductive gate connection structure including the conductive gate cap structure 240 Level dielectric layers 70 are spaced apart. The third gate electrode 14 may have the same thickness as the first gate electrode 14 and the second gate electrode 14 . A portion of the top surface of third gate electrode 14 is in direct contact with contact level dielectric layer 70 .

At least one gate contact structure, such as first gate contact via structure 76G, extends through contact level dielectric layer 70 and contacts a top surface of the conductive gate connection structure, which includes a conductive gate cap structure 240 , and at least one additional gate contact structure, such as second gate contact via structure 86G, extends through contact level dielectric layer 70 and contacts a portion of the top surface of third gate electrode 14 . The entire top surface of third gate electrode 14 is in contact with at least one additional gate contact structure or contact level dielectric layer 70 .

The third exemplary structure may include additional field effect transistors, such as a fourth field effect transistor formed in the third field effect transistor region (500 or 600). The additional field effect transistor includes an additional active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting the sidewalls of the additional portion of the trench isolation structure 8 and being isolated by the trench Additional parts of the structure surround it laterally. Additional field effect transistors include additional gate structures (10, 14, 236, 240) overlying the additional active regions. Additional gate structures (10, 14, 236, 240) may include additional gate dielectric 10 having a greater thickness than first gate dielectric 12, additional gate electrode 14 (which may have the same thickness as first gate electrode 14 thickness), an additional semiconductor gate cap structure 236 having the same thickness and the same material composition as the first semiconductor gate cap structure 236 , and having the same thickness and the same material composition as the first conductive gate cap structure 240 An additional conductive gate cap structure 240 composed of a material. The entire top surface of the additional gate electrode 14 is in contact with the bottom surface of the additional semiconductor gate cap structure 236 .

In one embodiment, the third exemplary structure may include a passive device that may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device includes a layer stack that includes, from bottom to top, a first dielectric layer (such as another example of gate dielectric 12), a first semiconductor plate (such as gate electrode 14), a second dielectric layer layer (such as planar dielectric spacer plate 30), a second semiconductor plate (such as planar semiconductor spacer plate 34), a third semiconductor plate (such as semiconductor gate cap structure 236), and a metal plate (such as conductive gate cap structure 240 ). The first dielectric layer has the same material composition and the same thickness as the first gate dielectric 12 . The first semiconductor plate may have the same thickness as the first gate electrode 14 . The second dielectric layer has the same material composition and the same thickness as the first planar dielectric spacer plate 30 . The third semiconductor plate has the same material composition and the same thickness as the first semiconductor gate cap structure 236 in the first field effect transistor region (100 and/or 200). The metal plate has the same material composition and the same thickness as the first conductive gate cap structure 240 in the first field effect transistor region (100 and/or 200).

36A to 36B illustrate a comparison sense amplifier transistor 900C. Transistor 900C may be located in the sense amplifier region of the driver circuit. The gate electrode (40, 50) of transistor 900C extends in a second horizontal direction (eg, transistor width direction) hd2 above active region 51. The second horizontal direction hd2 is perpendicular to the first horizontal direction (eg, the transistor length direction) hd1 , which is parallel to the source-to-drain direction. The comparison sense amplifier transistor 900C includes an edge region in which the gate electrode (40, 50) extends through the active region 51 in the second horizontal direction hd2 and covers a portion of the trench isolation region 8.

37A and 37B illustrate a fourth exemplary sense amplifier transistor 900T according to a fourth embodiment of the present disclosure. Gate cap dielectric 50 may be omitted in transistor 900T, and the gate electrode may include heavily doped polysilicon portion 14 and a conductive gate cap structure including a self-contained gate cap on polysilicon portion 14 . Align the suicide portion 40 . Transistor 900T does not include an edge region in which the gate electrode (14, 40) extends past the active region 51 in the second horizontal direction hd2. Therefore, the gate electrode (14, 40) does not cover a portion of the trench isolation region 8 and the entire occupied area of the gate electrode (14, 40) is located above and within the lateral boundaries of the active region 51. Therefore, the gate electrode (14, 40) may be self-aligned with the active region 51 and have substantially the same width as the active region 51. Silicide portion 40 may serve as gate contact via structure 76G tap region. Alternatively, conductive gate cap structure 40 may include a metal and/or metal nitride structure, such as a W/TiN/Ti structure.

38 is a top view of two adjacent comparison sense amplifier transistors 900C of FIG. 36A, and FIG. 39 is a top view of two adjacent fourth exemplary sense amplifier transistors 900T of FIG. 37A according to the fourth embodiment of the present invention. . Due to the edge region in the transistor 900C, the distance d1 between the active regions 51 of adjacent transistors 900C along the second horizontal direction hd2 is larger than the distance between the active regions 51 of adjacent transistors 900T along the second horizontal direction hd2 d2 is longer. Therefore, edgeless transistors 900T may be formed closer to each other and occupy less chip space than comparative transistor 900C. Therefore, the overall chip size can be reduced.

40A and 40B illustrate a first exemplary transistor 100T according to the first embodiment of the present disclosure. Transistor 100T may be located in a low or ultra-low voltage transistor region (100, 200, 300 or 400) of the peripheral circuit. For example, transistor 100T may be located in region 100 of Figures 14A and 14B. Transistor 100T is also edgeless and lacks the edge regions described above.

FIG. 41 is a top view of two adjacent comparison transistors 100C including the above-described edge region in which the gate electrodes (40, 50) extend past the rear boundary of the active region 51. FIG. 42 is a top view of two adjacent first exemplary transistors 100T of FIG. 40A without edge regions on the rear side of active region 51 . Due to the edge region in the transistor 100C, the distance d3 between the active regions 51 of adjacent transistors 100C along the second horizontal direction hd2 is larger than the distance along the second horizontal direction hd2 between the active regions 51 of adjacent transistors 100T. d4 is longer. Therefore, embodiment transistors 100T may be formed closer to each other and occupy less chip space than comparative transistor 100C. Therefore, the overall chip size can be reduced.

Figure 43 is a top view of two adjacent second exemplary transistors 200T according to the second embodiment of the present disclosure. The second example transistor 200T may be located in the low or ultra-low voltage transistor region 200 of Figures 25A and 25B. Transistor 200T is edgeless and has no edge areas on the front and back sides of active area 51 . The gate electrodes (40, 50) are located above and completely within the boundaries of the active area 51 (ie, the occupied area). Therefore, the edgeless transistors 200T may be formed closer to each other than the transistor 100T, and the distance d5 between the active regions 51 of adjacent transistors 200C along the second horizontal direction hd2 is longer than the active regions of the adjacent transistors 100T. The distance d4 between 51 along the second horizontal direction hd2 is even shorter and longer. Therefore, embodiment transistors 200T may be formed even closer to each other and occupy even less chip space.

Figure 44 is a top view of an alternative configuration of a second exemplary transistor 200T according to a second embodiment of the present disclosure. In the configuration of Figure 44, as shown in Figure 43, the first gate contact via structure 76G may be positioned closer to the middle of the underlying gate electrode (40, 50) rather than closer to the underlying gate electrode The edge of (40,50). This configuration reduces the risk of misalignment between the contact pad areas of the underlying gate electrodes (40, 50) and the first gate contact via structure 76G.

45A, 45B, 46A, 46B, and 46C illustrate a third exemplary transistor structure according to the third embodiment of the present disclosure. The overlying semiconductor gate cap structure 236 and the conductive gate cap structure 240 serve as gate contact via structure 76G tap areas for transistor structures containing both edge and edgeless transistors. Specifically, the edgeless transistor does not have an overlying semiconductor gate cap structure 236 and may include an edgeless gate electrode 14 . The edge-band transistor includes an overlying semiconductor gate cap structure 236 and underlying gate electrode 14 extending across the boundary of active region 51, as shown in Figures 46A and 46C.

The resistance of the polysilicon gate electrode 14 and the semiconductor gate cap structure 236 is reduced by including corresponding suicide regions 25S and 240 on their upper surfaces. The semiconductor gate cap structure 236 extends between two adjacent transistor structures along the second horizontal direction hd2 and serves as a common gate contact via structure 76G tap region. Furthermore, since both the underlying gate electrode 14 and the overlying semiconductor gate cap structure 236 include polysilicon with a suicide cap structure, an edgeless transistor including only the underlying gate electrode 14 and an edgeless transistor including the underlying Characterization of edge-band transistors is facilitated by both the gate electrode 14 and the overlying semiconductor gate cap structure 236 .

The transistor structures may be formed closer to each other (eg, separated by a relatively small distance d2 along the second horizontal direction) and occupy relatively less chip space. Therefore, the overall chip size can be reduced.

Referring to FIGS. 47A-47D , a fifth exemplary structure according to the fifth embodiment of the present disclosure after forming shallow trenches is shown. The fifth exemplary structure may be formed as an additional part of the first exemplary structure, the second exemplary structure, or the third exemplary structure, or may be substituted in the first exemplary structure, the second exemplary structure, or the third exemplary structure. all or part of any of. In one embodiment, by forming additional device regions, or by replacing one or more device regions in the first exemplary structure of FIGS. 1A-1E with the device regions shown in FIGS. The first exemplary structure shown in FIGS. 1A to 1F results in a fifth exemplary structure.

In an illustrative example, the fifth exemplary structure may include a first doped well 5E and a second doped well 5F, each of which may independently have doping of a first conductivity type or a second conductivity. type of doping. Each of the first doped well 5E and the second doped well 5F may be connected to a p-type well (5A, 5B, 5C) or an n-type well (6A, 6B, 6C, 6C, 6A, 6B, 6C) shown in FIGS. 1A to 1F 6D) is formed in the upper portion of the substrate semiconductor layer 4 in the same manner. Each of the first doped well 5E and the second doped well 5F may independently include an atomic concentration in the range of 1.0×10 ¹⁴ /cm ³ to 1.0×10 ¹⁸ /cm ³ (such as, 1.0×10 ¹⁵ /cm ³ to 1.0 × 10 ¹⁷ /cm ³ ) of the first conductivity type dopant or the second conductivity type dopant, although lower and higher atomic concentrations may also be used. The depth of each doped well (5E, 5F) can range from 50nm to 2,000nm, although smaller and larger depths are also possible. The first doped well 5E is used to form peripheral transistors, while the second doped well is used to form sense amplifier transistors of a memory device, such as a three-dimensional memory device.

A silicon oxide pad dielectric layer and a hard mask material layer may be deposited sequentially over the top surface of the semiconductor substrate including the doped wells (5E, 5F). A photoresist layer (not shown) can be applied over the top surface of the hard mask material layer and can be photolithographically patterned to form a plurality of discrete photoresist material portions. In one embodiment, the plurality of discrete photoresist material portions may comprise photoresist having respective rectangular horizontal cross-sectional shapes and located entirely within the region of a respective one of the doped wells (5E, 5F) Material section. In one embodiment, the rectangular horizontal cross-sectional shape may have a pair of longitudinal edges parallel to a first horizontal direction hd1 and a pair of transverse edges parallel to a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 .

A first anisotropic etch process may be performed to transfer a pattern of portions of photoresist material through the layer of hard mask material and the silicon oxide pad dielectric layer. A vertical stack of silicon oxide pad dielectric 120 and hard mask 21 may be formed beneath each portion of patterned photoresist material. Each silicon oxide pad dielectric 120 is a patterned portion of the silicon oxide pad dielectric layer, and each hard mask plate 21 is a patterned portion of the hard mask material layer. In one embodiment, silicon oxide pad dielectric 120 may consist essentially of silicon oxide and may have a thickness in the range of 3 nm to 30 nm, such as 6 nm to 15 nm, although smaller and larger thicknesses may also be used. thickness. In one embodiment, hard mask 21 may consist essentially of silicon nitride and may have a thickness in the range of 60 nm to 300 nm, such as 100 nm to 200 nm, although smaller and larger thicknesses may also be used. The photoresist layer may be removed, for example by ashing, or alternatively may be removed in parallel during a subsequent anisotropic etching process.

A second anisotropic etching process may be performed to transfer the pattern of the hard mask 21 into the upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate that is not masked by the hard mask 21 is anisotropically etched by a second anisotropic etching process to form shallow isolation trenches 7 . The shallow isolation trenches 7 laterally surround the active regions 51 of the semiconductor substrate, which are the patterned upper portions of the semiconductor substrate laterally surrounded by the shallow isolation trenches 7 . The active region 51 includes a first active region 51A and a second active region 51B. The first active region is located under the first hard mask 21A of the hard mask 21 and includes a portion of the first doping well 5E. The second active region is located under the second hard mask 21B of the hard mask 21 and includes a portion of the second doped well 5F.

In one embodiment, each active area 51 may have a corresponding rectangular top surface. In one embodiment, the top surface of the first active area 51A has a first active area length ARL1 along the first horizontal direction hd1 and a first active area width ARW1 along the second horizontal direction hd2. In one embodiment, the top surface of the second active area 51B has a second active area length ARL2 along the second horizontal direction hd1 and a second active area width ARW2 along the second horizontal direction hd2. The depth of the shallow isolation trench 7 may be in the range of 200 nm to 800 nm (such as 300 nm to 600 nm), although smaller and larger depths may also be used. The thickness of each active region 51 may be the same as the depth of the shallow isolation trench 7 .

Referring to FIGS. 48A-48D , at least one dielectric fill material may be conformally deposited in trench 7 and over hard mask 21 . The at least one dielectric fill material may include silicon oxide material. Optionally, a dielectric liner, such as a silicon nitride liner (not explicitly shown), may be deposited prior to depositing the at least one dielectric fill material. Excess portions of the at least one dielectric fill material may be removed from above a horizontal plane including the top surface of hardmask 21 by a planarization process, including a chemical mechanical polishing (CMP) process. In one embodiment, the CMP process stops on hard mask 21 .

The remainder of the at least one dielectric fill material filling trench 7 constitutes a trench isolation structure 8 which may be an adjacent semiconductor that brings the semiconductor material of the semiconductor substrate into contact with the dielectric surface and will subsequently be formed. A continuous structure providing electrical isolation between active regions 51 of the device. Trench isolation structure 8 may include a shallow trench isolation structure located in shallow isolation trench 7 . Each device active region 51 may include a patterned portion of a respective doped well (5E, 5F) laterally surrounded by a respective portion of trench isolation structure 8. Each of the hard masks 21 may include a respective horizontal bottom surface located in a horizontal plane and a respective horizontal top surface located in another horizontal plane.

Referring to FIGS. 49A-49D , a photoresist layer 27 may be applied over the hard mask 21 and the trench isolation structure 8 and may be photolithographically patterned to form an opening having a first doped The entire area of the first hard mask 21A above the well 5E. According to one aspect of the present disclosure, the periphery of the opening in patterned photoresist layer 27 may be offset laterally outward from the sidewalls of first hard mask 21A by at least a minimum lateral offset distance. In one embodiment, the minimum lateral offset distance may be equal to or greater than the lateral thickness of the dielectric spacer to be subsequently formed. In one embodiment, the minimum lateral offset distance may be in the range of 5 nm to 200 nm (such as 10 nm to 100 nm), although smaller and larger minimum lateral offset distances may also be used.

According to one aspect of the present disclosure, at least one region between the sidewalls of the first hard mask 21A and the periphery of the patterned photoresist layer 27 surrounding the opening of the first hard mask 21A may be wide enough to Accommodating at least one gate contact via structure. In other words, the gap region 32 between the sidewalls of the first hard mask 21A and the periphery of the opening in the patterned photoresist layer 27 may extend continuously around the first hard mask 21A, and may include A region of at least one gate contact via structure is then formed without area overlap with first hard mask 21A or patterned photoresist layer 27 .

An etching process may be performed to selectively etch the material of the trench isolation structure 8 with respect to the material of the hard mask 21 to mask the trench isolation of the second hard mask 21B, the second active region 5B, and laterally surrounding the gap region 32 When the field region of the structure 8 is formed, the gap region 32 of the trench isolation structure 8 that laterally surrounds the first active region 51A (ie, the portion of the first doped well 5E located under the first hard mask 21A) is vertically recessed. . The etching process may include an anisotropic etching process (such as a reactive ion etching process). The field region of the trench isolation structure 8 may include a portion of the trench isolation structure 8 covered by the photoresist layer 27 . The recessed horizontal surface of the trench isolation structure 8 is formed in a portion of the trench isolation structure 8 located in the gap region 32 . The recessed horizontal surface is vertically recessed relative to the topmost surface of the trench isolation structure 8 located in the field region and contained in the second horizontal plane.

Generally speaking, the gap region 32 of the trench isolation structure 8 is vertically recessed by performing an etching process to etch the unmasked portion of the trench isolation structure 8 while the hard mask 21 is present on the semiconductor substrate. The recessed horizontal surface is formed above a horizontal plane including the bottom surface of the hard mask template 21 and below a horizontal plane including the top surface of the hard mask template 21 . In one embodiment, the recessed horizontal surface may lie in a horizontal plane. Patterned photoresist layer 27 may then be removed, such as by ashing.

Referring to FIGS. 50A-50D , a selective first etch process (such as a wet etch process) may be performed to selectively remove the hard mask 21 with respect to the materials of the trench isolation structure 8 and the silicon oxide pad dielectric 120 . For example, if the hard mask 21 includes silicon nitride, the first etching process may include a wet etching process using hot phosphoric acid.

An optional second etch process may be performed to remove the silicon oxide pad dielectric 120 selectively to the material of the semiconductor substrate. For example, the second etching process may include an anisotropic etching process (such as a reactive ion etching process) or an isotropic etching process (such as a wet etching process). Silicon oxide pad dielectric 120 (if present) may be removed and the top surface of the active area may be physically exposed around the opening through trench isolation structure 8 .

For example, a gate may be formed on the physically exposed surface of the doped well (5E, 5F) by thermal oxidation of a surface portion of the doped well (5E, 5F) and/or by conformal deposition of a layer of gate dielectric material Dielectric layer 20L. The conformally deposited gate dielectric material layer, if employed, may include silicon oxide and/or dielectric metal oxide materials (such as aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, etc.). The thickness of gate dielectric layer 20L may range from 2 nm to 50 nm, such as 6 nm to 30 nm, although smaller and larger thicknesses may also be used.

Alternatively, the second etch process may be omitted and pad dielectric 120 may be retained. In this case, pad dielectric 120 serves as gate dielectric layer 20L.

The top surface of the gate dielectric layer 20L may be located within the first horizontal plane HP1. The topmost surface of the trench isolation structure 8 may be located within the second horizontal plane HP2. The recessed horizontal surface of the trench isolation structure 8 in the gap region 32 may be located within the third horizontal plane HP3. The vertical distance between the first horizontal plane HP1 and the second horizontal plane HP2 may be in the range of 60 nm to 300 nm, but smaller or larger vertical distances may also be used. In one embodiment, the vertical distance between the third horizontal plane HP3 and the first horizontal plane HP1 may be 10% to 90% of the vertical distance between the second horizontal plane HP2 and the first horizontal plane HP1 (such as 20% to 80% and/or 30% to 70%).

Referring to FIGS. 51A-51D , at least one gate electrode material may be deposited in a cavity located in an opening through trench isolation structure 8 . The at least one gate electrode material includes a conductive material (such as heavily doped polysilicon and/or a metallic (ie, metal or metal alloy) material) and/or a heavily doped amorphous semiconductor material (such as heavily doped amorphous silicon) , the heavily doped amorphous semiconductor material can be transformed into a conductive material (such as heavily doped polysilicon) during a subsequent annealing process.

A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove the at least one gate electrode material from above the second horizontal plane HP2 (ie, the horizontal plane including the topmost surface of trench isolation structure 8 ) part. Thermal annealing may be performed as desired to convert any amorphous semiconductor material in the at least one gate electrode material to a conductive heavily doped polycrystalline semiconductor material. The remainder of the at least one gate electrode material constitutes gate electrode material portion 24', which includes a first gate electrode material portion 24E' and a second gate electrode material portion 24F'. The first gate electrode material portion 24E' may overlie the first active region 51A (ie, a portion of the first doped well 5E), and the second gate electrode material portion 24F' may overlie the second active region 51B (ie, a portion of the second doped well 5F). The first gate electrode material portion 24E' may be formed over and over the gate dielectric layer 20L and the recessed horizontal surface of the trench isolation structure 8 within the third horizontal plane HP3.

Referring to Figures 52A-52D, a photoresist layer 57 can be applied over the gate electrode material portion 24' and the trench isolation structure 8, and can be photolithographically patterned into the pattern of the gate electrode that will subsequently be formed. . In an illustrative example, patterned photoresist layer 57 may include a pair of first photoresist material portions across first active region 51A along second horizontal direction hd2 and along a second horizontal direction hd2 Direction hd2 spans a pair of second photoresist material portions of second active region 51B. According to one aspect of the present disclosure, the periphery of the pair of first photoresist material portions in plan view may be located entirely by the outer periphery of gap region 32 (i.e., separated by a trench laterally surrounding first active region 51A within the area defined by the outer periphery of the recessed horizontal surface of structure 8). In one embodiment, the periphery of the pair of first photoresist material portions in plan view may be laterally spaced inwardly from the outer periphery of gap region 32 by at least one lateral thickness of a dielectric spacer that will subsequently be formed. In one embodiment, the lateral extent of each photoresist material portion of patterned photoresist layer 57 overlying second active region 51B may be greater than that along second active region 51B. The width of the horizontal direction hd2, and the lateral edges of the portion of photoresist material of the patterned photoresist layer 57 overlying the second active area may be completely located in a plan view (such as the top view of FIG. 52A). 2. Outside the area of the active area.

An anisotropic etching process may be performed to etch gate electrode material portions 24' and portions of gate dielectric layer 20L that are not masked by patterned photoresist layer 57. The anisotropic etching process may include a first etching step that selectively etches the material of the gate electrode material portion 24 ′ with respect to the material of the trench isolation structure 8 and the gate dielectric layer 20L and a second etching step. , this second etching step selectively etches the material of the gate dielectric layer 20L with respect to the material of the semiconductor substrate (which is the material of the doped wells (5E, 5F)). The patterned portions of gate electrode material portion 24' constitute gate electrodes 24, which include first gate electrode 24E overlying first active region 51A in first doped well 5E and overlying first active region 51A in first doped well 5E. The second gate electrode 24F above the second active region 51B in the second doped well 5F. Patterned portions of gate dielectric layer 20L constitute gate dielectric 20, which include first gate dielectric 2OE and second gate dielectric 2OF.

Generally speaking, at least one first gate electrode 24E may be formed by patterning a first gate electrode material portion 24E', and at least one second gate electrode 24F may be formed by patterning a second gate electrode material portion 24F'. to form. At least one first gate electrode 24E includes a respective lower gate electrode portion and includes a respective upper gate electrode portion that contacts a top surface of the respective first gate dielectric 20E and the trench isolation structure 8 A pair of sidewall sections, the respective upper gate electrode portions contact the top surface of the respective first section of the recessed horizontal surface of the trench isolation structure 8 and have sidewalls exposed in the gap region 32 . Each lower gate electrode portion is completely between the first and third horizontal planes HP1 and HP3, and each upper gate electrode portion is completely between the second and third horizontal planes HP2 and HP3.

In one embodiment, the top surface of the first active area 51A has an active area length ARL along the first horizontal direction hd1 and an active area width ARW along the second horizontal direction hd2. In one embodiment, the lower gate electrode portion of each first gate electrode 24E has the same lower electrode width LEW as the active area width ARW along the second horizontal direction hd2. The upper gate electrode portion has an upper electrode width UEW greater than the active area width ARW along the second horizontal direction hd2. Patterned photoresist layer 57 may then be removed, such as by ashing.

Referring to FIGS. 53A-53D , optional dielectric liner layer 55L may be conformally deposited on gate electrode 24 and physically exposed surfaces of trench isolation structure 8 , including conformally deposited in gap region 32 . Dielectric liner layer 55L, if present, includes a first layer of dielectric spacer material. Dielectric liner layer 55L may be conformally formed over and around gate electrode 24 and over the recessed horizontal surface of trench isolation structure 8 . Dielectric liner 55L includes a dielectric material such as silicon nitride, and has a thickness in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be employed. In general, the thickness of dielectric liner layer 55L may be selected to optimize the profile of source/drain extensions 64 that will subsequently be formed.

Electrical dopants may be implanted into the exposed surface portions of active regions (51A, 51B) to form source/drain extension regions 64. Each source/drain extension 64 may form a pn junction with a corresponding underlying doped well (5E, 5F). Source/drain extensions 64 may include electrical dopants of corresponding conductivity types with atomic concentrations in the range of 1.0×10 ¹⁷ /cm ³ to 1.0×10 ²⁰ /cm ³ , although smaller and larger sizes may also be used. atomic concentration. The depth of each source/drain extension 64 may be in the range of 5 nm to 100 nm (such as 10 nm to 50 nm), although smaller and larger depths may also be used.

Referring to Figures 54A-54D, the main dielectric spacer layer may be conformally deposited. The main dielectric spacer layer includes a layer of dielectric spacer material. Generally, at least one layer of dielectric spacer material may be deposited over gate electrode 24 and trench isolation structure 8 . The at least one layer of dielectric spacer material includes optional dielectric liner layer 55L and a main dielectric spacer layer. The second dielectric spacer layer includes a dielectric material, such as silicon oxide. The thickness of the main dielectric spacer layer may range from 10 nm to 300 nm (such as 20 nm to 150 nm), although smaller and larger thicknesses may also be used.

An anisotropic etching process may be performed to remove horizontally extending portions of the at least one layer of dielectric spacer material. Generally speaking, at least one layer of dielectric spacer material may be conformally formed over and around first gate electrode 24E, second gate electrode 24F and over the recessed horizontal surfaces and topmost surfaces of trench isolation structure 8 . The remainder of the at least one layer of dielectric spacer material includes: dielectric gate spacers (55, 56) that laterally surround and contact respective ones of gate electrodes 24; and dielectric Isolation spacers (55', 56'), these dielectric isolation spacers contact the sidewalls of the trench isolation structure 8 between the second horizontal plane HP2 and the third horizontal plane HP3.

In one embodiment, each dielectric gate spacer (55, 56) may be a composite dielectric gate spacer including at least two different compositions (which may have different dielectric compositions), and the dielectric isolation The spacers (55', 56') may be composite dielectric isolation spacers including at least two different compositions. In one embodiment, each dielectric gate spacer (55, 56) may include a main dielectric gate spacer 56 (which may be a patterned portion of the main dielectric spacer layer) and optional liner spacers. Electrical gate spacers 55 (which are patterned portions of dielectric liner layer 55L). In one embodiment, the dielectric isolation spacers (55', 56') may include a main dielectric isolation spacer 56 (which may be a patterned portion of the main dielectric spacer layer) and an optional pad dielectric gate Polar isolation spacers 55 (which are patterned portions of dielectric liner layer 55L).

The dielectric gate spacers (55, 56) include at least one first dielectric gate spacer (55, 56) laterally surrounding the respective first gate electrode 24E and A corresponding second section of the recessed horizontal surface of the trench isolation structure 8 is contacted. Dielectric isolation spacers (55', 56') contact the sidewalls of trench isolation structure 8 in gap region 32, these sidewalls connect the recessed horizontal surface of trench isolation structure 8 to the outermost surface of trench isolation structure 8. top surface.

In one embodiment, dielectric isolation spacers (55', 56') include the same set of materials as dielectric gate spacers (55, 56). In one embodiment, the lateral dimension between the inner periphery of the bottom surface of the dielectric isolation spacers (55', 56') and the outer periphery of the bottom surface of the dielectric isolation spacers (55', 56') may be The lateral dimensions between the inner periphery of the bottom surface of the dielectric gate spacers (55, 56) and the outer periphery of the bottom surface of the dielectric gate spacers (55, 56) are the same.

In one embodiment, the dielectric isolation spacers (55', 56') are not in direct contact with the semiconductor substrate and the entire dielectric isolation spacers (55', 56') are located at the level of the recess that includes the trench isolation structure 8 Above the horizontal plane of the surface (ie above the third horizontal plane HP3). In one embodiment shown in Figures 54B and 54C, each dielectric gate spacer (55, 56) includes a pair of first bottom surfaces contacting a section of the top surface of first active region 51A, and A pair of second bottom surfaces contact a second section of the recessed horizontal surface of the trench isolation structure 8 above a horizontal plane including the pair of first bottom surfaces.

In one embodiment, dielectric gate spacers (55, 56) are laterally spaced from sidewalls of trench isolation structure 8 that connect the recessed horizontal surfaces of trench isolation structure 8 to trench isolation structure 8 the topmost surface.

Electrical dopants may be implanted into doped regions 64 and surface portions of source/drain extension regions 64 to form deep source/drain regions 66 . Each deep source/drain region 66 may form a pn junction with a corresponding active region (51A, 51B) in a corresponding underlying doped well (5E, 5F). The implanted portions of source/drain extension regions 64 may be incorporated into respective ones of deep source/drain regions 66 and may have the same conductivity as respective ones of deep source/drain regions 66 type of doping. Deep source/drain regions 66 may include electrical dopants of corresponding conductivity types with atomic concentrations in the range of 5.0×10 ¹⁸ /cm ³ to 2.0×10 ²¹ /cm ³ , although smaller and larger sizes may also be used. atomic concentration. The depth of each deep source/drain region 66 may be in the range of 30 nm to 600 nm, such as 60 nm to 300 nm, although smaller and larger depths may also be used. Each successive combination of source/drain extension region 64 and deep source/drain region 66 constitutes a source/drain region (64, 66) which may function as either a source region or a drain region district. A pn junction may be formed between each source/drain region (64, 66) and the corresponding active region (51A, 51B) in the underlying doped well (5E, 5F).

A first field effect transistor 902 and a second field effect transistor 904 may be formed. The first field effect transistor 902 may include peripheral transistors that are not sense amplifier transistors. The first field effect transistor 902 includes a first active region 51A including a first opening of the semiconductor substrate through the trench isolation structure 8 and a first gate structure (20E, 24E). In part, the first gate structure includes first gate dielectric 20E and first gate electrode 24E. First gate electrode 24E includes a lower gate electrode portion that contacts a top surface of first gate dielectric 20E and a pair of sidewall regions of trench isolation structure 8 and includes an upper gate electrode portion. section, the upper gate electrode portion contacts the first section of the recessed horizontal surface of the trench isolation structure 8 . The lower gate electrode part may be located below the third horizontal plane HP3 including the recessed horizontal surface of the trench isolation structure 8 , and the upper gate electrode part may be located above the third horizontal plane HP3 . First dielectric gate spacers (55, 56) laterally surround first gate electrode 24E and contact the second section of the recessed horizontal surface of trench isolation structure 8. The first field effect transistor 902 includes the above-mentioned edge region.

The second field effect 904 includes an edgeless sense amplifier transistor. The second field effect transistor 904 includes a second active region 51B including a second opening of the semiconductor substrate through the trench isolation structure 8 and includes a second gate structure (20F, 24F). Another portion of the second gate structure includes a second gate dielectric 20F and a second gate electrode 24F. Second gate electrode 24F includes a pair of sidewalls extending straight vertically from respective edges of a top surface of second gate electrode 24F to a second gate dielectric located beneath second gate electrode 24F. The corresponding edge of the top surface of the quality 20F. In one embodiment, the entire pair of sidewalls of second gate electrode 24F are in contact with corresponding sidewalls of trench isolation structure 8 . In one embodiment, second gate electrode 24F includes a first sidewall in contact with a sidewall section of trench isolation structure 8 and a second sidewall in contact with a pair of dielectric gate spacers (55, 156) , the pair of dielectric gate spacers includes a respective main dielectric gate spacer 156 and an optional pad dielectric gate spacer 55. Each second dielectric gate spacer (55, 56) contacts the second gate electrode 24F and the sidewalls of the trench isolation structure 8.

Referring to Figures 55A-55D, a metal (eg, W, Co, Ni, Ti, Ta, etc.) forming a metal-semiconductor alloy (such as a metal suicide) may be deposited at the physical exposure of the source/drain regions (64, 66) surface and on the top surface of gate electrode 24 . Metal-semiconductor alloy regions (e.g., silicide regions such as W, Co, Ni, Ti, Ta, etc.) (68,58) can be formed by performing an annealing process that causes the metal to interact with the source/drain Reaction of surface portions of regions (64, 66) and surface portions of gate electrode 24 (in the case where gate electrode 24 includes a semiconductor material such as silicon or a silicon-germanium alloy). The metal semiconductor alloy regions (68, 58) include a source/drain metal semiconductor alloy region 68 in contact with the source/drain regions (64, 66), and a gate metal semiconductor alloy region 58 in contact with the gate electrode 24 . Unreacted portions of the metal may be removed, for example, by a wet etching process that etch the metal selectively with respect to the metal-semiconductor alloy of the metal-semiconductor alloy regions (68, 58).

In one embodiment, the first gate metal semiconductor alloy portion 58 may have a bottom surface below a horizontal plane that includes the topmost surface of the trench isolation structure 8 (ie, below the second horizontal plane HP2) contacts the top surface of the first gate electrode 24E in a horizontal plane and may have a top surface located above a horizontal plane including the topmost surface of the trench isolation structure 8 . In one embodiment, second gate electrode 24F includes a top surface located in the same horizontal plane as the top surface of first gate electrode (20E, 24E).

Referring to Figures 56A-56D, at least one dielectric liner (172,174) may be conformally deposited on the trench isolation structure 8, the metal-semiconductor alloy region (68,58) and the dielectric spacer {(55,56),( 55',56'),(55,136)} above. The at least one dielectric pad (172, 174) may include a first dielectric pad 172 and a second dielectric pad 174. In one embodiment, the first dielectric liner 172 may include a silicon oxide liner having a thickness in the range of 3 nm to 60 nm, and the second dielectric liner 174 may include a silicon oxide liner having a thickness in the range of 3 nm to 60 nm. thickness of silicon nitride liner.

A contact level dielectric layer 70 may be deposited over the at least one dielectric pad (172, 174). First contact level dielectric layer 70 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organic silicate glass. Optionally, a planarization process may be performed to planarize the top surface of contact level dielectric layer 70 .

Referring to FIGS. 57A-57D , contact via cavities may be formed through contact level dielectric layer 70 and the at least one dielectric pad (172, 174) and may be filled with at least one conductive material to form various contact vias. Structure (176A, 176G, 186A, 186G). The contact via structures (176A, 176G, 186A, 186G) may include contacting a corresponding one of the source/drain metal semiconductor alloy region 68 or the source/drain regions (64, 66) of the first field effect transistor 902. A first source/drain contact via structure 176A, a first gate contact via structure 176G contacting a corresponding one of the gate metal semiconductor alloy region or the first gate electrode 24E, and a second field effect Second source/drain contact via structure 186A of respective one of source/drain metal semiconductor alloy region 68 or source/drain regions (64, 66) of transistor 904, and contact gate metal semiconductor Second gate contact via structure 186G of a respective one of alloy region or second gate electrode 24F. Generally speaking, gate contact via structures (176G, 186G) may be formed through planarized dielectric layer 70 such that first gate contact via structure 176G is electrically connected to a corresponding one of first gate electrode 24E. , and the second gate contact via structure 186G is electrically connected to a corresponding one of the second gate electrodes 24F.

In one embodiment, each of the first gate contact via structures 176G may be located completely outside the area of the top surface of the first active region 51A in plan view and may be completely located in the gap region 32 (i.e., within a region laterally bounded by the inner periphery of the recessed horizontal surface of the trench isolation structure 8 and the outer periphery of the recessed horizontal surface of the trench isolation structure 8). In other words, the first gate contact via structure 176G may be completely within the area of the recessed horizontal surface of the trench isolation structure 8 in plan view. Each of the second gate contact via structures 186G may be located entirely within the area of the top surface of the second active region 51B in plan view.

Referring to a fifth embodiment, a semiconductor structure including a first field effect transistor is provided. The semiconductor structure includes a trench isolation structure 8 located in an upper portion of the semiconductor substrate and including a first opening therethrough. Trench isolation structure 8 includes a gap region having a recessed horizontal surface, laterally surrounding the first opening, and laterally surrounded by a field region of trench isolation structure 8 including a topmost surface of trench isolation structure 8 . The first field effect transistor includes a first active region including a portion of the semiconductor substrate located within a first opening through trench isolation structure 8 . The first field effect transistor includes a first gate structure (24E-20E) including a first gate dielectric 20E and a first gate electrode 24E. First gate electrode 24E includes a lower gate electrode portion that contacts a top surface of first gate dielectric 20E and a pair of sidewall regions of trench isolation structure 8 and includes an upper gate electrode portion. section, the upper gate electrode portion contacts the first section of the recessed horizontal surface of the trench isolation structure 8 . First dielectric gate spacers (55, 56) laterally surround first gate electrode 24E and contact the second section of the recessed horizontal surface of trench isolation structure 8.

In embodiments of the present invention, the high voltage non-sense amplifier peripheral transistor 902 (which is external to the sense amplifier circuit) may be formed with a gate edge region to improve the stability of its electrical characteristics since it first The length of the gate electrode 24E in the horizontal direction hd1 is shorter, and the contact process has a greater impact on its gate dielectric layer. Conversely, low or ultra-low voltage sense amplifier transistor 904 (which operates at a lower voltage than transistor 902) may be formed with a larger gate electrode 24F length and no gate edge region. Gate contact 186G of transistor 904 is located over active region 51B. Therefore, the device area is reduced. Additionally, both transistors 902 and 904 can be fabricated in parallel using the same processing steps, which reduces the number of processing steps and reduces the cost of the process.

Although specific preferred embodiments are mentioned above, it will be understood that the disclosure is not limited thereto. It will be apparent to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. While embodiments are shown in this disclosure employing specific structures and/or configurations, it is understood that the disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not expressly made. prohibited or otherwise considered impossible by a person of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims (60)

1. A semiconductor structure, comprising:

a first field effect transistor comprising a first active region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric, the first active region comprising a source region, a drain region, and a channel region between the source region and the drain region;

a second field effect transistor comprising a second active region, a second gate dielectric overlying the active region, and a second gate electrode overlying the second gate dielectric, the second active region comprising a source region, a drain region, and a channel region between the source region and the drain region; and

a trench isolation region surrounding the first active region and the second active region;

wherein:

the first field effect transistor includes an edge region in which the first gate electrode extends through the active region in a second horizontal direction perpendicular to a first horizontal source region to drain region direction;

the second field effect transistor does not include the edge region in which the second gate electrode extends past the active region in the second horizontal direction.

2. The semiconductor structure of claim 1, wherein:

the first gate electrode overlies the trench isolation region in the edge region;

the second gate electrode does not overlie a portion of the trench isolation region; and is also provided with

The entire occupied area of the second gate electrode is located above and within the lateral boundaries of the second active region.

3. The semiconductor structure of claim 1, wherein the second field effect transistor is located in a sense amplifier circuit of a driver circuit of a memory device and the first transistor is located outside the sense amplifier circuit of the driver circuit of the memory device.

4. The semiconductor structure of claim 1, wherein along the first horizontal direction, the first gate electrode length is shorter than the second gate electrode length.

5. The semiconductor structure of claim 1, wherein:

the trench isolation region includes a trench isolation structure having a first opening therethrough;

the trench isolation structure includes a gap region having a recessed horizontal surface, laterally surrounding the first opening, and laterally surrounded by a field region of the trench isolation structure including a topmost surface of the trench isolation structure;

The first active region is located within the first opening through the trench isolation structure;

the first gate electrode includes a lower gate electrode portion contacting a top surface of the first gate dielectric and a pair of sidewall sections of the trench isolation structure and includes an upper gate electrode portion contacting a first section of the recessed horizontal surface of the trench isolation structure; and is also provided with

A first dielectric gate spacer laterally surrounds the first gate electrode and contacts a second section of the recessed horizontal surface of the trench isolation structure.

6. The semiconductor structure of claim 5, wherein:

a top surface of the first active region has an active region length along the first horizontal direction and an active region width along the second horizontal direction;

the lower gate electrode portion has a lower electrode width along the second horizontal direction that is the same as the active region width; and is also provided with

The upper gate electrode portion has an upper electrode width along the second horizontal direction that is greater than the active region width.

7. The semiconductor structure of claim 5, further comprising a dielectric isolation spacer contacting sidewalls of the trench isolation structure, the sidewalls connecting the recessed horizontal surface of the trench isolation structure to the topmost surface of the trench isolation structure.

8. The semiconductor structure of claim 4, wherein:

the dielectric isolation spacers comprise the same set of materials as the dielectric gate spacers;

a lateral dimension between an inner periphery of a bottom surface of the dielectric isolation spacer and an outer periphery of the bottom surface of the dielectric isolation spacer is the same as a lateral dimension between an inner periphery of a bottom surface of the dielectric gate spacer and an outer periphery of the bottom surface of the dielectric gate spacer;

the dielectric isolation spacer is not in direct contact with the semiconductor substrate; and is also provided with

The entire dielectric isolation spacer is located above a horizontal plane including the recessed horizontal surface of the trench isolation structure.

9. The semiconductor structure of claim 5, wherein:

the first dielectric gate spacer includes a pair of first bottom surfaces that contact a section of a top surface of the first active region and a pair of second bottom surfaces that contact the second section of the recessed horizontal surface of the trench isolation structure and that lie above a horizontal plane that includes the pair of first bottom surfaces; and is also provided with

The first dielectric gate spacer is laterally spaced from a sidewall of the trench isolation structure that connects the recessed horizontal surface of the trench isolation structure to the topmost surface of the trench isolation structure.

10. The semiconductor structure of claim 5, further comprising: a first gate metal semiconductor alloy portion having a bottom surface contacting a top surface of the first gate electrode in a horizontal plane below a horizontal plane including the topmost surface of the trench isolation structure and having a top surface above the horizontal plane including the topmost surface of the trench isolation structure.

11. The semiconductor structure of claim 5, further comprising:

a planarizing dielectric layer overlying the first gate electrode; and

a gate contact via structure extending vertically through the planarized dielectric layer, contacting the first gate stack structure, and electrically connected to the first gate electrode, wherein the gate contact via structure is located entirely outside of the area of the top surface of the first active region in plan view.

12. The semiconductor structure of claim 11, wherein the gate contact via structure is located entirely within a region of the recessed horizontal surface of the trench isolation structure in the plan view.

13. The semiconductor structure of claim 5, wherein:

the second active region is located within a second opening through the trench isolation structure; and is also provided with

The second gate electrode includes a top surface that lies in the same horizontal plane as the top surface of the first gate electrode and includes a pair of sidewalls that extend vertically straight from respective edges of the top surface of the second gate electrode to respective edges of the top surface of the second gate dielectric.

14. The semiconductor structure of claim 13, wherein the entire pair of sidewalls of the second gate electrode are in contact with respective sidewalls of the trench isolation structure.

15. A method of forming a semiconductor structure, comprising:

forming a hard mask plate over a semiconductor substrate;

forming an isolation trench by etching an upper portion of the semiconductor substrate not masked by the hard mask, wherein the isolation trench laterally surrounds a first active region located under a first hard mask in the hard mask;

Forming a trench isolation structure by depositing a dielectric fill material in the isolation trench;

vertically recessing a gap region of the trench isolation structure laterally surrounding the first active region while masking a field region of the trench isolation structure laterally surrounding the gap region, wherein a recessed horizontal surface is formed in a portion of the trench isolation structure located in the gap region, and wherein the recessed horizontal surface is vertically recessed relative to a topmost surface of the trench isolation structure located in the field region;

forming a first gate dielectric layer on a top surface of the first active region;

forming a first gate electrode material portion over the first gate dielectric layer and over the recessed horizontal surfaces of the trench isolation structure; and

forming a first gate dielectric and a first gate electrode by patterning the first gate dielectric layer and the first gate electrode material portion, respectively, wherein the first gate electrode comprises a lower gate electrode portion contacting a top surface of the first gate dielectric and a pair of sidewall sections of the trench isolation structure and comprises an upper gate electrode portion contacting a first section of the recessed horizontal surface of the trench isolation structure.

16. The method of claim 15 wherein the gap regions of the trench isolation structure are vertically recessed by performing an etching process that etches unmasked portions of the trench isolation structure while the hard mask is present over the semiconductor substrate.

17. The method of claim 15, wherein the recessed horizontal surface is formed above a horizontal plane that includes a bottom surface of the hard mask plate.

18. The method of claim 15, further comprising:

conformally forming at least one layer of dielectric spacer material over and around the first gate electrode and over the recessed horizontal surface; and

the at least one dielectric spacer material layer is anisotropically etched wherein a remaining portion of the at least one dielectric spacer material layer includes first dielectric gate spacers laterally surrounding the first gate electrode and contacting a second section of the recessed horizontal surfaces of the trench isolation structures.

19. The method of claim 18, wherein the remaining portion of the at least one layer of dielectric spacer material further comprises dielectric isolation spacers contacting sidewalls of the trench isolation structure, the sidewalls connecting the recessed horizontal surfaces of the trench isolation structure to the topmost surface of the trench isolation structure.

20. The method of claim 15, further comprising:

forming a planarizing dielectric layer over the first gate electrode; and

a gate contact via structure is formed through the planarized dielectric layer, wherein the gate contact via structure is electrically connected to the first gate electrode, and wherein the gate contact via structure is located entirely outside an area of a top surface of the first active region in a plan view.

21. A semiconductor structure comprising a first field effect transistor, wherein:

the first field effect transistor includes a first active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls that contact and are laterally surrounded by a sidewall of a first portion of the trench isolation structure;

the first active region includes a first source region, a first drain region, and a first channel region between the first source region and the first drain region;

the first gate structure includes a first gate dielectric, a first gate electrode, a first planar dielectric spacer, and a first conductive gate cap structure overlying the first channel region;

The first gate dielectric and the first gate electrode contact sidewalls of a protruding region of the first portion of the trench isolation structure, the sidewalls extending laterally along a first horizontal direction;

the first planar dielectric spacer contacts a first portion of a top surface of the first gate electrode; and is also provided with

The first conductive gate cap structure includes: a first section contacting a second portion of the top surface of the first gate electrode; a second section overlying the first planar dielectric spacer plate; and a connecting section contacting the first sidewall of the first planar dielectric spacer and connecting the first section and the second section.

22. The semiconductor structure of claim 21 wherein the first gate dielectric and the first gate electrode comprise sidewalls extending laterally along the first horizontal direction, vertically coincident with each other, laterally spaced apart from the sidewalls of the recessed region of the first portion of the trench isolation structure, and vertically coincident with sidewalls of another region of the first portion of the trench isolation structure.

23. The semiconductor structure of claim 21, further comprising a contact level dielectric layer overlying the first field effect transistor, laterally surrounding the first field effect transistor, and contacting a third portion of the top surface of the first gate electrode, wherein the third portion of the top surface of the first gate electrode is laterally spaced apart from the second portion of the top surface of the first gate electrode by the first portion of the top surface of the first gate electrode.

24. The semiconductor structure of claim 21, wherein a portion of a bottom surface of the first conductive gate cap structure contacts a top surface of the protruding region of the first portion of the trench isolation structure.

25. The semiconductor structure of claim 21 further comprising a first planar semiconductor spacer contacting a top surface of the first planar dielectric spacer, having a smaller area than the first planar dielectric spacer, and contacting a bottom surface of the second section of the first conductive gate cap structure.

26. The semiconductor structure of claim 25, wherein a first sidewall of the first planar semiconductor spacer overlies the first sidewall of the first planar dielectric spacer, vertically coincides with the first sidewall of the first planar dielectric spacer, and contacts the connection section of the first conductive gate cap structure.

27. The semiconductor structure of claim 26, further comprising a first dielectric gate spacer comprising an upper portion laterally surrounding and contacting the first conductive gate cap structure and the first planar semiconductor spacer and contacting a portion of a top surface of the first planar dielectric spacer.

28. The semiconductor structure of claim 27, wherein:

the first dielectric gate spacer contacts a second sidewall of the first planar semiconductor spacer; and is also provided with

An outer sidewall of the first dielectric gate spacer vertically coincides with a second sidewall of the first planar dielectric spacer plate.

29. The semiconductor structure of claim 27, wherein:

the first gate dielectric includes a first sidewall that contacts the sidewall of the protruding region of the first portion of the trench isolation structure;

The first gate electrode includes a first sidewall that contacts the sidewall of the protruding region of the first portion of the trench isolation structure;

a second sidewall of the first gate dielectric and a second sidewall of the first gate electrode extending laterally along the first horizontal direction contact sidewalls of a lower portion of the first dielectric gate spacer.

30. The semiconductor structure of claim 29 wherein the first gate dielectric and an additional sidewall of the first gate electrode contact an additional sidewall of the lower portion of the first dielectric gate spacer, the additional sidewall extending laterally along a second horizontal direction perpendicular to the first horizontal direction.

31. The semiconductor structure of claim 21, further comprising a second field effect transistor, wherein:

the second field effect transistor includes a second active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls contacting and laterally surrounded by sidewalls of a second portion of the trench isolation structure;

a second gate structure comprising a second gate dielectric and a second gate electrode overlying the second active region;

A contact level dielectric layer overlying the first gate structure and the second gate structure;

at least one gate contact structure is in contact with a portion of a top surface of the second gate electrode; and is also provided with

The entire top surface of the second gate electrode that is not in contact with the at least one gate contact structure is in contact with the contact level dielectric layer.

32. The semiconductor structure of claim 31, further comprising an additional field effect transistor, wherein:

the additional field effect transistor includes an additional active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls that contact and are laterally surrounded by the sidewalls of the additional portion of the trench isolation structure; and is also provided with

An additional gate structure overlies the additional active region, the additional gate structure including an additional composite gate dielectric including a silicon oxide sub-layer and a silicon nitride sub-layer having a greater thickness than the first gate dielectric, and an additional gate electrode including an additional conductive gate cap structure having the same thickness and the same material composition as the first section of the first conductive gate cap structure.

33. The semiconductor structure of claim 21, further comprising a passive device comprising at least one of a capacitor or a resistor, wherein:

the passive device includes a layer stack including, from bottom to top, a first dielectric layer, a second dielectric layer, a semiconductor plate, and a metal plate;

the second dielectric layer has the same material composition and the same thickness as the first planar dielectric spacer; and is also provided with

The metal plate has the same material composition and the same thickness as the first section of the first conductive gate cap structure.

34. A method of forming a semiconductor structure, comprising:

forming a first gate dielectric layer and a semiconductor gate material layer over the semiconductor material layer;

forming a trench isolation structure through the semiconductor gate material layer and the first gate dielectric layer, wherein patterned portions of the semiconductor gate material layer and the first gate dielectric layer comprise a stack of a first gate dielectric plate and a first gate electrode material plate laterally surrounded by a first portion of the trench isolation structure;

forming a planar dielectric spacer over the first gate electrode;

Physically exposing a top surface of a portion of the first semiconductor gate material layer by patterning the planar dielectric spacer layer; and

forming a first conductive gate cap structure on the physically exposed portion of the top surface of the first gate electrode material plate; and

patterning the stack of the first gate dielectric plate and the first gate electrode material plate into a stack of a first gate dielectric and a first gate electrode.

35. The method according to claim 34, wherein:

patterning the first gate electrode material plate into the first gate electrode by an anisotropic etching process employing a patterned etching mask;

patterning the first gate dielectric plate and the planar dielectric spacer plate into the first gate dielectric and the first planar dielectric spacer plate, respectively, by the same etching process; and is also provided with

The first planar dielectric spacer covers a first portion of a top surface of the first gate electrode when the first gate electrode material plate is patterned into the first gate electrode.

36. The method of claim 35, wherein the first conductive gate cap structure comprises:

A first section contacting a second portion of the top surface of the first gate electrode;

a second section overlying the first planar dielectric spacer plate; and

and a connecting section contacting the first sidewall of the first planar dielectric spacer and connecting the first section and the second section.

37. The method of claim 36, further comprising depositing a contact level dielectric layer directly on a third portion of the top surface of the first gate electrode, the third portion being laterally spaced apart from the second portion of the top surface of the first gate electrode by the first portion of the top surface of the first gate electrode.

38. The method according to claim 34, wherein:

a portion of the first conductive gate cap structure covers a top surface of the first portion of the trench isolation structure; and is also provided with

The method further includes vertically recessing unmasked portions of the trench isolation structure after forming the first conductive gate cap structure and before patterning the stack of the first gate dielectric plate and the first gate electrode material plate; and is also provided with

A section of the first portion of the trench isolation structure underlying the first conductive gate cap structure protrudes above a horizontal top surface of a recessed region of the first portion of the trench isolation structure.

39. The method of claim 34, further comprising forming a first planar semiconductor spacer on a top surface of the planar dielectric spacer layer prior to physically exposing the top surface of the portion of the first semiconductor gate material layer, wherein the first conductive gate cap structure is formed directly on the first planar semiconductor spacer.

40. The method of claim 39, further comprising:

forming a planar semiconductor spacer layer over the planar dielectric spacer layer;

patterning the planar semiconductor spacer layer and the planar dielectric spacer layer using an etching process, thereby physically exposing the top surface of the portion of the first semiconductor gate material layer, the etching process using an etching mask;

depositing a conductive gate cap layer over the planar semiconductor spacer layer and directly on the top surface of the portion of the first semiconductor gate material layer; and

The conductive gate cap layer and the planar semiconductor spacer layer are patterned, wherein the patterned portion of the planar semiconductor spacer layer comprises the first planar semiconductor spacer plate and the patterned portion of the conductive gate cap layer comprises the conductive gate cap structure.

41. A semiconductor structure comprising a first field effect transistor and a second field effect transistor, wherein:

the first and second field effect transistors include first and second active regions, respectively, wherein the first and second active regions contact sidewalls of a trench isolation structure and are laterally surrounded by the trench isolation structure, wherein a laterally extending portion of the trench isolation structure is located between the first and second active regions;

a stack of a first gate dielectric and a first gate electrode overlies a first channel region within the first active region and contacts a first sidewall of the laterally extending portion of the trench isolation structure;

a second gate dielectric and a second gate electrode stack overlying a second channel region within the second active region and contacting a second sidewall of the laterally extending portion of the trench isolation structure;

A conductive gate connection structure contacts a top surface of the first gate electrode, a top surface of the second gate electrode, and a portion of a top surface of the laterally extending portion of the trench isolation structure, and includes a pair of lateral sidewalls extending laterally along a first horizontal direction and a pair of longitudinal sidewalls extending laterally along a second horizontal direction; and is also provided with

Longitudinal sidewalls of the first gate electrode and the second gate electrode vertically coincide with the pair of longitudinal sidewalls of the conductive gate connection structure.

42. The semiconductor structure of claim 41, wherein:

the trench isolation structure includes a frame portion continuously laterally surrounding the first active region and the second active region;

the conductive gate connection structure includes a first end portion and a second end portion overlying and contacting a respective section of a top surface of the frame portion of the trench isolation structure.

43. The semiconductor structure of claim 42 wherein:

a first lateral sidewall of the first gate dielectric and a first lateral sidewall of the first gate electrode vertically coincide with each other and contact a first sidewall of the laterally extending portion of the trench isolation structure; and is also provided with

The first lateral sidewall of the second gate dielectric and the first lateral sidewall of the second gate electrode vertically coincide with each other and contact the second sidewall of the laterally extending portion of the trench isolation structure.

44. The semiconductor structure of claim 43, wherein:

a second lateral sidewall of the first gate dielectric and a second lateral sidewall of the first gate electrode vertically coincide with each other and contact a first sidewall of the frame portion of the trench isolation structure; and is also provided with

A second lateral sidewall of the second gate dielectric and a second lateral sidewall of the second gate electrode vertically overlap each other and contact a second sidewall of the frame portion of the trench isolation structure.

45. The semiconductor structure of claim 41 wherein the conductive gate connection structure comprises a metal gate connection structure having a first thickness over a main section of the first gate electrode, over the laterally extending portion of the trench isolation structure, and over an entire region of the second gate electrode, and a second thickness greater than the first thickness over a complementary section of the first gate electrode.

46. The semiconductor structure of claim 41 wherein the conductive gate connection structure comprises a heavily doped semiconductor gate connection structure having a uniform thickness throughout and contacting top surfaces of the first gate electrode, the laterally extending portion of the trench isolation structure, and the second gate electrode.

47. The semiconductor structure of claim 46 wherein the conductive gate connection structure comprises a heavily doped polysilicon gate connection structure having a silicide layer on a top surface and the first gate electrode and the second gate electrode comprise heavily doped polysilicon gate electrodes having a silicide layer on a top surface.

48. The semiconductor structure of claim 41, further comprising a dielectric gate spacer, the dielectric gate spacer comprising:

an upper portion laterally surrounding the conductive gate connection structure; and

four lower portions extending vertically between a horizontal plane including a top surface of the trench isolation structure and a horizontal plane including top surfaces of the first and second active regions and contacting respective longitudinal sidewalls of one of the first and second gate electrodes and contacting a top surface of a respective one of the first and second active regions.

49. The semiconductor structure of claim 48, further comprising a third field effect transistor, the third field effect transistor comprising:

a third active region laterally surrounded by an additional portion of the trench isolation structure;

a stack of a third gate dielectric and a third gate electrode, the stack having lateral sidewalls contacting sidewalls of the additional portion of the trench isolation structure;

additional dielectric gate spacers have respective openings therethrough and contact respective subsets of sidewalls of the additional portions of the trench isolation structure and respective longitudinal sidewalls of the third gate electrode.

50. The semiconductor structure of claim 49, further comprising a contact level dielectric layer overlying the first, second, and third field effect transistors, wherein:

the first gate electrode and the second gate electrode do not contact the contact level dielectric layer and are spaced from the contact level dielectric layer by the dielectric gate spacer and the conductive gate connection structure;

the third gate electrode has the same thickness as the first gate electrode and the second gate electrode; and is also provided with

A portion of a top surface of the third gate electrode is in direct contact with the contact level dielectric layer.

51. The semiconductor structure of claim 50, further comprising:

a conductive gate cap structure contacting another portion of the top surface of the third gate electrode and comprising the same material as the conductive gate connection structure;

at least one gate contact structure extending through the contact level dielectric layer and contacting a top surface of the conductive gate connection structure; and

at least one additional gate contact structure extending through the contact level dielectric layer and contacting a top surface of the conductive gate cap structure,

wherein the entire top surface of the first gate electrode and the entire top surface of the second gate electrode contact the bottom surface of the conductive gate connection structure.

52. The semiconductor structure of claim 50, further comprising:

at least one gate contact structure extending through the contact level dielectric layer and contacting a top surface of the conductive gate connection structure; and

At least one additional gate contact structure extending through the contact level dielectric layer and contacting a portion of a top surface of the third gate electrode,

wherein the entire top surface of the third gate electrode is in contact with the at least one additional gate contact structure or the contact level dielectric layer.

53. The semiconductor structure of claim 41, further comprising an additional field effect transistor, wherein:

the additional field effect transistor includes an additional active region having a pair of longitudinal sidewalls and a pair of lateral sidewalls that contact and are laterally surrounded by the sidewalls of the additional portion of the trench isolation structure;

an additional gate structure overlying the additional active region, the additional gate structure comprising an additional gate dielectric, an additional gate electrode, and a conductive gate cap structure, the additional gate dielectric having a thickness greater than the first gate dielectric and the second gate dielectric, the conductive gate cap structure having a same thickness and a same material composition as the conductive gate connection structure; and is also provided with

The entire top surface of the additional gate electrode is in contact with the bottom surface of the conductive gate cap structure.

54. The semiconductor structure of claim 41, further comprising a passive device comprising at least one of a capacitor or a resistor, wherein:

the passive device includes a layer stack including, from bottom to top, a first dielectric layer, a first semiconductor plate, a second dielectric layer, a second semiconductor plate, and a conductive plate;

the first dielectric layer has the same material composition and the same thickness as the first gate dielectric;

the first semiconductor plate has the same thickness as the first gate electrode; and is also provided with

The conductive plate has the same material composition and the same thickness as the first section of the conductive gate connection structure.

55. A semiconductor structure comprising a first field effect transistor, wherein:

the first field effect transistor includes a first active region including a source region, a drain region, and a channel region between the source region and the drain region, a first gate dielectric overlying the active region, a first gate electrode overlying the first gate dielectric, and a trench isolation region surrounding the first active region;

The first field effect transistor does not include an edge region in which the first gate electrode extends through the active region in a horizontal direction perpendicular to a direction from the source region to the drain region;

the first gate electrode does not overlie a portion of the trench isolation region; and is also provided with

The entire occupied area of the first gate electrode is located above and within the lateral boundaries of the first active region.

56. The semiconductor structure of claim 55, wherein the first field effect transistor is located in a sense amplifier circuit of a driver circuit of a memory device.

57. The semiconductor structure of claim 55, further comprising a second field effect transistor, wherein:

the second field effect transistor comprises a second active region, a second gate dielectric overlying the active region and a second gate electrode overlying the second gate dielectric, the second active region comprising a source region, a drain region and a channel region between the source region and the drain region;

the trench isolation region surrounds the second active region;

the second field effect transistor includes the edge region in which the second gate electrode extends through the active region in a horizontal direction perpendicular to a direction from the source region to the drain region; and is also provided with

The second gate electrode overlies the trench isolation region in the edge region.

58. A method of forming a semiconductor structure, comprising:

forming a gate dielectric layer and a semiconductor gate material layer over the semiconductor material layer;

forming a trench isolation structure through the semiconductor gate material layer and the gate dielectric layer, wherein patterned portions of the semiconductor gate material layer and the gate dielectric layer include a first stack of a first gate dielectric plate and a first gate electrode material plate overlying a first active region of the semiconductor material layer, and a second stack of a second gate dielectric plate and a second gate electrode material plate overlying a second active region of the semiconductor material layer;

forming a conductive gate connection material layer over the first gate electrode material plate, the second gate electrode material plate, and the trench isolation structure;

patterning the conductive gate connection material layer into a conductive gate connection structure;

anisotropically etching portions of the first and second gate electrode material plates not covered with the conductive gate connection structure, wherein patterned portions of the first and second gate electrode material plates include first and second gate electrodes; and

The first gate dielectric plate and the second gate dielectric plate are patterned into a first gate dielectric and a second gate dielectric, respectively.

59. The method of claim 58, wherein:

the conductive gate connection material layer comprises a metal material deposited directly on top surfaces of the first gate electrode material plate, the second gate electrode material plate, and the trench isolation structure;

the method further comprises the steps of:

depositing planar dielectric spacers and planar semiconductor spacers over the top surfaces of the first gate electrode material plate, the second gate electrode material plate, and the trench isolation structure prior to forming the conductive gate connection material layer;

patterning the planar dielectric spacer layer and the planar semiconductor spacer layer, wherein remaining portions of the planar dielectric spacer layer and the planar semiconductor spacer layer are outside the regions of the first active region and the second active region, wherein the layer of conductive gate connection material is deposited over the planar semiconductor spacer layer; and

the conductive gate connection material layer, the planar semiconductor spacer layer, the first gate electrode material plate, the second gate electrode material plate, and the additional gate electrode material plate are patterned using the same anisotropic etching process.

60. The method of claim 59 further comprising depositing a planar dielectric spacer layer and a planar semiconductor spacer layer over the top surfaces of the first gate electrode material plate, the second gate electrode material plate, and the trench isolation structure prior to forming the layer of conductive gate connection material, wherein the layer of conductive gate connection material is deposited over the semiconductor spacer layer.