CN116865749A - A direct modulation VCO spread spectrum clock generator based on two-point injection technology - Google Patents
A direct modulation VCO spread spectrum clock generator based on two-point injection technology Download PDFInfo
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Abstract
Description
技术领域Technical field
本发明涉及展频时钟发生器领域,是一种基于两点注入技术的直接调制VCO展频时钟发生器。The invention relates to the field of spread spectrum clock generators and is a directly modulated VCO spread spectrum clock generator based on two-point injection technology.
背景技术Background technique
随着CMOS技术的发展,为满足系统的高性能应用需求,电子器件的工作频率也在不断提高。高速时钟在有线通信系统中至关重要,因为它们为发送或接收数据提供可靠的时序。如今,随着PCIe、USB或SATA等有线系统数据速率的快速提高,高速时钟引起的电磁干扰(EMI)问题变得越来越重要。过高的电磁干扰会对通信系统造成灾难性的损害。展频时钟(SSC)作为一种有效的、低成本的方法来降低电磁干扰,一直以来是研究的热点话题。With the development of CMOS technology, in order to meet the high-performance application requirements of the system, the operating frequency of electronic devices is also constantly increasing. High-speed clocks are critical in wired communications systems because they provide reliable timing for sending or receiving data. Today, with the rapid increase in data rates in wired systems such as PCIe, USB or SATA, the issue of electromagnetic interference (EMI) caused by high-speed clocks is becoming increasingly important. Excessive electromagnetic interference can cause catastrophic damage to communication systems. As an effective and low-cost method to reduce electromagnetic interference, spread spectrum clock (SSC) has always been a hot topic of research.
展频时钟发生器中,不同轮廓的调制信号形式,也拥有着不同的EMI降低效果,常见的调制信号轮廓有三角波调制、正弦波调制、Hershey-Kiss调制。如图2,正弦波调制展频时钟输出频率跟随正弦波变化,其频谱旁瓣比中间频率幅度高的多,导致EMI降低效果不理想;三角波调制展频时钟输出频率跟随三角波线性变化,频谱旁瓣峰值更低,频谱中心更平坦,因此,三角波调制比正弦波调制EMI降低效果更佳。Hershey-Kiss调制与三角波调制相比,输出频率的峰值能量能得到更大的衰减,但是由于难以获得较为理想的Hershey-Kiss调制信号,所以在电路实现中,我们更加希望采用的是三角波调制信号。In spread spectrum clock generators, modulation signal forms with different contours also have different EMI reduction effects. Common modulation signal contours include triangle wave modulation, sine wave modulation, and Hershey-Kiss modulation. As shown in Figure 2, the output frequency of the sine wave modulated spread spectrum clock changes with the sine wave, and its spectrum side lobes are much higher than the middle frequency, resulting in unsatisfactory EMI reduction effect; the output frequency of the triangle wave modulated spread spectrum clock changes linearly with the triangle wave, and the spectrum side lobes The lobe peak value is lower and the spectrum center is flatter. Therefore, triangular wave modulation has a better EMI reduction effect than sine wave modulation. Compared with triangular wave modulation, Hershey-Kiss modulation can achieve greater attenuation of the peak energy of the output frequency. However, since it is difficult to obtain an ideal Hershey-Kiss modulation signal, we prefer to use a triangular wave modulation signal in circuit implementation. .
针对基于锁相环(PLL)的直接调制VCO展频时钟发生器结构已经提出了一些技术。如图3,通过在环路滤波器LPF中的电阻R1和电阻R2之间注入调制电流Imod,电容C1和C2充当积分作用,在Vb点生成三角波调制信号,此结构需要满足R1C1=R2C2的先决条件才能获得理想的积分效果,并且通过引入电阻R3和电容C3抑制由于展频操作带来的尖峰(Spikes)。基于相同的直接调制VCO原理,如图4,通过在环路滤波器LPF中的电阻R1和电容C1之间注入调制电流Imod,引入额外一路电流IP2和单位增益缓冲器U1,实现电容倍增技术,减小直接调制VCO结构PLL环路带宽较小而导致的巨大电容C1,节省面积成本,在满足条件fmod<<1/(2πR1C2)时,电容C1充当积分作用,在Vdump点生成三角波调制信号。通过引入电阻R3和电容C3来进一步抑制参考杂散。Several techniques have been proposed for phase-locked loop (PLL)-based directly modulated VCO spread spectrum clock generator structures. As shown in Figure 3, by injecting the modulation current I mod between the resistor R 1 and the resistor R 2 in the loop filter LPF, the capacitors C 1 and C 2 act as an integral to generate a triangular wave modulation signal at the V point . This structure requires The ideal integration effect can be obtained only by meeting the prerequisite of R 1 C 1 =R 2 C 2 , and the spikes (Spikes) caused by the spread spectrum operation are suppressed by introducing the resistor R 3 and the capacitor C 3 . Based on the same direct modulation VCO principle, as shown in Figure 4, by injecting the modulation current I mod between the resistor R 1 and the capacitor C 1 in the loop filter LPF, an additional current I P2 and a unity gain buffer U 1 are introduced, Implement capacitance multiplication technology to reduce the huge capacitance C 1 caused by the small PLL loop bandwidth of the direct modulation VCO structure, saving area costs. When the condition f mod <<1/(2πR 1 C 2 ) is met, the capacitance C 1 acts as Integral action generates a triangular wave modulation signal at the V dump point. Reference spurs are further suppressed by introducing resistor R3 and capacitor C3 .
通过以上两种技术实现展频时钟,由于PLL负反馈环路和展频时钟的实现,时域上,鉴频鉴相器PFD模块会持续输出UP或DN信号使得控制电压上会出现尖峰(Spikes),为了消除尖峰以及对PLL参考杂散进一步的抑制,两种结构均引入了电阻R3和电容C3,与此同时,原本接近理想的三角波调制信号,会由于PLL环路带宽的选取不够小和环路滤波器的低通特性,其高频分量会被滤除导致其衰减为接近正弦波的调制信号,恶化了EMI降低效果,如果EMI降低无法达到现行通信标准,通信系统仍然会遭受损害。因此,发明一款拥有良好EMI降低效果的展频时钟发生器具有重要意义。The spread spectrum clock is realized through the above two technologies. Due to the implementation of the PLL negative feedback loop and the spread spectrum clock, in the time domain, the phase frequency detector PFD module will continue to output the UP or DN signal, causing spikes (Spikes) to appear on the control voltage. ), in order to eliminate spikes and further suppress PLL reference spurs, both structures introduce resistor R 3 and capacitor C 3 . At the same time, the originally close-to-ideal triangle wave modulation signal will be affected by insufficient selection of the PLL loop bandwidth. Due to the low-pass characteristics of the small and loop filter, its high-frequency component will be filtered out, causing it to attenuate into a modulated signal close to a sine wave, which worsens the EMI reduction effect. If the EMI reduction cannot meet the current communication standards, the communication system will still suffer damage. Therefore, it is of great significance to invent a spread spectrum clock generator with good EMI reduction effect.
发明内容Contents of the invention
针对现有技术存在的不足,本发明提供了一种基于两点注入技术的直接调制VCO展频时钟发生器,通过在环路滤波器LPF中的电阻R1和电容C1之间注入调制电流Imod的同时,增加一路补偿电流Icom注入环路滤波器LPF中的电阻R3和电容C3之间,以解决上述背景技术中提出的问题。In view of the shortcomings of the existing technology, the present invention provides a directly modulated VCO spread spectrum clock generator based on two-point injection technology, by injecting modulation current between the resistor R 1 and the capacitor C 1 in the loop filter LPF While I mod , a compensation current I com is added and injected between the resistor R 3 and the capacitor C 3 in the loop filter LPF to solve the problems raised in the above background technology.
为了实现上述目的,本发明是通过如下的技术方案来实现:一种基于两点注入技术的直接调制VCO展频时钟发生器,包括晶振FREF、鉴频鉴相器PFD、电荷泵CP1、可编程电荷泵CP2、可编程电荷泵CP3、环路滤波器LPF、压控振荡器VCO、分频器DIV1、分频器DIV2、分频器DIV3。所述分频器DIV1与晶振FREF相连提供PLL锁定需要的参考频率PLLREF,所述分频器DIV2与晶振FREF相连产生两个差分方波调制信号UP2和DN2,所述鉴频鉴相器PFD和分频器DIV1相连鉴别PLLREF信号和PLLFB信号频率和相位差产生UP和DN信号,所述电荷泵CP1和鉴频鉴相器PFD相连,根据UP和DN信号产生电流ICP注入环路滤波器,所述可编程电荷泵CP2和可编程电荷泵CP3均与分频器DIV2相连,分别产生调制电流Imod和补偿电流Icom注入环路滤波器LPF产生三角波调制信号,所述环路滤波器LPF与电荷泵CP1、可编程电荷泵CP2和可编程电荷泵CP3相连,分别将电流ICP、调制电流Imod、补偿电流Icom转化为压控振荡器VCO的控制电压Vctrl,所述压控振荡器VCO和环路滤波器LPF相连,根据环路滤波器LPF输出控制电压Vctrl产生输出时钟信号,实现时域上频率的调制变化,所述分频器DIV3与压控振荡器VCO相连产生反馈信号PLLFB反馈连接回鉴频鉴相器PFD输入端,实现PLL的最终锁定。In order to achieve the above objectives, the present invention is realized through the following technical solutions: a directly modulated VCO spread spectrum clock generator based on two-point injection technology, including a crystal oscillator F REF , a phase frequency detector PFD, a charge pump CP1, and a Programmable charge pump CP2, programmable charge pump CP3, loop filter LPF, voltage controlled oscillator VCO, frequency divider DIV1, frequency divider DIV2, frequency divider DIV3. The frequency divider DIV1 is connected to the crystal oscillator F REF to provide the reference frequency PLL REF required for PLL locking. The frequency divider DIV2 is connected to the crystal oscillator F REF to generate two differential square wave modulation signals UP2 and DN2. The frequency and phase identification are The charge pump CP1 is connected to the frequency divider DIV1 to identify the frequency and phase difference between the PLL REF signal and the PLL FB signal to generate UP and DN signals. The charge pump CP1 is connected to the phase frequency detector PFD and generates a current I CP based on the UP and DN signals. Loop filter, the programmable charge pump CP2 and the programmable charge pump CP3 are both connected to the frequency divider DIV2, respectively generating the modulation current I mod and the compensation current I com and injecting them into the loop filter LPF to generate a triangular wave modulation signal, the The loop filter LPF is connected to the charge pump CP1, the programmable charge pump CP2 and the programmable charge pump CP3, respectively converting the current I CP , the modulation current I mod and the compensation current I com into the control voltage V ctrl of the voltage controlled oscillator VCO. , the voltage-controlled oscillator VCO is connected to the loop filter LPF, and an output clock signal is generated according to the loop filter LPF output control voltage V ctrl to achieve modulation changes in frequency in the time domain. The frequency divider DIV3 is connected to the voltage-controlled The oscillator VCO is connected to generate a feedback signal PLL FB feedback is connected back to the input terminal of the phase frequency detector PFD to achieve the final locking of the PLL.
优选的,所述环路滤波器LPF由电阻R1、电阻R3、电阻R4、电容C1、电容C2、电容C3、电容C4组成,所述电容C1一端接地,另一端和电阻R1相连,所述电阻R1一端和电容C1相连,另一端和电容C2、电阻R3相连于一点,所述电容C2一端接地,另一端和电阻R1、电阻R3相连于一点,所述电阻R3一端和电阻R1、电容C2相连于一点,另一端和电容C3、电阻R4相连于一点,所述电容C3一端接地,另一端和电阻R3、电阻R4相连于一点,所述电阻R4一端和电阻R3、电容C3相连于一点,另一端和电容C4相连,所述电容C4一端接地,另一端和电阻R4相连。整体环路滤波器LPF由四阶组成,拥有四个极点,因此所述整体PLL为五阶二型PLL环路。Preferably, the loop filter LPF is composed of a resistor R 1 , a resistor R 3 , a resistor R 4 , a capacitor C 1 , a capacitor C 2 , a capacitor C 3 and a capacitor C 4 . One end of the capacitor C 1 is grounded and the other end is grounded. It is connected to the resistor R 1. One end of the resistor R 1 is connected to the capacitor C 1 , and the other end is connected to the capacitor C 2 and the resistor R 3. One end of the capacitor C 2 is grounded, and the other end is connected to the resistor R 1 and the resistor R 3. Connected to one point, one end of the resistor R 3 is connected to the resistor R 1 and the capacitor C 2 , and the other end is connected to the capacitor C 3 and the resistor R 4 . One end of the capacitor C 3 is grounded, and the other end is connected to the resistor R 3 , resistor R 4 is connected to one point, one end of the resistor R 4 is connected to the resistor R 3 and capacitor C 3 to one point, and the other end is connected to the capacitor C 4 . One end of the capacitor C 4 is grounded, and the other end is connected to the resistor R 4 . The overall loop filter LPF is composed of fourth order and has four poles, so the overall PLL is a fifth-order type-2 PLL loop.
优选的,所述环路滤波器LPF与所述电荷泵CP1、所述可编程电荷泵CP2、所述可编程电荷泵CP3均有连接。所述电荷泵CP1输出与所述环路滤波器LPF中电阻R1和电容C2之间相连于一点。电荷泵CP1产生PLL主环路电流ICP注入所述环路滤波器LPF中电阻R1和电容C2之间。所述可编程电荷泵CP2输出与所述环路滤波器LPF中电阻R1和电容C1之间相连于一点。可编程电荷泵CP2产生调制电流Imod注入所述环路滤波器LPF中电阻R1和电容C1之间。所述可编程电荷泵CP3输出与所述环路滤波器LPF中电阻R3、电阻R4、电容C3之间相连于一点。可编程电荷泵CP3产生补偿电流Icom注入所述环路滤波器LPF中电阻R3和电容C3之间。其中,所述可编程电荷泵CP2、所述可编程电荷泵CP3电流大小可调。Preferably, the loop filter LPF is connected to the charge pump CP1, the programmable charge pump CP2, and the programmable charge pump CP3. The output of the charge pump CP1 is connected to a point between the resistor R 1 and the capacitor C 2 in the loop filter LPF. The charge pump CP1 generates the PLL main loop current I CP and injects it into the loop filter LPF between the resistor R 1 and the capacitor C 2 . The output of the programmable charge pump CP2 is connected to a point between the resistor R 1 and the capacitor C 1 in the loop filter LPF. The programmable charge pump CP2 generates a modulated current I mod and injects it into the loop filter LPF between the resistor R 1 and the capacitor C 1 . The output of the programmable charge pump CP3 and the resistor R 3 , resistor R 4 and capacitor C 3 in the loop filter LPF are connected to one point. The programmable charge pump CP3 generates a compensation current I com and injects it into the loop filter LPF between the resistor R 3 and the capacitor C 3 . Wherein, the current size of the programmable charge pump CP2 and the programmable charge pump CP3 is adjustable.
优选的,所述环路滤波器LPF输出与所述压控振荡器VCO输入相连接,所述环路滤波器LPF中电阻R4和电容C4与所述压控振荡器VCO输入相连于一点。所述环路滤波器LPF输出Vctrl信号控制压控振荡器VCO产生相应频率变化。Preferably, the output of the loop filter LPF is connected to the input of the voltage controlled oscillator VCO, and the resistor R 4 and capacitor C 4 in the loop filter LPF are connected to the input of the voltage controlled oscillator VCO at one point. . The loop filter LPF outputs the V ctrl signal to control the voltage controlled oscillator VCO to produce corresponding frequency changes.
本发明的有益效果:本发明是一种基于两点注入技术的直接调制VCO展频时钟发生器,提出了一种两点注入技术实现展频时钟。Beneficial effects of the present invention: The present invention is a directly modulated VCO spread spectrum clock generator based on two-point injection technology, and proposes a two-point injection technology to realize the spread spectrum clock.
1、采用可编程电荷泵CP2向环路滤波器LPF注入调制电流Imod的同时,引入额外可编程电荷泵CP3,向环路滤波器LPF中的电阻R3和电容C3之间注入补偿电流Icom,补偿了由于PLL环路带宽和滤波器低通特性而造成的三角波调制信号衰减成为正弦波调制信号的劣势,在消除压控振荡器VCO控制电压上尖峰(Spikes)的同时考虑到杂散抑制,引入四阶环路滤波器LPF,实现了更佳的EMI降低效果。1. While using the programmable charge pump CP2 to inject the modulation current I mod into the loop filter LPF, an additional programmable charge pump CP3 is introduced to inject a compensation current between the resistor R 3 and the capacitor C 3 in the loop filter LPF. I com , which compensates for the disadvantage that the triangular wave modulation signal is attenuated into a sine wave modulation signal due to the PLL loop bandwidth and filter low-pass characteristics. It eliminates the spikes (Spikes) on the voltage controlled oscillator VCO control voltage while taking into account the noise. For dissipation suppression, the fourth-order loop filter LPF is introduced to achieve better EMI reduction effect.
2、本发明实现了线性调制,可以根据用户需求改变可编程电荷泵CP2和可编程电荷泵CP3电流的大小,实现不同展频深度,对PVT变化具有一定的忍耐度,适合应用于高速通信领域。2. The present invention realizes linear modulation, can change the current size of programmable charge pump CP2 and programmable charge pump CP3 according to user needs, achieves different spread spectrum depths, has a certain tolerance for PVT changes, and is suitable for application in the field of high-speed communications .
附图说明Description of the drawings
通过阅读参照以下附图对非限制性实例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of the non-limiting examples with reference to the following drawings:
图1为本发明提出的基于两点注入技术的展频时钟发生器结构示意图;Figure 1 is a schematic structural diagram of a spread spectrum clock generator based on two-point injection technology proposed by the present invention;
图2为不同轮廓调制信号及调制后的频谱图;Figure 2 shows modulated signals with different contours and the spectrum diagram after modulation;
图3为已有的基于环路滤波器LPF电阻间注入展频时钟发生器示意图;Figure 3 is a schematic diagram of an existing spread spectrum clock generator based on injection between LPF resistors of a loop filter;
图4为已有的基于电容倍增技术展频时钟发生器示意图;Figure 4 is a schematic diagram of an existing spread spectrum clock generator based on capacitance multiplication technology;
图5为本发明中环路滤波器LPF和相关注入点的电路原理图;Figure 5 is a circuit schematic diagram of the loop filter LPF and related injection points in the present invention;
图6为二阶环路滤波器LPF压控振荡器VCO控制电压Vctrl仿真图;Figure 6 is a simulation diagram of the second-order loop filter LPF voltage controlled oscillator VCO control voltage V ctrl ;
图7为三阶环路滤波器LPF压控振荡器VCO控制电压Vctrl仿真图;Figure 7 is a simulation diagram of the third-order loop filter LPF voltage controlled oscillator VCO control voltage V ctrl ;
图8为本发明基于两点注入技术压控振荡器VCO控制电压Vctrl仿真图;Figure 8 is a simulation diagram of the control voltage Vctrl of the voltage controlled oscillator VCO based on the two-point injection technology of the present invention;
图9为本发明展频开启后EMI降低效果图。Figure 9 is a diagram showing the EMI reduction effect after the spread spectrum is turned on according to the present invention.
具体实施方式Detailed ways
为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例(电荷泵CP1、可编程电荷泵CP2、可编程电荷泵CP3的选择可以多种;PLL环路带宽的选取可以根据用户对锁定时间、噪声性能等综合考量进行选取,同时也可以采取图4所示的单位增益缓冲器结构调制注入方式,以减小环路滤波器LPF中电容面积,这些均在本专利保护范围内)。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。In order to make it easy to understand the technical means, creative features, objectives and effects of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, all The described embodiments are only some of the embodiments of the present invention, not all of them (charge pump CP1, programmable charge pump CP2, and programmable charge pump CP3 can be selected in many ways; the selection of the PLL loop bandwidth can be based on the user's requirements. The selection should be made based on comprehensive considerations such as locking time and noise performance. At the same time, the modulation injection method of the unit gain buffer structure shown in Figure 4 can also be used to reduce the capacitor area in the loop filter LPF. These are all within the scope of this patent protection) . Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.
展频时钟(Spread Spectrum Clock,简称SSC):是通过频率调制的手段,将时钟信号频谱上集中在窄频带范围内的能量分散到设定的某一宽频带范围内,从而降低时钟信号基波频率及奇次谐波频率的能量(幅度),是降低系统电磁干扰(Electromagneticinterference,简称EMI)的有效手段。Spread Spectrum Clock (SSC): It uses frequency modulation to disperse the energy concentrated in the narrow frequency band of the clock signal spectrum into a set wide frequency range, thereby reducing the fundamental wave of the clock signal. Frequency and the energy (amplitude) of odd harmonic frequencies are effective means of reducing system electromagnetic interference (EMI).
直接调制VCO:展频时钟发生器(Spread Spectrum Clock Generator,简称SSCG)大多基于锁相环(Phase Locked Loop,简称PLL)实现,通过直接调制压控振荡器(Voltage-controlled Oscillator,简称VCO)输入控制电压的方式达成频率调制的手段称为直接调制VCO。Directly modulate VCO: Spread Spectrum Clock Generator (SSCG) is mostly implemented based on Phase Locked Loop (PLL), by directly modulating the input of Voltage-controlled Oscillator (VCO) The method of controlling voltage to achieve frequency modulation is called direct modulation VCO.
展频调制轮廓:展频的调制轮廓决定了功率谱上的表现形式,常见的调制轮廓有三角波调制、正弦波调制、Hershey-Kiss调制。Spread spectrum modulation profile: The spread spectrum modulation profile determines the form of expression on the power spectrum. Common modulation profiles include triangle wave modulation, sine wave modulation, and Hershey-Kiss modulation.
参考杂散:由于电荷泵充放电电流不匹配等非理想因素引起的锁相环输出信号具有周期性的杂散成分,频谱上体现为距输出中心频率左右两边参考源频率大小处的突起。Reference spurs: The phase-locked loop output signal caused by non-ideal factors such as charge pump charge and discharge current mismatch has periodic spurious components, which are reflected in the spectrum as protrusions at the reference source frequency on the left and right sides of the output center frequency.
请参阅图1,本发明公开了一种基于两点注入技术的直接调制VCO展频时钟发生器,包括晶振FREF、鉴频鉴相器PFD、电荷泵CP1、可编程电荷泵CP2、可编程电荷泵CP3、环路滤波器LPF、压控振荡器VCO、分频器DIV1、分频器DIV2、分频器DIV3。分频器DIV1与晶振FREF相连提供PLL锁定需要的参考频率PLLREF,分频器DIV2与晶振FREF相连产生两个差分方波调制信号UP2和DN2,鉴频鉴相器PFD和分频器DIV1相连鉴别PLLREF信号和PLLFB信号频率和相位差产生UP和DN信号,电荷泵CP1和鉴频鉴相器PFD相连,根据UP和DN信号产生电流ICP注入环路滤波器,可编程电荷泵CP2和可编程电荷泵CP3均与分频器DIV2相连,分别产生调制电流Imod和补偿电流Icom注入环路滤波器LPF产生三角波调制信号,环路滤波器LPF与电荷泵CP1、可编程电荷泵CP2和可编程电荷泵CP3相连,分别将电流ICP、调制电流Imod、补偿电流Icom转化为压控振荡器VCO的控制电压Vctrl,压控振荡器VCO和环路滤波器LPF相连,根据环路滤波器LPF输出控制电压Vctrl产生输出时钟信号,实现时域上频率的调制变化,分频器DIV3与压控振荡器VCO相连产生反馈信号PLLFB反馈连接回鉴频鉴相器PFD输入端,实现PLL的最终锁定。Please refer to Figure 1. The present invention discloses a directly modulated VCO spread spectrum clock generator based on two-point injection technology, including a crystal oscillator F REF , a phase frequency detector PFD, a charge pump CP1, a programmable charge pump CP2, a programmable Charge pump CP3, loop filter LPF, voltage controlled oscillator VCO, frequency divider DIV1, frequency divider DIV2, frequency divider DIV3. The frequency divider DIV1 is connected to the crystal oscillator F REF to provide the reference frequency PLL REF required for PLL locking. The frequency divider DIV2 is connected to the crystal oscillator F REF to generate two differential square wave modulation signals UP2 and DN2. The phase frequency detector PFD and frequency divider DIV1 is connected to identify the frequency and phase difference between the PLL REF signal and the PLL FB signal to generate UP and DN signals. The charge pump CP1 is connected to the phase frequency detector PFD. The current ICP is generated according to the UP and DN signals. CP is injected into the loop filter and the charge is programmable. The pump CP2 and the programmable charge pump CP3 are both connected to the frequency divider DIV2, and respectively generate the modulation current I mod and the compensation current I com and inject them into the loop filter LPF to generate a triangular wave modulation signal. The loop filter LPF is connected with the charge pump CP1 and the programmable charge pump CP2. The charge pump CP2 is connected to the programmable charge pump CP3, which converts the current I CP , the modulation current I mod , and the compensation current I com into the control voltage V ctrl of the voltage-controlled oscillator VCO, the voltage-controlled oscillator VCO, and the loop filter LPF respectively. Connected, the output clock signal is generated according to the loop filter LPF output control voltage V ctrl to achieve modulation changes in frequency in the time domain. The frequency divider DIV3 is connected to the voltage controlled oscillator VCO to generate a feedback signal PLL FB feedback is connected back to the frequency and phase detector. The PFD input terminal of the device realizes the final locking of the PLL.
环路滤波器LPF由电阻R1、电阻R3、电阻R4、电容C1、电容C2、电容C3、电容C4组成,电容C1一端接地,另一端和电阻R1相连,电阻R1一端和电容C1相连,另一端和电容C2、电阻R3相连于一点,电容C2一端接地,另一端和电阻R1、电阻R3相连于一点,电阻R3一端和电阻R1、电容C2相连于一点,另一端和电容C3、电阻R4相连于一点,电容C3一端接地,另一端和电阻R3、电阻R4相连于一点,电阻R4一端和电阻R3、电容C3相连于一点,另一端和电容C4相连,电容C4一端接地,另一端和电阻R4相连。整体环路滤波器LPF由四阶组成,拥有四个极点,因此整体PLL为五阶二型PLL环路。The loop filter LPF is composed of resistor R 1 , resistor R 3 , resistor R 4 , capacitor C 1 , capacitor C 2 , capacitor C 3 , and capacitor C 4 . One end of capacitor C 1 is grounded, and the other end is connected to resistor R 1 . One end of R 1 is connected to capacitor C 1 , the other end is connected to capacitor C 2 and resistor R 3 at one end. One end of capacitor C 2 is connected to ground. The other end is connected to resistor R 1 and resistor R 3 at one point. One end of resistor R 3 is connected to resistor R 1. Capacitor C 2 is connected to one point, and the other end is connected to capacitor C 3 and resistor R 4. One end of capacitor C 3 is connected to ground, and the other end is connected to resistor R 3 and resistor R 4. One end of resistor R 4 is connected to resistor R. 3. Capacitor C 3 is connected to one point, and the other end is connected to capacitor C 4. One end of capacitor C 4 is connected to ground, and the other end is connected to resistor R 4 . The overall loop filter LPF is composed of fourth order and has four poles, so the overall PLL is a fifth-order type 2 PLL loop.
环路滤波器LPF与电荷泵CP1、可编程电荷泵CP2、可编程电荷泵CP3均有连接。电荷泵CP1输出与环路滤波器LPF中电阻R1和电容C2之间相连于一点。电荷泵CP1产生PLL主环路电流ICP注入环路滤波器LPF中电阻R1和电容C2之间。可编程电荷泵CP2输出与环路滤波器LPF中电阻R1和电容C1之间相连于一点。可编程电荷泵CP2产生调制电流Imod注入环路滤波器LPF中电阻R1和电容C1之间。可编程电荷泵CP3输出与环路滤波器LPF中电阻R3、电阻R4、电容C3之间相连于一点。可编程电荷泵CP3产生补偿电流Icom注入环路滤波器LPF中电阻R3和电容C3之间。其中,可编程电荷泵CP2、可编程电荷泵CP3电流大小可调。The loop filter LPF is connected to the charge pump CP1, the programmable charge pump CP2, and the programmable charge pump CP3. The output of the charge pump CP1 is connected to a point between the resistor R 1 and the capacitor C 2 in the loop filter LPF. The charge pump CP1 generates the PLL main loop current I CP and injects it into the loop filter LPF between the resistor R 1 and the capacitor C 2 . The output of the programmable charge pump CP2 is connected to a point between the resistor R 1 and the capacitor C 1 in the loop filter LPF. The programmable charge pump CP2 generates a modulated current I mod and injects it into the loop filter LPF between the resistor R 1 and the capacitor C 1 . The output of the programmable charge pump CP3 is connected to one point between the resistor R 3 , the resistor R 4 and the capacitor C 3 in the loop filter LPF. The programmable charge pump CP3 generates a compensation current I com and injects it into the loop filter LPF between the resistor R 3 and the capacitor C 3 . Among them, the current size of programmable charge pump CP2 and programmable charge pump CP3 is adjustable.
环路滤波器LPF输出与压控振荡器VCO输入相连接,环路滤波器LPF中电阻R4和电容C4与压控振荡器VCO输入相连于一点。环路滤波器LPF输出Vctrl信号控制压控振荡器VCO产生相应频率变化。The output of the loop filter LPF is connected to the input of the voltage controlled oscillator VCO. The resistor R 4 and capacitor C 4 in the loop filter LPF are connected to the input of the voltage controlled oscillator VCO at one point. The loop filter LPF outputs the V ctrl signal to control the voltage controlled oscillator VCO to produce corresponding frequency changes.
本发明工作原理:Working principle of the invention:
本发明公开了一种基于两点注入技术的直接调制VCO展频时钟发生器,如图1,分频器DIV1、鉴频鉴相器PFD、电荷泵CP1、环路滤波器LPF、压控振荡器VCO和分频器DIV3构成常规PLL的主体结构,实现PLL锁定至目标频率。The invention discloses a direct modulation VCO spread spectrum clock generator based on two-point injection technology, as shown in Figure 1, frequency divider DIV1, phase frequency detector PFD, charge pump CP1, loop filter LPF, voltage controlled oscillation The VCO and the frequency divider DIV3 form the main structure of a conventional PLL, enabling the PLL to be locked to the target frequency.
分频器DIV2对晶振FREF进行分频,产生两个差分周期调制信号UP2(fmodp)和DN2(fmodn),通常情况下,fmodp和fmodn的频率范围在30kHz到70kHz之间。可编程电荷泵CP2根据周期信号UP2(fmodp)和DN2(fmodn)产生调制电流Imod注入环路滤波器LPF中的电阻R1和电容C1之间,由此,我们可以写出从Imod到Vctrl的传递函数如下:The frequency divider DIV2 divides the crystal oscillator F REF to generate two differential periodic modulation signals UP2(f modp ) and DN2(f modn ). Normally, the frequency range of f modp and f modn is between 30kHz and 70kHz. The programmable charge pump CP2 generates a modulated current I mod based on the periodic signals UP2(f modp ) and DN2(f modn ) and injects it between the resistor R 1 and the capacitor C 1 in the loop filter LPF. From this, we can write from The transfer function from I mod to V ctrl is as follows:
式中R1、C1、C2分别为环路滤波器LPF中的电阻R1、电容C1和电容C2,保持调制频率fmod<<(C1+C2)/(2πR1C1C2),即可得到一个理想的积分效果,这样上式可以化简为In the formula, R 1 , C 1 and C 2 are the resistor R 1 , capacitor C 1 and capacitor C 2 in the loop filter LPF respectively, maintaining the modulation frequency f mod <<(C 1 +C 2 )/(2πR 1 C 1 C 2 ), an ideal integral effect can be obtained, so the above formula can be simplified to
那么三角波调制信号可以由调制电流Imod积分得到,可以在Vctrl节点产生周期性的三角信号,并且周期信号UP2(fmodp)和DN2(fmodn)的频率和调制电流Imod以及产生的三角波调制信号三者频率相同,因此,此注入方式可以用于实现展频时钟。Then the triangular wave modulation signal can be obtained by integrating the modulation current I mod , and a periodic triangular signal can be generated at the V ctrl node, and the frequency of the periodic signals UP2(f modp ) and DN2(f modn ) and the modulation current I mod and the generated triangular wave The three modulated signals have the same frequency, so this injection method can be used to implement spread spectrum clocking.
在传统基于PLL的直接调制VCO展频时钟发生器中,由于三角波调制信号施加在压控振荡器VCO控制电压上,调制路径整体呈现高通特性,所以需要选择极低的PLL环路带宽,保证调制信号可以完整的通过PLL环路,除此之外,极低的PLL环路带宽还有利于滤除由于展频操作带来鉴频鉴相器PFD输出的调制分量。如前面所述,调制信号fmodp和fmodn频率范围在30kHz到70kHz之间,所以为了实现展频时钟,需要将PLL的环路带宽设置在3kHz到7kHz之间。不幸的是,极小的环路带宽需要巨大的环路滤波器LPF电容C1,增大了面积成本,另一方面加长了PLL的锁定时间。因此发明一款既拥有良好展频性能又不增加面积成本和锁定时间的直接调制VCO展频时钟发生器具有十分重要的意义。In the traditional PLL-based direct modulation VCO spread spectrum clock generator, since the triangular wave modulation signal is applied to the voltage controlled oscillator VCO control voltage, the entire modulation path exhibits high-pass characteristics, so it is necessary to select an extremely low PLL loop bandwidth to ensure modulation The signal can pass through the PLL loop completely. In addition, the extremely low PLL loop bandwidth is also helpful in filtering out the modulation component of the phase frequency detector PFD output due to the spread spectrum operation. As mentioned earlier, the frequency range of the modulation signals f modp and f modn is between 30kHz and 70kHz, so in order to implement the spread spectrum clock, the loop bandwidth of the PLL needs to be set between 3kHz and 7kHz. Unfortunately, the extremely small loop bandwidth requires a huge loop filter LPF capacitor C 1 , which increases the area cost and, on the other hand, lengthens the locking time of the PLL. Therefore, it is of great significance to invent a directly modulated VCO spread spectrum clock generator that has good spread spectrum performance without increasing area cost and locking time.
如前面所分析,从Imod到Vctrl点的传输函数表明,Vctrl点可生成周期性的三角波调制信号。如果采用二阶环路滤波器LPF,由于调制电流Imod的注入和展频时钟的实现,在时域上,鉴频鉴相器(PFD)会鉴别出PLLFB和PLLREF之间的相位差,输出UP和DN信号,使得电荷泵CP1对环路滤波器进行周期性的充放电,从而在Va点看到尖峰(Spikes),这是不希望看到的。幸运的是,可以通过在环路滤波器LPF中引入电阻R3和电容C3对其进行滤除,但是在滤除尖峰的同时,Va点三角波调制信号的高频分量也会被滤除,这样会衰减三角调制信号的峰值。并且,如果PLL环路带宽选取过大,在Va点已经是经环路滤波器LPF中电阻R1和电容C2低通滤波后的周期信号,再经过电阻R3和电容C3的滤波,严重的情况下,会衰减为接近正弦波调制信号,恶化EMI降低效果。As analyzed previously, the transfer function from I mod to V ctrl point shows that the V ctrl point can generate a periodic triangular wave modulation signal. If the second-order loop filter LPF is used, due to the injection of the modulation current I mod and the implementation of the spread spectrum clock, in the time domain, the phase frequency detector (PFD) will identify the phase difference between PLL FB and PLL REF , outputting UP and DN signals, causing the charge pump CP1 to periodically charge and discharge the loop filter, thereby seeing spikes (Spikes) at the V a point, which is undesirable. Fortunately, it can be filtered by introducing resistor R 3 and capacitor C 3 in the loop filter LPF, but while filtering out the spikes, the high-frequency component of the triangle wave modulation signal at point Va will also be filtered out. , which will attenuate the peak value of the triangular modulated signal. Moreover, if the PLL loop bandwidth is selected too large, at point V a it is already a periodic signal that has been low-pass filtered by the resistor R 1 and capacitor C 2 in the loop filter LPF, and then filtered by the resistor R 3 and capacitor C 3 , in severe cases, it will attenuate to a modulation signal close to a sine wave, worsening the EMI reduction effect.
鉴于上述问题,本发明提出了引入额外可编程电荷泵CP3,它拥有和可编程电荷泵CP2同样的操作,不同的是它们的电流大小,可编程电荷泵CP3的补偿电流Icom小于可编程电荷泵CP2的调制电流Imod,类似地,只需要保持环路滤波器LPF中电阻R1、电容C1、电容C2、电容R3的等效阻抗之和不超过电容C3的等效阻抗,从补偿电流Icom注入点到Vctrl的传输函数为:In view of the above problems, the present invention proposes to introduce an additional programmable charge pump CP3, which has the same operation as the programmable charge pump CP2. The difference is their current size. The compensation current I com of the programmable charge pump CP3 is smaller than the programmable charge pump CP3. The modulation current I mod of the pump CP2 is similarly required to keep the sum of the equivalent impedances of the resistor R 1 , capacitor C 1 , capacitor C 2 and capacitor R 3 in the loop filter LPF not exceeding the equivalent impedance of the capacitor C 3 , the transfer function from the compensation current I com injection point to V ctrl is:
式中R4、C3、C4分别为环路滤波器LPF中的电阻R4、电容C3和电容C4,如果调制频率fmod<<(C3+C4)/(2πR4C3C4),即可得到一个理想的积分效果,所以我们可以将上式化简为:In the formula, R 4 , C 3 and C 4 are the resistor R 4 , capacitor C 3 and capacitor C 4 in the loop filter LPF respectively. If the modulation frequency f mod <<(C 3 +C 4 )/(2πR 4 C 3 C 4 ), we can get an ideal integral effect, so we can simplify the above formula to:
根据上式,可以知道补偿电流Icom的注入到压控振荡器VCO控制电压Vctrl仍然是积分效果,即可以实现对衰减后的正弦波调制信号的补偿效果。只需要合理调整可编程电荷泵CP3的电流大小就可以实现补偿将其恢复为三角波调制。除此之外,补偿电流Icom的引入可以放宽传统直接调制VCO展频时钟发生器结构对于PLL环路带宽的限制,即使原本接近理想的三角波调制信号经环路滤波器LPF滤波为正弦波调制信号,也可以通过调整补偿电流Icom的大小将其补偿回来,有效地减小了PLL的锁定时间。According to the above formula, it can be known that the injection of the compensation current I com into the voltage controlled oscillator VCO control voltage V ctrl still has an integral effect, that is, the compensation effect on the attenuated sine wave modulation signal can be achieved. It only needs to reasonably adjust the current size of the programmable charge pump CP3 to achieve compensation and restore it to triangular wave modulation. In addition, the introduction of the compensation current I com can relax the limitation of the traditional direct modulation VCO spread spectrum clock generator structure on the PLL loop bandwidth, even if the originally close-to-ideal triangle wave modulation signal is filtered into a sine wave modulation by the loop filter LPF signal, it can also be compensated back by adjusting the size of the compensation current I com , effectively reducing the locking time of the PLL.
考虑到杂散抑制,为了保持良好的参考杂散抑制性能,需要选择较小的极点位置,考虑到环路滤波器LPF的主极点的位置为:Considering spurious suppression, in order to maintain good reference spurious suppression performance, a smaller pole position needs to be selected. Considering that the position of the main pole of the loop filter LPF is:
从上述公式可知,要想获得较好的参考杂散抑制效果,需要增大Ceq的值,其中Ceq=C1·C2/(C1+C2),C1、C2分别为环路滤波器LPF中电容C1和电容C2。结合前面调制频率fmod的先决条件,Ceq的增大会增加环路滤波器LPF中电容对调制电流Imod进行积分的非线性,所以此结构在调制线性度和杂散抑制之间存在折衷,然而本发明优先考虑调制线性度,减小了Ceq的取值,使得三角波调制信号可以实现更为理想的积分效果,更加线性,通过在环路滤波器LPF中增加额外的电阻R4和电容C4实现更好的参考杂散抑制。It can be seen from the above formula that in order to obtain better reference spurious suppression effect, the value of C eq needs to be increased, where C eq =C 1 ·C 2 /(C 1 + C 2 ), C 1 and C 2 are respectively Capacitor C 1 and capacitor C 2 in the loop filter LPF. Combined with the previous prerequisite of modulation frequency f mod , the increase of C eq will increase the nonlinearity of the capacitor in the loop filter LPF integrating the modulation current I mod , so this structure has a trade-off between modulation linearity and spurious suppression. However, the present invention gives priority to modulation linearity and reduces the value of C eq so that the triangular wave modulated signal can achieve a more ideal integration effect and be more linear by adding an additional resistor R 4 and capacitor in the loop filter LPF. C 4 achieves better reference spur suppression.
本发明采用的环路滤波器LPF结构如图5,基于四阶环路滤波器LPF实现了较好的三角波线性调制。The structure of the loop filter LPF used in the present invention is shown in Figure 5. Based on the fourth-order loop filter LPF, better triangular wave linear modulation is achieved.
给出具体的仿真结果辅助验证本发明的理论正确性。如图6所示为采用二阶环路滤波器LPF,则进入压控振荡器VCO的控制电压Vctrl会夹带着尖峰(Spikes),图7为引入三阶环路滤波器LPF滤除尖峰,但是调制信号会被进一步衰减。最终,本发明提出的引入补偿电流Icom和电阻R4、电容C4效果如图9所示,进入压控振荡器VCO的控制电压Vctrl曲线可以被恢复为近似三角调制波信号。图9为本发明展频开启前和开启后的频谱对比图,从图中可以看出,本发明提出的展频时钟发生器EMI降低可达14.48dB。Specific simulation results are given to assist in verifying the theoretical correctness of the present invention. As shown in Figure 6, the second-order loop filter LPF is used, and the control voltage V ctrl entering the voltage-controlled oscillator VCO will carry spikes (Spikes). Figure 7 shows the introduction of the third-order loop filter LPF to filter out the spikes. But the modulated signal will be further attenuated. Finally, the effect of introducing the compensation current I com , resistor R 4 and capacitor C 4 proposed by the present invention is shown in Figure 9. The control voltage V ctrl curve entering the voltage controlled oscillator VCO can be restored to an approximate triangular modulated wave signal. Figure 9 is a spectrum comparison chart before and after the spread spectrum is turned on according to the present invention. It can be seen from the figure that the EMI of the spread spectrum clock generator proposed by the present invention can be reduced by up to 14.48dB.
以上内容描述了本发明的工作原理、主要特征和本发明相较于传统结构的优点。对于本领域的技术人员而言,显然本发明不限于上述示范性实施例的细节描述,而且在不背离本发明的理论或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,本实施例应当是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,旨在将落在权利要求的含义和范围内的所有变化囊括在本发明创新型内,不应将权利要求中的任何附图标记视为限制所涉及的权利要求。The above content describes the working principle, main features and advantages of the present invention compared with traditional structures. It is obvious to those skilled in the art that the present invention is not limited to the detailed description of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the theory or basic characteristics of the present invention. Therefore, this embodiment should be exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that the meaning and scope of the claims will fall All changes within are included in the novelty of the present invention, and any reference signs in the claims should not be construed as limiting the involved claims.
此外,应当理解,说明书的这种叙述仅仅是为了更加清晰易懂。本领域技术人员应当将说明书作为一个整体,可以对前述各实施例所采用的技术方案进行修改,或者对其中部分技术特征进行等同替换。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。Furthermore, it should be understood that such description in the specification is merely for clarity and ease of understanding. Those skilled in the art should take the description as a whole and may modify the technical solutions adopted in the foregoing embodiments, or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.
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