CN116863869B - Arrangement structure of sub-pixels and control method thereof - Google Patents
Arrangement structure of sub-pixels and control method thereof Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
A sub-pixel arrangement structure and a control method thereof belong to the technical field of display screens, and solve the problems that a non-uniform quadrilateral arrangement mode can not provide uniform image display effect, the display effect is more general, the production efficiency is lower, and the production cost is higher. The arrangement structure is formed by arranging a plurality of periodic sub-pixel combinations in a matrix form; the plurality of periodic sub-pixel combinations are formed by arranging six sub-pixel combinations in a matrix form in the horizontal direction; the six sub-pixel combinations are all composed of four adjacent sub-pixels, and the four adjacent sub-pixels form a square arrangement structure. The sub-pixel arrangement structure can be applied to LED display screens of various types.
Description
Technical Field
The invention relates to the technical field of display screens, in particular to a subpixel arrangement structure and a control method thereof.
Background
An LED (light emitting diode) display screen is a display technology using light emitting diodes as sub-pixels. It consists of many small sub-pixels, each of which is controlled in brightness and color to form an image or video. Therefore, the LED display screen has the characteristics of high brightness, low power consumption, long service life and the like, and has the advantages of good color expression, high contrast, high refresh rate, customizable performance and the like.
The arrangement mode of the LED display screen can be selected according to different application scenes and requirements. For example, a quadrilateral arrangement, a hexagonal arrangement, etc. The quadrilateral arrangement mode is widely applied to the technical field of LED display screens due to the advantages of unique aesthetic effect, capability of realizing diversified layout, good expansibility and adaptability and the like.
However, the existing quadrilateral arrangement adopts non-uniform arrangement modes of sub-pixels such as diamond, parallelogram and the like, and the non-uniform arrangement modes can cause the following defects:
1) The uniform image display effect cannot be provided;
2) Under the condition that the image display is undistorted, the display effect is more general;
3) The production mode is complex, so that the production efficiency is low and the production cost is high.
In summary, the conventional LED display screen adopts a non-uniform quadrilateral arrangement manner, which results in failure to provide uniform image display effect, general display effect, low production efficiency and high production cost.
Disclosure of Invention
The invention solves the problems that the non-uniform quadrilateral arrangement mode can not provide uniform image display effect, the display effect is more general, the production efficiency is lower and the production cost is higher.
The invention relates to a subpixel arrangement structure, which is formed by arranging a plurality of periodic subpixel combinations in a matrix form;
the plurality of periodic sub-pixel combinations are formed by arranging six sub-pixel combinations in a matrix form in the horizontal direction;
the six sub-pixel combinations are all composed of four adjacent sub-pixels;
the four adjacent sub-pixels form a square arrangement structure.
Further, in one embodiment of the present invention, the six sub-pixel combinations are a first sub-pixel combination, a second sub-pixel combination, a third sub-pixel combination, a fourth sub-pixel combination, a fifth sub-pixel combination, and a sixth sub-pixel combination, respectively;
the first sub-pixel combination, the second sub-pixel combination, the third sub-pixel combination, the fourth sub-pixel combination, the fifth sub-pixel combination and the sixth sub-pixel combination comprise four sub-pixels which are respectively a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel;
the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in a quadrilateral mode.
Further, in one embodiment of the present invention, the first subpixel and the second subpixel are arranged in the same row, and the third subpixel and the fourth subpixel are arranged in the same row;
the first sub-pixel and the third sub-pixel are arranged in the same column, and the second sub-pixel and the fourth sub-pixel are arranged in the same column.
Further, in an embodiment of the present invention, the first subpixel is equidistant from the second subpixel and the third subpixel, and the fourth subpixel is equidistant from the second subpixel and the third subpixel.
Further, in one embodiment of the present invention, in the first subpixel combination, the third subpixel combination, and the fifth subpixel combination, the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are arranged in the same form of subpixels;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in the same form.
Further, in one embodiment of the present invention, in the first subpixel combination, the third subpixel combination, and the fifth subpixel combination, the second subpixel and the third subpixel are the same primary color, and the first subpixel and the fourth subpixel are two primary colors;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the third sub-pixel and the fourth sub-pixel are of the same primary color, and the first sub-pixel and the second sub-pixel are of two primary colors.
The invention relates to a control method of a sub-pixel arrangement structure, which is realized by adopting any one of the sub-pixel arrangement structures, and is characterized by comprising the following steps:
reading and outputting the row number and column number of the sub-pixel data of the video source by adopting a row counter;
when the number of the lines read and output by the line counter is smaller than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in six registers, and when the six registers are valid and the video source sub-pixel data coming in each clock period, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started;
the six registers are a register 1, a register 2, a register 3, a register 7, a register 8 and a register 9 respectively;
when the number of the lines read and output by the line counter is larger than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in nine registers, and when the video source sub-pixel data coming in each clock period of the 2 n-th line comes, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started, wherein n is a positive integer;
the nine registers are register 1, register 2, register 3, register 4, register 5, register 6, register 7, register 8 and register 9, respectively.
Further, in one embodiment of the present invention, the video source subpixel data of each clock cycle of each line is written and read in FIFO1 and FIFO2 simultaneously, and stored in six registers, specifically:
when the number of lines read and output by the line counter is 1, video source sub-pixel data arriving in each clock period are written into the FIFO1;
when the number of the lines read and output by the line counter is 2, the video source sub-pixel data coming from each clock period is written into the FIFO2 and assigned to the register 9, the register 9 and the register 8 and the register 7 respectively carry out assignment operation, and meanwhile, the reading enabling of the FIFO1 is pulled high;
the video source sub-pixel data which come every clock period and are read out by the FIFO1 is assigned to the register 3, and the register 3 and the register 2 and the register 1 respectively carry out assignment operation.
Further, in one embodiment of the present invention, the video source sub-pixel data coming in each clock period of each line is written and read in FIFO1 and FIFO2 simultaneously, and stored in nine registers, specifically:
when the number of lines read and output by the line counter is larger than 2, video source sub-pixel data arriving in each clock period is written into the FIFO2 and assigned to the register 9, and the register 9 and the register 8 and the register 7 respectively carry out assignment operation;
the FIFO2 reads out video source sub-pixel data coming from each clock period of the previous line, and the video source sub-pixel data is written into the FIFO1 and is assigned to the register 6, and the register 6 and the register 5 and the register 4 respectively carry out assignment operation;
the FIFO1 reads out the video source sub-pixel data coming from each clock period of the two rows, and assigns the video source sub-pixel data to the register 3, and the register 3 and the register 2, and the register 2 and the register 1 respectively perform assignment operation.
Further, in one embodiment of the present invention, the operation of calculating the sub-pixel data of the video source coming every clock period is specifically:
when the number of the lines read and output by the line counter is 2, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the register of the line, the previous line and the two previous lines;
when the number of the lines read and output by the line counter is 2n, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the registers of the line, the upper line and the upper two lines;
when the number of the lines read and output by the line counter is larger than 2n and the number of the columns is larger than 2n, video source sub-pixel data which come in each clock period and are stored in the registers of the first column, the last two columns and the last three lines of the three columns are subjected to mean value processing, and n is a positive integer.
The invention solves the problems that the non-uniform quadrilateral arrangement mode can not provide uniform image display effect, the display effect is more general, the production efficiency is lower and the production cost is higher. The method has the specific beneficial effects that:
1. according to the sub-pixel arrangement structure, most of the existing quadrilateral arrangement modes are non-uniform, and the problem that uniform image display effect cannot be provided, the display effect is common, the production efficiency is low and the production cost is high is caused by the arrangement modes. The invention is square arrangement mode, the sub-pixels have equal intervals in the horizontal and vertical directions, and can provide uniformity and consistency of image display effect; the square arrangement mode enables details and lines of the image to be more uniform and accurate, and display is clearer under the condition of no distortion; the square-arranged sub-pixel structure is more regular and visual, is easy to realize in the design and manufacturing processes, can reduce the production complexity and cost, and provides better production efficiency;
2. according to the arrangement structure of the sub-pixels, the arrangement structure is in a positive direction, and due to the consistency of the sub-pixels in the horizontal and vertical directions, color mixing and gradual change are smoother, and color accuracy is higher;
3. according to the arrangement structure of the sub-pixels, four times of virtual pixel multiplexing can be realized, the resolution, the brightness and the contrast can be improved, the energy consumption can be reduced, and the display effect can be improved;
4. according to the control method of the sub-pixel arrangement structure, the plurality of FIFOs and the plurality of registers are used for storing the sub-pixel data of the video source, and the data storage mode can improve the data transmission and processing efficiency;
the sub-pixel arrangement structure can be applied to LED display screens of various types.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic view of a periodic subpixel combination arrangement according to an embodiment;
FIG. 2 is a diagram of a virtual pixel cell according to one embodiment;
FIG. 3 is a diagram of a plurality of sub-pixel combinations according to the second embodiment;
FIG. 4 is a video source subpixel data diagram according to embodiment four;
FIG. 5 is a diagram of a sub-pixel combination processing system according to a fifth embodiment;
FIG. 6 is a diagram of a sub-pixel combination processing system according to a sixth embodiment;
in the figure, A is a periodic subpixel combination, A1 is a first subpixel combination, A2 is a second subpixel combination, A3 is a third subpixel combination, A4 is a fourth subpixel combination, A5 is a fifth subpixel combination, A6 is a sixth subpixel combination, A1-1 is a first subpixel of the first subpixel combination, A1-2 is a second subpixel of the first subpixel combination, A1-3 is a third subpixel of the first subpixel combination, A1-4 is a fourth subpixel of the first subpixel combination, A2-1 is a first subpixel of the second subpixel combination, A2-2 is a second subpixel of the second subpixel combination, A2-3 is a fourth subpixel of the second subpixel combination, A3-1 is a first subpixel of the third subpixel combination, A3-2 is a second subpixel of the fourth subpixel combination, A3-3 is a fourth subpixel of the fourth subpixel combination, A3-4 is a fourth subpixel of the fourth subpixel combination, A2-4 is a fifth subpixel of the fourth subpixel combination, A2-4 is a fourth subpixel of the fourth subpixel combination, A4-5 is a fifth subpixel combination, A4-5 is a subpixel of the fourth subpixel combination, A-4 is a fifth subpixel combination, a6-3 is the third subpixel of the sixth subpixel combination, and A6-4 is the fourth subpixel of the sixth subpixel combination;
is a red primary color->Is a green primary color->Is the primary color blue.
Detailed Description
Various embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The embodiments described by referring to the drawings are exemplary and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the first embodiment, the arrangement structure of the sub-pixels is formed by arranging a plurality of periodic sub-pixel combinations in a matrix form;
the plurality of periodic sub-pixel combinations A are formed by arranging six sub-pixel combinations in a matrix form in the horizontal direction;
the six sub-pixel combinations are all composed of four adjacent sub-pixels;
the four adjacent sub-pixels form a square arrangement structure.
In this embodiment, as shown in fig. 1, periodic sub-pixel combinations a are sequentially arranged in the horizontal direction, each of the periodic sub-pixel combinations a includes six sub-pixel combinations, each of the sub-pixel combinations is composed of four adjacent sub-pixels, the four adjacent sub-pixels compose a square arrangement structure, and a plurality of virtual pixel units exist between the sub-pixel combinations and the sub-pixel combinations. That is, there is a case where a plurality of sub-pixels are multiplexed between virtual pixel units.
For example, as shown in fig. 2, two sub-pixels are shared between the virtual pixel unit 11-1 and the virtual pixel unit 12-1, two sub-pixels are shared between the virtual pixel unit 11-1 and the virtual pixel unit 21-1, two sub-pixels are shared between the virtual pixel unit 12-1 and the virtual pixel unit 22-1, and one sub-pixel is shared among the virtual pixel unit 11-1, the virtual pixel unit 12-1, the virtual pixel unit 21-1 and the virtual pixel unit 22-1, so that the sub-pixels in the arrangement structure can be multiplexed four times as much as the virtual pixel multiplexing structure.
The four-time virtual pixel multiplexing structure can improve resolution, brightness and contrast, reduce energy consumption and improve display effect.
In the second embodiment, the arrangement structure of one subpixel of the first embodiment is further defined, and the six subpixel combinations are a first subpixel combination A1, a second subpixel combination A2, a third subpixel combination A3, a fourth subpixel combination A4, a fifth subpixel combination A5, and a sixth subpixel combination A6;
the first sub-pixel combination A1, the second sub-pixel combination A2, the third sub-pixel combination A3, the fourth sub-pixel combination A4, the fifth sub-pixel combination A5 and the sixth sub-pixel combination A6 comprise four sub-pixels which are respectively a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel;
the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in a quadrilateral mode.
In this embodiment, the first subpixel and the second subpixel are arranged in the same row, and the third subpixel and the fourth subpixel are arranged in the same row;
the first sub-pixel and the third sub-pixel are arranged in the same column, and the second sub-pixel and the fourth sub-pixel are arranged in the same column.
In this embodiment, the first subpixel is equal to the second subpixel and the third subpixel in distance, and the fourth subpixel is equal to the second subpixel and the third subpixel in distance.
Most of the existing quadrilateral arrangement is in a non-uniform quadrilateral arrangement mode, and the arrangement mode can cause the problems that uniform image display effect cannot be provided, the display effect is common, the production efficiency is low, and the production cost is high.
In the present embodiment, as shown in fig. 3, the first sub-pixel combination A1, the second sub-pixel combination A2, the third sub-pixel combination A3, the fourth sub-pixel combination A4, the fifth sub-pixel combination A5, and the sixth sub-pixel combination A6 each include four sub-pixels;
namely, the first subpixel combination A1 comprises a first subpixel A1-1 of the first subpixel combination, a second subpixel A1-2 of the first subpixel combination, a third subpixel A1-3 of the first subpixel combination and a fourth subpixel A1-4 of the first subpixel combination;
the second sub-pixel combination A2 comprises a first sub-pixel A2-1 of the second sub-pixel combination, a second sub-pixel A2-2 of the second sub-pixel combination, a third sub-pixel A2-3 of the second sub-pixel combination and a fourth sub-pixel A2-4 of the second sub-pixel combination;
the third subpixel combination A3 includes a first subpixel A3-1 of the third subpixel combination, a second subpixel A3-2 of the third subpixel combination, a third subpixel A3-3 of the third subpixel combination, and a fourth subpixel A3-4 of the third subpixel combination;
the fourth sub-pixel combination A4 comprises a first sub-pixel A4-1 of the fourth sub-pixel combination, a second sub-pixel A4-2 of the fourth sub-pixel combination, a third sub-pixel A4-3 of the fourth sub-pixel combination and a fourth sub-pixel A4-4 of the fourth sub-pixel combination;
the fifth subpixel combination A5 comprises a first subpixel A5-1 of the fifth subpixel combination, a second subpixel A5-2 of the fifth subpixel combination, a third subpixel A5-3 of the fifth subpixel combination and a fourth subpixel A5-4 of the fifth subpixel combination;
the sixth subpixel combination A6 comprises a first subpixel A6-1 of the sixth subpixel combination, a second subpixel A6-2 of the sixth subpixel combination, a third subpixel A6-3 of the sixth subpixel combination and a fourth subpixel A6-4 of the sixth subpixel combination;
in the six sub-pixel combinations, four sub-pixels can form a regular quadrilateral arrangement mode;
namely, the distance from the first subpixel A1-1 of the first subpixel combination to the second subpixel A1-2 of the first subpixel combination, the distance from the first subpixel A1-1 of the first subpixel combination to the third subpixel A1-3 of the first subpixel combination, the distance from the fourth subpixel A1-4 of the first subpixel combination to the second subpixel A1-2 of the first subpixel combination, and the distance from the fourth subpixel A1-4 of the first subpixel combination to the third subpixel A1-3 of the first subpixel combination are all equal;
in the vertical direction, a first subpixel A1-1 of the first subpixel combination is arranged in the same column as a third subpixel A1-3 of the first subpixel combination, and a second subpixel A1-2 of the first subpixel combination is arranged in the same column as a fourth subpixel A1-4 of the first subpixel combination;
in the horizontal direction, a first subpixel A1-1 of the first subpixel combination is arranged in the same row as a second subpixel A1-2 of the first subpixel combination, and a third subpixel A1-3 of the first subpixel combination is arranged in the same row as a fourth subpixel A1-4 of the first subpixel combination;
the arrangement of the other sub-pixel combinations is the same as that of the first sub-pixel combination.
Because the arrangement structure is in a square arrangement mode, the sub-pixels have equal intervals in the horizontal and vertical directions, and the uniformity and consistency of the image display effect can be provided. The square arrangement mode enables details and lines of the image to be more uniform and accurate, and display is clearer under the condition of no distortion. The sub-pixel structure of the square arrangement mode is more regular and visual, is easy to realize in the design and manufacturing process, can reduce the production complexity and cost, and provides better production efficiency. And the consistency of the sub-pixels in the square arrangement mode in the horizontal and vertical directions is smoother in color mixing and gradual change, and the color accuracy is higher.
In the third embodiment, the arrangement structure of one subpixel of the second embodiment is further defined, and in the first subpixel combination, the third subpixel combination and the fifth subpixel combination, the first subpixel, the second subpixel, the third subpixel and the fourth subpixel are arranged in the same form of subpixels;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in the same form.
In this embodiment, in the first subpixel combination, the third subpixel combination, and the fifth subpixel combination, the second subpixel and the third subpixel are the same primary color, and the first subpixel and the fourth subpixel are two primary colors;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the third sub-pixel and the fourth sub-pixel are of the same primary color, and the first sub-pixel and the second sub-pixel are of two primary colors.
In this embodiment, as shown in fig. 3, the first sub-pixel group A1, the third sub-pixel group A2 and the fifth sub-pixel group A3 are arranged in the same manner;
namely, a first subpixel A1-1 of a first subpixel combination and a fourth subpixel A1-4 of the first subpixel combination are two primary colors, the first subpixel A1-1 of the first subpixel combination is a red primary color, the fourth subpixel A1-4 of the first subpixel combination is a blue primary color, the second subpixel A1-2 of the first subpixel combination and the third subpixel A1-3 of the first subpixel combination are the same primary color, and the second subpixel A1-2 of the first subpixel combination and the third subpixel A1-3 of the first subpixel combination are both green primary colors;
the first subpixel A3-1 of the third subpixel combination and the fourth subpixel A3-4 of the third subpixel combination are two primary colors, the first subpixel A3-1 of the third subpixel combination is a green primary color, the fourth subpixel A3-4 of the third subpixel combination is a red primary color, the second subpixel A3-2 of the third subpixel combination and the third subpixel A3-3 of the third subpixel combination are the same primary color, and the second subpixel A3-2 of the third subpixel combination and the third subpixel A3-3 of the third subpixel combination are both blue primary colors;
the first sub-pixel A5-1 of the fifth sub-pixel combination and the fourth sub-pixel A5-4 of the fifth sub-pixel combination are two primary colors, the first sub-pixel A5-1 of the fifth sub-pixel combination is a blue primary color, the fourth sub-pixel A5-4 of the fifth sub-pixel combination is a green primary color, the second sub-pixel A5-2 of the fifth sub-pixel combination and the third sub-pixel A5-3 of the fifth sub-pixel combination are the same primary color, and the second sub-pixel A5-2 of the fifth sub-pixel combination and the third sub-pixel A5-3 of the fifth sub-pixel combination are both red primary colors;
the arrangement form of the second sub-pixel combination A2, the fourth sub-pixel combination A4 and the sixth sub-pixel combination A6 is the same;
namely, a first sub-pixel A2-1 of a second sub-pixel combination and a second sub-pixel A2-2 of the second sub-pixel combination are two primary colors, the first sub-pixel A2-1 of the second sub-pixel combination is a blue primary color, the second sub-pixel A2-2 of the second sub-pixel combination is a green primary color, a third sub-pixel A2-3 of the second sub-pixel combination and a fourth sub-pixel A2-4 of the second sub-pixel combination are the same primary color, and the third sub-pixel A2-3 of the second sub-pixel combination and the fourth sub-pixel A2-4 of the second sub-pixel combination are both red primary colors;
the first sub-pixel A4-1 of the fourth sub-pixel combination and the second sub-pixel A4-2 of the fourth sub-pixel combination are two primary colors, the first sub-pixel A4-1 of the fourth sub-pixel combination is a red primary color, the second sub-pixel A4-2 of the fourth sub-pixel combination is a blue primary color, the third sub-pixel A4-3 of the fourth sub-pixel combination and the fourth sub-pixel A4-4 of the fourth sub-pixel combination are the same primary color, and the third sub-pixel A4-3 of the fourth sub-pixel combination and the fourth sub-pixel A4-4 of the fourth sub-pixel combination are both green primary colors;
the first sub-pixel A6-1 of the sixth sub-pixel combination and the second sub-pixel A6-2 of the sixth sub-pixel combination are two primary colors, the first sub-pixel A6-1 of the sixth sub-pixel combination is a green primary color, the second sub-pixel A6-2 of the sixth sub-pixel combination is a red primary color, the third sub-pixel A6-3 of the sixth sub-pixel combination and the fourth sub-pixel A6-4 of the sixth sub-pixel combination are the same primary color, and the third sub-pixel A6-3 of the sixth sub-pixel combination and the fourth sub-pixel A6-4 of the sixth sub-pixel combination are both blue primary colors.
An embodiment four, a control method for an arrangement structure of sub-pixels according to the embodiment, where the control method is implemented by using an arrangement structure of sub-pixels according to any one of the embodiments one to three, specifically:
reading and outputting the row number and column number of the sub-pixel data of the video source by adopting a row counter;
when the number of the lines read and output by the line counter is smaller than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in six registers, and when the six registers are valid and the video source sub-pixel data coming in each clock period, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started;
the six registers are a register 1, a register 2, a register 3, a register 7, a register 8 and a register 9 respectively;
when the number of the lines read and output by the line counter is larger than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in nine registers, and when the video source sub-pixel data coming in each clock period of the 2 n-th line comes, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started, wherein n is a positive integer;
the nine registers are register 1, register 2, register 3, register 4, register 5, register 6, register 7, register 8 and register 9, respectively.
In this embodiment, the video source sub-pixel data of each row is output in a row form, and the row counter is used to read the row number and column number of the output video source sub-pixel data, where the sub-pixel data of each two rows are one row of video source sub-pixel data, and sub-pixel data information is contained in each source video sub-pixel data.
As shown in fig. 4, video source subpixel data 11, video source subpixel data 12, video source subpixel data 13, video source subpixel data 14, … are video source subpixel data output in the first line;
video source subpixel data 21, video source subpixel data 22, video source subpixel data 23, video source subpixel data 24 … are video source subpixel data output by the second line;
the first row of sub-pixel data and the second row of sub-pixel data are one row of video source sub-pixel data, in one row of video source sub-pixel data, four adjacent sub-pixel data are one sub-pixel combination data, and the whole sub-pixel combination data are combined together to be output in a multiplication process.
The video source sub-pixel data of other lines are output in the same mode, and data storage is carried out in a plurality of FIFOs and a plurality of registers;
for the video source subpixel data of the first line, two FIFOs (first-in first-out memories) and six registers are required;
the two FIFOs are FIFO1 and FIFO2, respectively;
the six registers are register 1, register 2, register 3, register 7, register 8 and register 9, respectively.
The video source sub-pixel data of the second line and the video source sub-pixel data of the other lines meet the requirement conditions, so that two FIFOs and nine registers are needed for the video source sub-pixel data of the second line and the video source sub-pixel data after the second line;
the two FIFOs are FIFO1 and FIFO2, respectively;
the nine registers are register 1, register 2, register 3, register 4, register 5, register 6, register 7, register 8 and register 9, respectively.
The use of FIFOs and registers to process video source sub-pixel data may lead to higher data processing efficiency, better data accuracy, signal processing and calibration capabilities, and higher flexibility and programmability. These advantages may improve image quality, display efficiency, and image processing capabilities, enabling better processing of video source subpixel data in image processing and display applications.
In a fifth embodiment, the present embodiment is further defined on the control method for an arrangement structure of sub-pixels in the fourth embodiment, where the video source sub-pixel data of each clock cycle of each row is written and read in the FIFO1 and the FIFO2 respectively at the same time, and stored in six registers, specifically:
when the number of lines read and output by the line counter is 1, video source sub-pixel data arriving in each clock period are written into the FIFO1;
when the number of the lines read and output by the line counter is 2, the video source sub-pixel data coming from each clock period is written into the FIFO2 and assigned to the register 9, the register 9 and the register 8 and the register 7 respectively carry out assignment operation, and meanwhile, the reading enabling of the FIFO1 is pulled high;
the video source sub-pixel data which come every clock period and are read out by the FIFO1 is assigned to the register 3, and the register 3 and the register 2 and the register 1 respectively carry out assignment operation.
In this embodiment, as shown in fig. 5, when the number of lines read and output by the line counter is 1, the video source sub-pixel data coming every clock cycle is written into the FIFO1;
when the number of lines read and output by the line counter is 2, video source sub-pixel data arriving in each clock period is written into the FIFO2 and assigned to the register 9, video source sub-pixel data of the last clock period stored in the register 9 is assigned to the register 8, video source sub-pixel data of the last clock period stored in the register 8 is assigned to the register 7, and meanwhile, the reading enabling of the FIFO1 and the FIFO2 is respectively pulled up;
the video source sub-pixel data coming from each clock cycle read out by the FIFO1 is written into the register 3, the video source sub-pixel data of the last clock cycle stored in the register 3 is assigned to the register 2, and the video source sub-pixel data of the last clock cycle stored in the register 2 is assigned to the register 1.
In a sixth embodiment, the present embodiment is further defined on a control method for an arrangement structure of sub-pixels in the fourth embodiment, where the video source sub-pixel data coming in each clock cycle of each row is written and read in the FIFO1 and the FIFO2 respectively at the same time, and stored in nine registers, specifically:
when the number of lines read and output by the line counter is larger than 2, video source sub-pixel data arriving in each clock period is written into the FIFO2 and assigned to the register 9, and the register 9 and the register 8 and the register 7 respectively carry out assignment operation;
the FIFO2 reads out video source sub-pixel data coming from each clock period of the previous line, and the video source sub-pixel data is written into the FIFO1 and is assigned to the register 6, and the register 6 and the register 5 and the register 4 respectively carry out assignment operation;
the FIFO1 reads out the video source sub-pixel data coming from each clock period of the two rows, and assigns the video source sub-pixel data to the register 3, and the register 3 and the register 2, and the register 2 and the register 1 respectively perform assignment operation.
In this embodiment, as shown in fig. 6, when the line counter reads the output line number 4, the video source sub-pixel data coming in each clock cycle is written into the FIFO2 and assigned to the register 9, the video source sub-pixel data stored in the register 9 and in the last clock cycle is assigned to the register 8, and the video source sub-pixel data stored in the register 8 and in the last clock cycle is assigned to the register 7;
the FIFO2 reads out video source sub-pixel data coming from each clock period of the third row, and the video source sub-pixel data is written into the FIFO1 and is assigned to the register 6, meanwhile, the video source sub-pixel data of the last clock period stored in the register 6 is assigned to the register 5, and the video source sub-pixel data of the last clock period stored in the register 5 is assigned to the register 4;
the FIFO1 reads out the video source sub-pixel data coming in each clock cycle of the second row, and assigns the video source sub-pixel data of the last clock cycle stored in the register 3 to the register 2, and assigns the video source sub-pixel data of the last clock cycle stored in the register 2 to the register 1.
The processing modes of the video source sub-pixel data of the other rows meet the conditions.
In a sixth embodiment, the present embodiment is further defined to a control method for an arrangement structure of sub-pixels according to the fourth embodiment, where the operation of calculating sub-pixel data of a video source coming in each clock cycle specifically includes:
when the number of the lines read and output by the line counter is 2, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the register of the line, the previous line and the two previous lines;
when the number of the lines read and output by the line counter is 2n, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the registers of the line, the upper line and the upper two lines;
when the number of the lines read and output by the line counter is larger than 2n and the number of the columns is larger than 2n, video source sub-pixel data which come in each clock period and are stored in the registers of the first column, the last two columns and the last three lines of the three columns are subjected to mean value processing, and n is a positive integer.
In this embodiment, for the video source sub-pixel data of the first two rows, valid video source sub-pixel data is in each of the register 1, the register 2, the register 3, the register 7, the register 8, and the register 9 from the third video source sub-pixel clock period of the second row, and the calculation and assignment operation is performed on the video source sub-pixel data coming every clock period from this time.
For the first row of sub-pixel combination data, the first sub-pixel combination data requires input of video source sub-pixel data of a first column of the first row, video source sub-pixel data of a second column of the first row, video source sub-pixel data of the first column of the second row, and video source sub-pixel data of the second column of the second row;
video source subpixel data of a second column of the first row, video source subpixel data of a third column of the first row, video source subpixel data of a fourth column of the first row, video source subpixel data of a second column of the second row, video source subpixel data of a third column of the second row, and video source subpixel data of a fourth column of the second row, which are required for the second subpixel combination data;
the remaining sub-pixel combination data of the first row meets the above requirement.
For the sub-pixel combination data of the second row, the first sub-pixel combination data requires input of video source sub-pixel data of the first column of the second row, video source sub-pixel data of the second column of the second row, video source sub-pixel data of the first column of the third row, video source sub-pixel data of the second column of the third row, video source sub-pixel data of the first column of the fourth row, and video source sub-pixel data of the second column of the fourth row;
the second subpixel combination data requires input of video source subpixel data of a second column of the second row, video source subpixel data of a third column of the second row, video source subpixel data of a fourth column of the second row, video source subpixel data of a second column of the third row, video source subpixel data of a third column of the third row, video source subpixel data of a fourth column of the third row, video source subpixel data of a second column of the fourth row, video source subpixel data of a third column of the fourth row, and video source subpixel data of a fourth column of the fourth row.
For example, the first blue subpixel of the second row outputting the subpixel combination data requires the values of the blue subpixels in the registers 9, 8, 6, 5, 3 and 2, so that the values of the blue subpixels in these registers are taken out for averaging operation, the obtained data is assigned to the blue subpixels of the output data, and the remaining subpixel data calculation modes are similar.
The above describes in detail a subpixel arrangement structure and a control method thereof, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (5)
1. An arrangement of sub-pixels, wherein the arrangement is formed by a plurality of periodic sub-pixel combinations arranged in a matrix;
the plurality of periodic sub-pixel combinations (A) are formed by arranging six sub-pixel combinations in a matrix form in the horizontal direction;
the six sub-pixel combinations are all composed of four adjacent sub-pixels;
the four adjacent sub-pixels form a square arrangement structure;
the six sub-pixel combinations are respectively a first sub-pixel combination (A1), a second sub-pixel combination (A2), a third sub-pixel combination (A3), a fourth sub-pixel combination (A4), a fifth sub-pixel combination (A5) and a sixth sub-pixel combination (A6);
the first sub-pixel combination (A1), the second sub-pixel combination (A2), the third sub-pixel combination (A3), the fourth sub-pixel combination (A4), the fifth sub-pixel combination (A5) and the sixth sub-pixel combination (A6) comprise four sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel;
the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in a quadrilateral manner;
the first sub-pixel and the second sub-pixel are arranged in the same row, and the third sub-pixel and the fourth sub-pixel are arranged in the same row;
the first sub-pixel and the third sub-pixel are arranged in the same column, and the second sub-pixel and the fourth sub-pixel are arranged in the same column;
the first sub-pixel is respectively equal to the second sub-pixel and the third sub-pixel in distance, and the fourth sub-pixel is respectively equal to the second sub-pixel and the third sub-pixel in distance;
in the first subpixel combination, the third subpixel combination and the fifth subpixel combination, the first subpixel, the second subpixel, the third subpixel and the fourth subpixel are arranged in the same form;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged in the same form of sub-pixels;
in the first subpixel combination, the third subpixel combination and the fifth subpixel combination, the second subpixel and the third subpixel are of the same primary color, and the first subpixel and the fourth subpixel are of two primary colors;
in the second sub-pixel combination, the fourth sub-pixel combination and the sixth sub-pixel combination, the third sub-pixel and the fourth sub-pixel are of the same primary color, and the first sub-pixel and the second sub-pixel are of two primary colors.
2. A method for controlling an arrangement of sub-pixels, the method being implemented by using the arrangement of sub-pixels according to claim 1, characterized by comprising:
reading and outputting the row number and column number of the sub-pixel data of the video source by adopting a row counter;
when the number of the lines read and output by the line counter is smaller than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in six registers, and when the six registers are valid and the video source sub-pixel data coming in each clock period, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started;
the six registers are a register 1, a register 2, a register 3, a register 7, a register 8 and a register 9 respectively;
when the number of the lines read and output by the line counter is larger than 2, the video source sub-pixel data coming in each clock period of each line are written in and read out in the FIFO1 and the FIFO2 respectively and stored in nine registers, and when the video source sub-pixel data coming in each clock period of the 2 n-th line comes, the operation of calculating and assigning the video source sub-pixel data coming in each clock period is started, wherein n is a positive integer;
the nine registers are register 1, register 2, register 3, register 4, register 5, register 6, register 7, register 8 and register 9, respectively.
3. The method for controlling the arrangement structure of the sub-pixels according to claim 2, wherein the video source sub-pixel data of each clock cycle of each row is written and read in FIFO1 and FIFO2 respectively at the same time, and stored in six registers, specifically:
when the number of lines read and output by the line counter is 1, video source sub-pixel data arriving in each clock period are written into the FIFO1;
when the number of the lines read and output by the line counter is 2, the video source sub-pixel data coming from each clock period is written into the FIFO2 and assigned to the register 9, the register 9 and the register 8 and the register 7 respectively carry out assignment operation, and meanwhile, the reading enabling of the FIFO1 is pulled high;
the video source sub-pixel data which come every clock period and are read out by the FIFO1 is assigned to the register 3, and the register 3 and the register 2 and the register 1 respectively carry out assignment operation.
4. The method for controlling the arrangement structure of the sub-pixels according to claim 2, wherein the video source sub-pixel data coming from each clock cycle of each row is written and read in FIFO1 and FIFO2 respectively at the same time, and stored in nine registers, specifically:
when the number of lines read and output by the line counter is larger than 2, video source sub-pixel data arriving in each clock period is written into the FIFO2 and assigned to the register 9, and the register 9 and the register 8 and the register 7 respectively carry out assignment operation;
the FIFO2 reads out video source sub-pixel data coming from each clock period of the previous line, and the video source sub-pixel data is written into the FIFO1 and is assigned to the register 6, and the register 6 and the register 5 and the register 4 respectively carry out assignment operation;
the FIFO1 reads out the video source sub-pixel data coming from each clock period of the two rows, and assigns the video source sub-pixel data to the register 3, and the register 3 and the register 2, and the register 2 and the register 1 respectively perform assignment operation.
5. The method for controlling the arrangement structure of the sub-pixels according to claim 2, wherein the operation of calculating the sub-pixel data of the video source coming in each clock cycle is specifically:
when the number of the lines read and output by the line counter is 2, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the register of the line, the previous line and the two previous lines;
when the number of the lines read and output by the line counter is 2n, carrying out average processing on video source sub-pixel data which come in each clock period and are stored in the registers of the line, the upper line and the upper two lines;
when the number of the lines read and output by the line counter is larger than 2n and the number of the columns is larger than 2n, video source sub-pixel data which come in each clock period and are stored in the registers of the first column, the last two columns and the last three lines of the three columns are subjected to mean value processing, and n is a positive integer.
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