[go: up one dir, main page]

CN116845158A - LED epitaxial wafer, preparation method thereof and LED - Google Patents

LED epitaxial wafer, preparation method thereof and LED Download PDF

Info

Publication number
CN116845158A
CN116845158A CN202311127603.3A CN202311127603A CN116845158A CN 116845158 A CN116845158 A CN 116845158A CN 202311127603 A CN202311127603 A CN 202311127603A CN 116845158 A CN116845158 A CN 116845158A
Authority
CN
China
Prior art keywords
layer
source
emitting diode
ingan
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311127603.3A
Other languages
Chinese (zh)
Inventor
张彩霞
印从飞
刘春杨
胡加辉
金从龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202311127603.3A priority Critical patent/CN116845158A/en
Publication of CN116845158A publication Critical patent/CN116845158A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/815Bodies having stress relaxation structures, e.g. buffer layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/822Materials of the light-emitting regions
    • H10H20/824Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN

Landscapes

  • Led Devices (AREA)

Abstract

本发明公开了一种发光二极管外延片及其制备方法、LED,所述发光二极管外延片包括衬底,所述衬底上依次设有形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。本发明提供的发光二极管外延片能够提高发光二极管的发光波长均匀性。

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof, and an LED. The light-emitting diode epitaxial wafer includes a substrate. The substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, and a uniform wavelength layer. property control layer, multiple quantum well layer, electron blocking layer, and P-type semiconductor layer; the wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer, and the compressive stress providing layer includes a first AlN layer deposited in sequence , AlGaN layer, and second AlN layer. The tensile stress providing layer includes a first InGaN layer, an InN layer, and a second InGaN layer deposited in sequence. The light-emitting diode epitaxial wafer provided by the invention can improve the uniformity of the light-emitting wavelength of the light-emitting diode.

Description

发光二极管外延片及其制备方法、LEDLight-emitting diode epitaxial wafer and preparation method thereof, LED

技术领域Technical field

本发明涉及光电技术领域,尤其涉及一种发光二极管外延片及其制备方法、LED。The present invention relates to the field of optoelectronic technology, and in particular to a light-emitting diode epitaxial wafer and a preparation method thereof, and an LED.

背景技术Background technique

目前,GaN基发光二极管已经大量应用于固态照明领域以及显示领域,吸引着越来越多的人关注。GaN基发光二极管已经实现工业化生产、在背光源、照明、景观灯等方面都有应用。At present, GaN-based light-emitting diodes have been widely used in the field of solid-state lighting and display, attracting more and more people's attention. GaN-based light-emitting diodes have achieved industrial production and are used in backlights, lighting, landscape lights, etc.

外延结构对发光二极管的光电性能具有很大影响。传统的发光二极管外延片包括衬底、以及在所述衬底上依次生长的形核层、本征GaN层、N型半导体层、多量子阱层、电子阻挡层、P型半导体层;多量子阱层作为有源区是发光二极管的核心结构,现有多量子阱层为InGaN势阱层和GaN量子垒层周期性层叠组成,传统结构的多量子阱层具有以下问题:The epitaxial structure has a great influence on the photoelectric performance of light-emitting diodes. A traditional light-emitting diode epitaxial wafer includes a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer, and a P-type semiconductor layer grown sequentially on the substrate; As the active area, the well layer is the core structure of the light-emitting diode. The existing multi-quantum well layer is composed of an InGaN potential well layer and a GaN quantum barrier layer periodically stacked. The traditional multi-quantum well layer has the following problems:

目前,国内MOCVD使用蓝宝石图形化衬底生长LED外延片都会遇到因切换不同种蓝宝石图形衬底而导致品质上存在波动,而其中由于衬底图形深度、间距等规格上的差异导致产品生长过程中翘曲变化而影响波长分布均匀性,使用原有条件生长出来的产品容易出现波长呈同心圆偏长或偏短的现象,导致波长分布不集中,制作出的芯片波长分布散、落Bin率低。现有技术解决方法主要是针对形核层的生长参数修改进行应力调节,显著缺点是:距离发光有源区即多量子阱层较远,产出波长均匀性不易控制。并且多量子阱层InGaN势阱层由于In偏析问题,影响发光效率。At present, domestic MOCVD using sapphire patterned substrates to grow LED epitaxial wafers will encounter quality fluctuations due to switching between different types of sapphire patterned substrates. Among them, due to differences in substrate pattern depth, spacing and other specifications, the product growth process Medium warpage changes affect the uniformity of wavelength distribution. Products grown using original conditions are prone to concentric circles with longer or shorter wavelengths, resulting in non-concentrated wavelength distribution. The produced chips have scattered wavelength distribution and low bin rate. Low. The existing technical solution is mainly to adjust the stress by modifying the growth parameters of the nucleation layer. The significant disadvantage is that it is far away from the light-emitting active area, that is, the multi-quantum well layer, and the uniformity of the output wavelength is difficult to control. Moreover, the multi-quantum well layer InGaN potential well layer affects the luminous efficiency due to In segregation problem.

发明内容Contents of the invention

本发明所要解决的技术问题在于,提供一种发光二极管外延片,其能够提高发光二极管的发光波长均匀性。The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer that can improve the uniformity of the light-emitting wavelength of the light-emitting diode.

本发明所要解决的技术问题还在于,提供一种发光二极管外延片的制备方法,其工艺简单,能够稳定制得发光效率良好的发光二极管外延片。The technical problem to be solved by the present invention is to provide a method for preparing a light-emitting diode epitaxial wafer, which has a simple process and can stably produce a light-emitting diode epitaxial wafer with good luminous efficiency.

为了解决上述技术问题,本发明提供了一种发光二极管外延片,包括衬底,所述衬底上依次设有形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;In order to solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, which includes a substrate. The substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity control layer, and a multi-quantum semiconductor layer. Well layer, electron blocking layer, P-type semiconductor layer;

所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited sequentially. The tensile stress providing layer includes a sequentially deposited The first InGaN layer, the InN layer, and the second InGaN layer.

在一种实施方式中,所述压应力提供层的厚度为10nm~100nm;In one embodiment, the thickness of the compressive stress providing layer is 10nm~100nm;

所述张应力提供层的厚度为10nm~100nm。The thickness of the tensile stress providing layer is 10nm~100nm.

在一种实施方式中,所述第一AlN层或第二AlN层的厚度为5nm~20nm;In one embodiment, the thickness of the first AlN layer or the second AlN layer is 5nm~20nm;

所述AlGaN层的厚度为10nm~80nm。The thickness of the AlGaN layer is 10nm~80nm.

在一种实施方式中,所述AlGaN层的Al组分为0.2~0.7。In one implementation, the Al composition of the AlGaN layer is 0.2 to 0.7.

在一种实施方式中,所述第一InGaN层或第二InGaN层的厚度为10nm~50nm;In one implementation, the thickness of the first InGaN layer or the second InGaN layer is 10nm~50nm;

所述InN层的厚度为5nm~20nm。The thickness of the InN layer is 5nm~20nm.

在一种实施方式中,所述第一InGaN层或第二InGaN层的In组分为0.1~0.5。In one implementation, the In composition of the first InGaN layer or the second InGaN layer is 0.1 to 0.5.

为了解决上述问题,本发明还提供了一种发光二极管外延片的制备方法,包括以下步骤:In order to solve the above problems, the present invention also provides a method for preparing a light-emitting diode epitaxial wafer, which includes the following steps:

S1、准备衬底;S1. Prepare the substrate;

S2、在所述衬底上依次沉积形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;S2. Deposit sequentially on the substrate a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity control layer, a multi-quantum well layer, an electron blocking layer, and a P-type semiconductor layer;

所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited sequentially. The tensile stress providing layer includes a sequentially deposited The first InGaN layer, the InN layer, and the second InGaN layer.

在一种实施方式中,所述压应力提供层采用下述方法制得:In one embodiment, the compressive stress providing layer is made by the following method:

将反应室温度控制在1000℃~1100℃,反应室压力控制在100torr~500torr,通入Al源、N源,完成第一AlN层的沉积,再通入Al源、Ga源、N源,完成所述AlGaN层的沉积,然后通入Al源、N源,完成所述第二AlN层的沉积。Control the temperature of the reaction chamber at 1000℃~1100℃ and the pressure of the reaction chamber at 100torr~500torr. Pass in the Al source and N source to complete the deposition of the first AlN layer. Then feed in the Al source, Ga source and N source to complete. After the deposition of the AlGaN layer, the Al source and the N source are introduced to complete the deposition of the second AlN layer.

在一种实施方式中,所述张应力提供层采用下述方法制得:In one embodiment, the tensile stress providing layer is made by the following method:

将反应室温度控制在800℃~900℃,反应室压力控制在100torr~500torr,通入Ga源、In源、N源,完成所述第一InGaN层的沉积,再通入In源、N源,完成所述InN层的沉积,然后通入Ga源、In源、N源,完成所述第二InGaN层的沉积。The temperature of the reaction chamber is controlled at 800°C~900°C, and the pressure of the reaction chamber is controlled at 100torr~500torr. The Ga source, In source, and N source are introduced to complete the deposition of the first InGaN layer, and then the In source and N source are introduced. , to complete the deposition of the InN layer, and then pass in the Ga source, In source, and N source to complete the deposition of the second InGaN layer.

相应地,本发明还提供了一种LED,所述LED包括上述的发光二极管外延片。Correspondingly, the present invention also provides an LED, which includes the above-mentioned light-emitting diode epitaxial wafer.

实施本发明,具有如下有益效果:Implementing the present invention has the following beneficial effects:

本发明提供的发光二极管外延片,其在N型半导体层和多量子阱层之间插入特定结构的波长均匀性调控层,所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。In the light-emitting diode epitaxial wafer provided by the invention, a wavelength uniformity control layer of a specific structure is inserted between the N-type semiconductor layer and the multi-quantum well layer. The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited in sequence, and the tensile stress providing layer includes a first InGaN layer, an InN layer, and a second InGaN layer deposited in sequence.

所述压应力提供层中,由于Al原子较小,AlN和AlGaN材料晶格常数小,可以对外延层提供压应力。所述压应力提供层为AlN/AlGaN/AlN三明治结构,高温下的AlN层有很高的致密度,但是连续高温生长厚度过高的AlN层会容易产生裂纹,所以中间AlGaN材料作为缓冲。AlN/AlGaN/AlN三明治结构对底层缺陷有很好的阻挡作用,使得位错缺陷在这一层发生扭曲和湮灭,避免了缺陷累积至多量子阱层,影响In组分的均匀分布。In the compressive stress providing layer, since Al atoms are small and AlN and AlGaN materials have small lattice constants, compressive stress can be provided to the epitaxial layer. The compressive stress providing layer is an AlN/AlGaN/AlN sandwich structure. The AlN layer at high temperatures has a high density. However, continuous high-temperature growth of an AlN layer that is too thick will easily cause cracks, so the middle AlGaN material serves as a buffer. The AlN/AlGaN/AlN sandwich structure has a good blocking effect on underlying defects, causing dislocation defects to be distorted and annihilated in this layer, preventing defects from accumulating into the multi-quantum well layer and affecting the uniform distribution of the In component.

所述张应力提供层中,由于In原子大,InN和InGaN材料晶格质量大,可以提供张应力。所述张应力提供层为InGaN/InN/InGaN三明治结构,其不仅可以缓解InN材料稳定性差的问题,而且其和多量子阱层中势阱层的InGaN材料晶格失配小,可以减少多量子阱层所受的压应力,避免压应力过大导致In组分分布不均匀,从而避免加重In偏析现象。In the tensile stress providing layer, due to the large In atoms and the large lattice quality of InN and InGaN materials, tensile stress can be provided. The tensile stress providing layer is an InGaN/InN/InGaN sandwich structure, which can not only alleviate the problem of poor stability of InN materials, but also has a small lattice mismatch with the InGaN material of the potential well layer in the multi-quantum well layer, which can reduce the number of multi-quantum wells. The compressive stress on the well layer prevents uneven distribution of In components caused by excessive compressive stress, thereby avoiding aggravation of In segregation.

综上,本发明提出的波长均匀性调控层可以在多量子阱层生长前,调整翘曲,更加精准的控制多量子阱层生长时的翘曲,增加发光波长的均匀性。同时,减少了多量子阱层的缺陷,减少了多量子阱层生长时的应力,增加了In组分分布的均匀性,增加发光波长的均匀性。同时由于多量子阱层应力的减少,缺陷的减少,可以增加电子空穴的复合效率,增加发光二极管的发光效率。In summary, the wavelength uniformity control layer proposed by the present invention can adjust the warpage before the growth of the multi-quantum well layer, more accurately control the warpage during the growth of the multi-quantum well layer, and increase the uniformity of the luminescence wavelength. At the same time, the defects of the multi-quantum well layer are reduced, the stress during the growth of the multi-quantum well layer is reduced, the uniformity of the In component distribution is increased, and the uniformity of the luminescence wavelength is increased. At the same time, due to the reduction of stress and defects in the multi-quantum well layer, the recombination efficiency of electrons and holes can be increased, and the luminous efficiency of the light-emitting diode can be increased.

附图说明Description of the drawings

图1为本发明提供的发光二极管外延片的结构示意图;Figure 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by the present invention;

图2为本发明提供的发光二极管外延片的制备方法的流程图;Figure 2 is a flow chart of a method for preparing a light-emitting diode epitaxial wafer provided by the present invention;

图3为本发明提供的发光二极管外延片的制备方法的步骤S2的流程图。FIG. 3 is a flow chart of step S2 of the method for preparing a light-emitting diode epitaxial wafer provided by the present invention.

具体实施方式Detailed ways

为使本发明的目的、技术方案和优点更加清楚,下面对本发明作进一步地详细描述。In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail below.

除非另外说明或存在矛盾之处,本文中使用的术语或短语具有以下含义:Unless otherwise stated or contradictory, the terms or phrases used in this article have the following meanings:

本发明中,“优选”仅为描述效果更好的实施方式或实施例,应当理解,并不构成对本发明保护范围的限制。In the present invention, "preferred" is only used to describe an embodiment or example with better effect. It should be understood that it does not constitute a limitation on the scope of protection of the present invention.

本发明中,以开放式描述的技术特征中,包括所列举特征组成的封闭式技术方案,也包括包含所列举特征的开放式技术方案。In the present invention, the technical features described in open terms include closed technical solutions composed of the listed features, and also include open technical solutions including the listed features.

本发明中,涉及到数值区间,如无特别说明,则包括数值区间的两个端点。In the present invention, when it comes to a numerical interval, unless otherwise specified, it includes the two endpoints of the numerical interval.

为解决上述问题,本发明提供了一种发光二极管外延片,如图1所示,包括衬底1,所述衬底1上依次设有形核层2、本征GaN层3、N型半导体层4、波长均匀性调控层5、多量子阱层6、电子阻挡层7、P型半导体层8;In order to solve the above problems, the present invention provides a light-emitting diode epitaxial wafer, as shown in Figure 1, including a substrate 1, which is sequentially provided with a nucleation layer 2, an intrinsic GaN layer 3, and an N-type semiconductor layer. 4. Wavelength uniformity control layer 5, multiple quantum well layer 6, electron blocking layer 7, and P-type semiconductor layer 8;

所述波长均匀性调控层5包括压应力提供层51和张应力提供层52,所述压应力提供层51包括依次沉积的第一AlN层511、AlGaN层512、第二AlN层513,所述张应力提供层包括依次沉积的第一InGaN层521、InN层522、第二InGaN层523。The wavelength uniformity control layer 5 includes a compressive stress providing layer 51 and a tensile stress providing layer 52. The compressive stress providing layer 51 includes a first AlN layer 511, an AlGaN layer 512, and a second AlN layer 513 deposited in sequence. The tensile stress providing layer includes a first InGaN layer 521, an InN layer 522, and a second InGaN layer 523 deposited in sequence.

所述压应力提供层51和张应力提供层52的具体结构如下:The specific structures of the compressive stress providing layer 51 and the tensile stress providing layer 52 are as follows:

在一种实施方式中,所述压应力提供层51的厚度为10nm~100nm;示例性的压应力提供层51的厚度为20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm,但不限于此;所述第一AlN层511或第二AlN层513的厚度为5nm~20nm;示例性的所述第一AlN层511或第二AlN层513的厚度为7nm、9nm、11nm、13nm、15nm、17nm、19nm,但不限于此;所述AlGaN层512的厚度为10nm~80nm;示例性的AlGaN层512的厚度为20nm、30nm、40nm、50nm、60nm、70nm,但不限于此;所述AlGaN层512的Al组分为0.2~0.7;示例性的AlGaN层512的Al组分为0.3、0.4、0.5、0.6,但不限于此。所述压应力提供层中,由于Al原子较小,AlN和AlGaN材料晶格常数小,可以对外延层提供压应力。所述压应力提供层为AlN/AlGaN/AlN三明治结构,高温下的AlN层有很高的致密度,但是连续高温生长厚度过高的AlN层会容易产生裂纹,所以中间AlGaN材料作为缓冲。AlN/AlGaN/AlN三明治结构对底层缺陷有很好的阻挡作用,使得位错缺陷在这一层发生扭曲和湮灭,避免了缺陷累积至多量子阱层,影响In组分的均匀分布。In one embodiment, the thickness of the compressive stress providing layer 51 is 10nm~100nm; the thickness of the exemplary compressive stress providing layer 51 is 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, but not Limited to this; the thickness of the first AlN layer 511 or the second AlN layer 513 is 5nm~20nm; the exemplary thickness of the first AlN layer 511 or the second AlN layer 513 is 7nm, 9nm, 11nm, 13nm, 15nm, 17nm, 19nm, but not limited thereto; the thickness of the AlGaN layer 512 is 10nm~80nm; the thickness of the exemplary AlGaN layer 512 is 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, but not limited thereto; The Al composition of the AlGaN layer 512 is 0.2~0.7; the exemplary Al composition of the AlGaN layer 512 is 0.3, 0.4, 0.5, and 0.6, but is not limited thereto. In the compressive stress providing layer, since Al atoms are small and AlN and AlGaN materials have small lattice constants, compressive stress can be provided to the epitaxial layer. The compressive stress providing layer is an AlN/AlGaN/AlN sandwich structure. The AlN layer at high temperatures has a high density. However, continuous high-temperature growth of an AlN layer that is too thick will easily cause cracks, so the middle AlGaN material serves as a buffer. The AlN/AlGaN/AlN sandwich structure has a good blocking effect on underlying defects, causing dislocation defects to be distorted and annihilated in this layer, preventing defects from accumulating into the multi-quantum well layer and affecting the uniform distribution of the In component.

在一种实施方式中,所述张应力提供层52的厚度为10nm~100nm;示例性的张应力提供层52的厚度为20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm,但不限于此;所述第一InGaN层521或第二InGaN层523的厚度为10nm~50nm;示例性的第一InGaN层521或第二InGaN层523的厚度为20nm、30nm、40nm,但不限于此;所述InN层522的厚度为5nm~20nm;示例性的所述InN层522的厚度为7nm、9nm、11nm、13nm、15nm、17nm、19nm,但不限于此;所述第一InGaN层521或第二InGaN层523的In组分为0.1~0.5;示例性的第一InGaN层521或第二InGaN层523的In组分为0.2、0.3、0.4,但不限于此。所述张应力提供层中,由于In原子大,InN和InGaN材料晶格质量大,可以提供张应力。所述张应力提供层为InGaN/InN/InGaN三明治结构,其不仅可以缓解InN材料稳定性差的问题,而且其和多量子阱层中势阱层的InGaN材料晶格失配小,可以减少多量子阱层所受的压应力,避免压应力过大导致In组分分布不均匀,从而避免加重In偏析现象。In one embodiment, the thickness of the tensile stress providing layer 52 is 10nm~100nm; the thickness of the exemplary tensile stress providing layer 52 is 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, but not Limited to this; the thickness of the first InGaN layer 521 or the second InGaN layer 523 is 10nm~50nm; the thickness of the exemplary first InGaN layer 521 or the second InGaN layer 523 is 20nm, 30nm, or 40nm, but is not limited thereto. ; The thickness of the InN layer 522 is 5nm~20nm; Exemplary thicknesses of the InN layer 522 are 7nm, 9nm, 11nm, 13nm, 15nm, 17nm, 19nm, but are not limited thereto; The first InGaN layer 521 Or the In composition of the second InGaN layer 523 is 0.1~0.5; the exemplary In composition of the first InGaN layer 521 or the second InGaN layer 523 is 0.2, 0.3, or 0.4, but is not limited thereto. In the tensile stress providing layer, due to the large In atoms and the large lattice quality of InN and InGaN materials, tensile stress can be provided. The tensile stress providing layer is an InGaN/InN/InGaN sandwich structure, which can not only alleviate the problem of poor stability of InN materials, but also has a small lattice mismatch with the InGaN material of the potential well layer in the multi-quantum well layer, which can reduce the number of multi-quantum wells. The compressive stress on the well layer prevents uneven distribution of In components caused by excessive compressive stress, thereby avoiding aggravation of In segregation.

需要说明的是,本发明的所述压应力提供层和张应力提供层是通过设置特定的厚度、Al/In组分来调节多量子阱层的生长时的翘曲。具体地,本发明的所述压应力提供层的Al组分多,厚度更厚,则生长至多量子阱层时,翘曲偏凹;所述张应力提供层的In组分多,厚度更厚,则生长至多量子阱层时,翘曲偏凸。在最靠近多量子阱层的位置,对多量子阱层的生长影响更敏感,所以比通过形核层厚度控制多量子阱层的翘曲更精准,波长均匀性更好。It should be noted that the compressive stress providing layer and the tensile stress providing layer of the present invention adjust the warpage during the growth of the multi-quantum well layer by setting a specific thickness and Al/In composition. Specifically, if the compressive stress providing layer of the present invention has a large Al component and is thicker, the warpage will be concave when growing to the multi-quantum well layer; the tensile stress providing layer has a large In component and is thicker. , then when the multi-quantum well layer is grown, the warpage becomes convex. The position closest to the multi-quantum well layer is more sensitive to the growth of the multi-quantum well layer, so it is more accurate and has better wavelength uniformity than controlling the warpage of the multi-quantum well layer through the thickness of the nucleation layer.

综上,本发明提出的波长均匀性调控层可以在多量子阱层生长前,调整翘曲,更加精准的控制多量子阱层生长时的翘曲,增加发光波长的均匀性。同时,减少了多量子阱层的缺陷,减少了多量子阱层生长时的应力,增加了In组分分布的均匀性,增加发光波长的均匀性。同时由于多量子阱层应力的减少,缺陷的减少,可以增加电子空穴的复合效率,增加发光二极管的发光效率。In summary, the wavelength uniformity control layer proposed by the present invention can adjust the warpage before the growth of the multi-quantum well layer, more accurately control the warpage during the growth of the multi-quantum well layer, and increase the uniformity of the luminescence wavelength. At the same time, the defects of the multi-quantum well layer are reduced, the stress during the growth of the multi-quantum well layer is reduced, the uniformity of the In component distribution is increased, and the uniformity of the luminescence wavelength is increased. At the same time, due to the reduction of stress and defects in the multi-quantum well layer, the recombination efficiency of electrons and holes can be increased, and the luminous efficiency of the light-emitting diode can be increased.

相应地,本发明提供了一种发光二极管外延片的制备方法,如图2所示,包括以下步骤:Correspondingly, the present invention provides a method for preparing a light-emitting diode epitaxial wafer, as shown in Figure 2, including the following steps:

S1、准备衬底1;S1. Prepare substrate 1;

在一种实施方式中,采用蓝宝石衬底。优选地,控制反应室温度为1000℃~1200℃,控制反应室压力为200torr~600torr,在H2气氛下对衬底进行5min~8min的高温退火,对衬底表面的颗粒和氧化物进行清洁。In one embodiment, a sapphire substrate is used. Preferably, the temperature of the reaction chamber is controlled to be 1000℃~1200℃, the pressure of the reaction chamber is controlled to be 200torr~600torr, the substrate is annealed at a high temperature for 5min~8min in an H2 atmosphere, and the particles and oxides on the surface of the substrate are cleaned. .

S2、在所述衬底1上依次沉积形核层2、本征GaN层3、N型半导体层4、波长均匀性调控层5、多量子阱层6、电子阻挡层7、P型半导体层8。S2. Deposit sequentially on the substrate 1 the nucleation layer 2, the intrinsic GaN layer 3, the N-type semiconductor layer 4, the wavelength uniformity control layer 5, the multiple quantum well layer 6, the electron blocking layer 7, and the P-type semiconductor layer. 8.

如图3所示,步骤S2包括以下步骤:As shown in Figure 3, step S2 includes the following steps:

S21、在衬底1上沉积形核层2。S21. Deposit the nucleation layer 2 on the substrate 1.

在一种实施方式中,形核层的材料为AlGaN或AlN。本层主要用于提供晶种,缓解衬底和外延层的晶格失配,提升外延片晶格质量。优选地,控制反应室温度为500℃~700℃,反应室压力为200torr~400torr,通入N源、Ga源、Al源,N2和H2做载气,生长厚度为20nm~40nm的AlGaN作为形核层。In one implementation, the material of the nucleation layer is AlGaN or AlN. This layer is mainly used to provide crystal seeds, alleviate the lattice mismatch between the substrate and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. Preferably, the reaction chamber temperature is controlled to 500°C~700°C, the reaction chamber pressure is 200torr~400torr, N source, Ga source, and Al source are introduced, N 2 and H 2 are used as carrier gases, and AlGaN with a thickness of 20nm~40nm is grown. as nucleation layer.

S22、在形核层2上沉积本征GaN层3。S22. Deposit the intrinsic GaN layer 3 on the nucleation layer 2.

在一种实施方式中,将反应室的温度控制在1100℃~1150℃,压力控制为100torr~500torr,通入N源、Ga源,生长厚度为300nm~800nm的本征GaN层。In one embodiment, the temperature of the reaction chamber is controlled at 1100°C to 1150°C, the pressure is controlled at 100torr to 500torr, N source and Ga source are introduced, and an intrinsic GaN layer with a thickness of 300nm to 800nm is grown.

S23、在本征GaN层3上沉积N型半导体层4。S23. Deposit the N-type semiconductor layer 4 on the intrinsic GaN layer 3.

在一种实施方式中,将反应室的温度控制在1100℃~1150℃,压力控制为100torr~500torr,通入N源、Ga源、Si源,生长厚度为1μm~3μm的N型GaN层作为主要提供电子的N型半导体层。In one embodiment, the temperature of the reaction chamber is controlled at 1100°C~1150°C, the pressure is controlled at 100torr~500torr, N source, Ga source, and Si source are introduced, and an N-type GaN layer with a thickness of 1 μm~3 μm is grown as N-type semiconductor layer that mainly provides electrons.

S24、在N型半导体层4上沉积波长均匀性调控层5。S24. Deposit the wavelength uniformity control layer 5 on the N-type semiconductor layer 4.

在一种实施方式中,所述压应力提供层采用下述方法制得:In one embodiment, the compressive stress providing layer is made by the following method:

将反应室温度控制在1000℃~1100℃,反应室压力控制在100torr~500torr,通入Al源、N源,完成第一AlN层的沉积,再通入Al源、Ga源、N源,完成所述AlGaN层的沉积,然后通入Al源、N源,完成所述第二AlN层的沉积。Control the temperature of the reaction chamber at 1000℃~1100℃ and the pressure of the reaction chamber at 100torr~500torr. Pass in the Al source and N source to complete the deposition of the first AlN layer. Then feed in the Al source, Ga source and N source to complete. After the deposition of the AlGaN layer, the Al source and the N source are introduced to complete the deposition of the second AlN layer.

在一种实施方式中,所述张应力提供层采用下述方法制得:In one embodiment, the tensile stress providing layer is made by the following method:

将反应室温度控制在800℃~900℃,反应室压力控制在100torr~500torr,通入Ga源、In源、N源,完成所述第一InGaN层的沉积,再通入In源、N源,完成所述InN层的沉积,然后通入Ga源、In源、N源,完成所述第二InGaN层的沉积。The temperature of the reaction chamber is controlled at 800°C~900°C, and the pressure of the reaction chamber is controlled at 100torr~500torr. The Ga source, In source, and N source are introduced to complete the deposition of the first InGaN layer, and then the In source and N source are introduced. , to complete the deposition of the InN layer, and then pass in the Ga source, In source, and N source to complete the deposition of the second InGaN layer.

需要说明的是,所述压应力提供层采用高温生长,高温生长的AlN层有很高的致密度,但是连续高温生长厚度过高的AlN层会容易产生裂纹,所以中间AlGaN材料作为缓冲。所述张应力提供层采用低温生长,In组分并入需要低温生长,并且由于InN材料稳定性差,采用InGaN/InN/InGaN三明治结构能够提高稳定性。It should be noted that the compressive stress providing layer is grown at high temperature. The AlN layer grown at high temperature has a high density. However, continuous high-temperature growth of an AlN layer that is too thick will easily cause cracks, so the intermediate AlGaN material serves as a buffer. The tensile stress providing layer adopts low-temperature growth. The incorporation of the In component requires low-temperature growth. Since InN material has poor stability, the stability can be improved by using an InGaN/InN/InGaN sandwich structure.

S25、在波长均匀性调控层5上沉积多量子阱层6。S25. Deposit the multi-quantum well layer 6 on the wavelength uniformity control layer 5.

在一种实施方式中,所述多量子阱层为交替堆叠的InGaN量子阱层和GaN量子垒层,堆叠周期数3~15个;其中,InGaN量子阱层生长温度为700℃~800℃,厚度为2nm~5nm,生长压力100torr~500torr;GaN量子垒层生长温度为800℃~900℃,厚度为5nm~15nm,生长压力100torr~500torr。In one embodiment, the multiple quantum well layer is an alternately stacked InGaN quantum well layer and a GaN quantum barrier layer, with a stacking cycle number of 3 to 15; wherein the growth temperature of the InGaN quantum well layer is 700°C to 800°C. The thickness is 2nm~5nm, and the growth pressure is 100torr~500torr; the growth temperature of the GaN quantum barrier layer is 800℃~900℃, the thickness is 5nm~15nm, and the growth pressure is 100torr~500torr.

S26、在多量子阱层6上沉积电子阻挡层7。S26. Deposit the electron blocking layer 7 on the multi-quantum well layer 6.

在一种实施方式中,电子阻挡层为交替堆叠的InGaN层和AlGaN层,堆叠周期数3~15个,将反应室温度控制为900℃~1000℃,反应室压力控制在100torr~500torr,通入相应的材料源,生长得到电子阻挡层。In one implementation, the electron blocking layer is an alternately stacked InGaN layer and an AlGaN layer. The number of stacking cycles is 3 to 15. The temperature of the reaction chamber is controlled to 900°C to 1000°C, and the pressure of the reaction chamber is controlled to 100torr to 500torr. Input the corresponding material source and grow the electron blocking layer.

S27、在电子阻挡层7上沉积P型半导体层8。S27. Deposit the P-type semiconductor layer 8 on the electron blocking layer 7.

在一种实施方式中,将反应室的温度控制在800℃~1000℃,压力控制为100torr~300torr,通入N源、Ga源、Mg源,生长厚度为10nm~50nm的P型GaN层作为P型半导体层,其Mg掺杂浓度为5×1017atoms/cm3~1×1020atoms/cm3。Mg掺杂浓度过高会破坏晶体质量,而掺杂浓度较低则会影响空穴浓度。In one embodiment, the temperature of the reaction chamber is controlled at 800°C~1000°C, the pressure is controlled at 100torr~300torr, N source, Ga source, and Mg source are introduced, and a P-type GaN layer with a thickness of 10nm~50nm is grown as The P-type semiconductor layer has a Mg doping concentration of 5×10 17 atoms/cm 3 ~1×10 20 atoms/cm 3 . Too high a Mg doping concentration will destroy the crystal quality, while a low doping concentration will affect the hole concentration.

相应地,本发明还提供了一种LED,所述LED包括上述的发光二极管外延片。所述LED的光电效率得到有效提升,且其他项电学性能良好。Correspondingly, the present invention also provides an LED, which includes the above-mentioned light-emitting diode epitaxial wafer. The photoelectric efficiency of the LED is effectively improved, and other electrical properties are good.

下面以具体实施例进一步说明本发明:The present invention will be further described below with specific examples:

实施例1Example 1

本实施例提供一种发光二极管外延片,包括衬底,所述衬底上依次设有形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;This embodiment provides a light-emitting diode epitaxial wafer, including a substrate. The substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity control layer, a multi-quantum well layer, and an electron blocking layer. , P-type semiconductor layer;

所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited sequentially. The tensile stress providing layer includes a sequentially deposited The first InGaN layer, the InN layer, and the second InGaN layer.

所述第一AlN层或第二AlN层的厚度为10nm,所述AlGaN层的厚度为50nm、Al组分为0.5。The thickness of the first AlN layer or the second AlN layer is 10 nm, the thickness of the AlGaN layer is 50 nm, and the Al composition is 0.5.

所述第一InGaN层或第二InGaN层的厚度为30nm、In组分为0.3,所述InN层的厚度为10nm。The thickness of the first InGaN layer or the second InGaN layer is 30 nm, the In composition is 0.3, and the thickness of the InN layer is 10 nm.

实施例2Example 2

本实施例提供一种发光二极管外延片,包括衬底,所述衬底上依次设有形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;This embodiment provides a light-emitting diode epitaxial wafer, including a substrate. The substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity control layer, a multi-quantum well layer, and an electron blocking layer. , P-type semiconductor layer;

所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited sequentially. The tensile stress providing layer includes a sequentially deposited The first InGaN layer, the InN layer, and the second InGaN layer.

所述第一AlN层或第二AlN层的厚度为5nm,所述AlGaN层的厚度为80nm、Al组分为0.2。The thickness of the first AlN layer or the second AlN layer is 5 nm, the thickness of the AlGaN layer is 80 nm, and the Al composition is 0.2.

所述第一InGaN层或第二InGaN层的厚度为10nm、In组分为0.5,所述InN层的厚度为20nm。The thickness of the first InGaN layer or the second InGaN layer is 10 nm, the In composition is 0.5, and the thickness of the InN layer is 20 nm.

实施例3Example 3

本实施例提供一种发光二极管外延片,包括衬底,所述衬底上依次设有形核层、本征GaN层、N型半导体层、波长均匀性调控层、多量子阱层、电子阻挡层、P型半导体层;This embodiment provides a light-emitting diode epitaxial wafer, including a substrate. The substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity control layer, a multi-quantum well layer, and an electron blocking layer. , P-type semiconductor layer;

所述波长均匀性调控层包括压应力提供层和张应力提供层,所述压应力提供层包括依次沉积的第一AlN层、AlGaN层、第二AlN层,所述张应力提供层包括依次沉积的第一InGaN层、InN层、第二InGaN层。The wavelength uniformity control layer includes a compressive stress providing layer and a tensile stress providing layer. The compressive stress providing layer includes a first AlN layer, an AlGaN layer, and a second AlN layer deposited sequentially. The tensile stress providing layer includes a sequentially deposited The first InGaN layer, the InN layer, and the second InGaN layer.

所述第一AlN层或第二AlN层的厚度为20nm,所述AlGaN层的厚度为10nm、Al组分为0.7。The thickness of the first AlN layer or the second AlN layer is 20 nm, the thickness of the AlGaN layer is 10 nm, and the Al composition is 0.7.

所述第一InGaN层或第二InGaN层的厚度为40nm、In组分为0.1,所述InN层的厚度为5nm。The thickness of the first InGaN layer or the second InGaN layer is 40 nm, the In composition is 0.1, and the thickness of the InN layer is 5 nm.

对比例1Comparative example 1

本对比例提供一种发光二极管外延片,与实施例1的不同之处在于:不设有波长均匀性调控层,其余均与实施例1相同。This comparative example provides a light-emitting diode epitaxial wafer. The difference from Embodiment 1 is that there is no wavelength uniformity control layer, and the rest are the same as Embodiment 1.

对比例2Comparative example 2

本对比例提供一种发光二极管外延片,与实施例1的不同之处在于:其波长均匀性调控层不设有压应力提供层,其余均与实施例1相同。This comparative example provides a light-emitting diode epitaxial wafer. The difference from Embodiment 1 is that the wavelength uniformity control layer does not have a compressive stress providing layer. The rest is the same as Embodiment 1.

对比例3Comparative example 3

本对比例提供一种发光二极管外延片,与实施例1的不同之处在于:其波长均匀性调控层不设有张应力提供层,其余均与实施例1相同。This comparative example provides a light-emitting diode epitaxial wafer. The difference from Embodiment 1 is that the wavelength uniformity control layer does not have a tensile stress providing layer. The rest is the same as Embodiment 1.

以实施例1~实施例3和对比例1~对比例3制得发光二极管外延片使用相同芯片工艺条件制备成成10 mil*24 mil芯片,分别抽取300颗LED芯片,在在120 mA/ 60 mA电流下测试波长均匀性和亮度,具体测试结果如表1所示。The light-emitting diode epitaxial wafers prepared in Examples 1 to 3 and Comparative Examples 1 to 3 were prepared into 10 mil*24 mil chips using the same chip process conditions, and 300 LED chips were extracted respectively. At 120 mA/60 The wavelength uniformity and brightness were tested under mA current. The specific test results are shown in Table 1.

表1实施例1~实施例3和对比例1~对比例3制得LED的性能测试结果Table 1 Performance test results of LEDs prepared in Examples 1 to 3 and Comparative Examples 1 to 3

由上述结果可知,本发明提供的发光二极管外延片,具有特定结构的波长均匀性调控层,其可以在多量子阱层生长前,调整翘曲,更加精准的控制多量子阱层生长时的翘曲,增加发光波长的均匀性。同时,减少了多量子阱层的缺陷,减少了多量子阱层生长时的应力,增加了In组分分布的均匀性,增加发光波长的均匀性。同时由于多量子阱层应力的减少,缺陷的减少,可以增加电子空穴的复合效率,增加发光二极管的发光效率。It can be seen from the above results that the light-emitting diode epitaxial wafer provided by the present invention has a wavelength uniformity control layer with a specific structure, which can adjust the warpage before the growth of the multi-quantum well layer and more accurately control the warpage during the growth of the multi-quantum well layer. Curved to increase the uniformity of the luminous wavelength. At the same time, the defects of the multi-quantum well layer are reduced, the stress during the growth of the multi-quantum well layer is reduced, the uniformity of the In component distribution is increased, and the uniformity of the luminescence wavelength is increased. At the same time, due to the reduction of stress and defects in the multi-quantum well layer, the recombination efficiency of electrons and holes can be increased, and the luminous efficiency of the light-emitting diode can be increased.

以上所述是发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也视为本发明的保护范围。The above is the preferred embodiment of the invention. It should be pointed out that for those of ordinary skill in the art, several improvements and modifications can be made without departing from the principles of the invention, and these improvements and modifications are also regarded as protection scope of the present invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, wherein a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity regulating layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer are sequentially arranged on the substrate;
the wavelength uniformity regulating and controlling layer comprises a compressive stress providing layer and a tensile stress providing layer, wherein the compressive stress providing layer comprises a first AlN layer, an AlGaN layer and a second AlN layer which are sequentially deposited, and the tensile stress providing layer comprises a first InGaN layer, an InN layer and a second InGaN layer which are sequentially deposited.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the compressive stress providing layer has a thickness of 10nm to 100nm;
the tensile stress providing layer has a thickness of 10 nm-100 nm.
3. The light-emitting diode epitaxial wafer according to claim 1, wherein the thickness of the first AlN layer or the second AlN layer is 5 nm-20 nm;
the thickness of the AlGaN layer is 10 nm-80 nm.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the Al composition of the AlGaN layer is 0.2 to 0.7.
5. The light emitting diode epitaxial wafer of claim 1, wherein the thickness of the first InGaN layer or the second InGaN layer is 10 nm-50 nm;
the thickness of the InN layer is 5 nm-20 nm.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the In composition of the first InGaN layer or the second InGaN layer is 0.1-0.5.
7. A method for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, comprising the following steps:
s1, preparing a substrate;
s2, sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a wavelength uniformity regulating layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer on the substrate;
the wavelength uniformity regulating and controlling layer comprises a compressive stress providing layer and a tensile stress providing layer, wherein the compressive stress providing layer comprises a first AlN layer, an AlGaN layer and a second AlN layer which are sequentially deposited, and the tensile stress providing layer comprises a first InGaN layer, an InN layer and a second InGaN layer which are sequentially deposited.
8. The method for manufacturing a light-emitting diode epitaxial wafer according to claim 7, wherein the compressive stress providing layer is manufactured by the following method:
controlling the temperature of a reaction chamber at 1000-1100 ℃, controlling the pressure of the reaction chamber at 100-500 torr, introducing an Al source and an N source to finish the deposition of a first AlN layer, introducing the Al source, the Ga source and the N source to finish the deposition of the AlGaN layer, and then introducing the Al source and the N source to finish the deposition of a second AlN layer.
9. The method of manufacturing a light emitting diode epitaxial wafer of claim 7, wherein the tensile stress providing layer is manufactured by:
and controlling the temperature of the reaction chamber at 800-900 ℃, controlling the pressure of the reaction chamber at 100-500 torr, introducing a Ga source, an In source and an N source to finish the deposition of the first InGaN layer, introducing the In source and the N source to finish the deposition of the InN layer, and then introducing the Ga source, the In source and the N source to finish the deposition of the second InGaN layer.
10. An LED, characterized in that the LED comprises a light emitting diode epitaxial wafer according to any one of claims 1 to 6.
CN202311127603.3A 2023-09-04 2023-09-04 LED epitaxial wafer, preparation method thereof and LED Pending CN116845158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311127603.3A CN116845158A (en) 2023-09-04 2023-09-04 LED epitaxial wafer, preparation method thereof and LED

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311127603.3A CN116845158A (en) 2023-09-04 2023-09-04 LED epitaxial wafer, preparation method thereof and LED

Publications (1)

Publication Number Publication Date
CN116845158A true CN116845158A (en) 2023-10-03

Family

ID=88171111

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311127603.3A Pending CN116845158A (en) 2023-09-04 2023-09-04 LED epitaxial wafer, preparation method thereof and LED

Country Status (1)

Country Link
CN (1) CN116845158A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117293241A (en) * 2023-11-27 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207909908U (en) * 2018-02-12 2018-09-25 厦门三安光电有限公司 Uv led
CN112242460A (en) * 2020-09-29 2021-01-19 苏州紫灿科技有限公司 AlN composite film with Si-doped insertion layer and epitaxial growth method thereof
CN115188863A (en) * 2022-09-09 2022-10-14 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN115458650A (en) * 2022-11-10 2022-12-09 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode
CN115985959A (en) * 2022-12-30 2023-04-18 华灿光电(苏州)有限公司 Nitride semiconductor device having composite buffer layer and method for manufacturing the same
CN116207197A (en) * 2023-05-06 2023-06-02 江西兆驰半导体有限公司 High-efficiency light-emitting diode epitaxial wafer and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207909908U (en) * 2018-02-12 2018-09-25 厦门三安光电有限公司 Uv led
CN112242460A (en) * 2020-09-29 2021-01-19 苏州紫灿科技有限公司 AlN composite film with Si-doped insertion layer and epitaxial growth method thereof
CN115188863A (en) * 2022-09-09 2022-10-14 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN115458650A (en) * 2022-11-10 2022-12-09 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode
CN115985959A (en) * 2022-12-30 2023-04-18 华灿光电(苏州)有限公司 Nitride semiconductor device having composite buffer layer and method for manufacturing the same
CN116207197A (en) * 2023-05-06 2023-06-02 江西兆驰半导体有限公司 High-efficiency light-emitting diode epitaxial wafer and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117293241A (en) * 2023-11-27 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117293241B (en) * 2023-11-27 2024-01-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode

Similar Documents

Publication Publication Date Title
CN115458650B (en) Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode
CN115472720B (en) Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN116190519B (en) LED epitaxial wafer, preparation method thereof and LED
CN103811601B (en) A kind of GaN base LED multi-level buffer layer growth method with Sapphire Substrate as substrate
CN112786746B (en) Epitaxial wafer of light-emitting diode and preparation method thereof
CN106653971B (en) Epitaxial wafer of GaN-based light emitting diode and growth method thereof
CN117133841B (en) InGaN-based green light-emitting diode epitaxial wafer and preparation method thereof, LED
CN115347097B (en) Light emitting diode epitaxial wafer and preparation method thereof
CN116344695A (en) LED epitaxial wafer, preparation method thereof and LED
CN115458649A (en) Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN116504895B (en) LED epitaxial wafer, preparation method thereof and LED
CN117276428A (en) InGaN-based light-emitting diode epitaxial wafer, preparation method thereof and LED
CN116190520A (en) LED epitaxial wafer for improving wavelength yield, preparation method thereof and LED chip
CN106848017B (en) Epitaxial wafer of GaN-based light emitting diode and growth method thereof
CN116845158A (en) LED epitaxial wafer, preparation method thereof and LED
CN110620168A (en) LED epitaxial growth method
CN117410402B (en) Light-emitting diode epitaxial wafer, preparation method thereof and Micro-LED chip
CN116454180B (en) Light-emitting diode epitaxial wafer and preparation method thereof, LED
CN116960248B (en) Light-emitting diode epitaxial wafer and preparation method thereof
CN116936700B (en) Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode
CN117712254A (en) A high-light-efficiency light-emitting diode epitaxial wafer and its preparation method
CN117613156A (en) Light-emitting diode epitaxial wafer and preparation method thereof, LED
CN116682909A (en) A kind of LED epitaxial wafer, preparation method and LED chip
CN116364819A (en) Light-emitting diode epitaxial wafer and preparation method thereof, LED
CN116779736A (en) Light-emitting diode epitaxial wafer and preparation method thereof, LED

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20231003