CN116844989A - MAP generation method, and identification method and system for chip failure reasons - Google Patents
MAP generation method, and identification method and system for chip failure reasons Download PDFInfo
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- CN116844989A CN116844989A CN202311127742.6A CN202311127742A CN116844989A CN 116844989 A CN116844989 A CN 116844989A CN 202311127742 A CN202311127742 A CN 202311127742A CN 116844989 A CN116844989 A CN 116844989A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
The application relates to the field of chips and discloses a MAP generation method, a chip failure reason identification method and a chip failure reason identification system. The MAP generation method comprises the following steps: generating a first MAP of the wafer based on test results of a last test flow of the wafer by a first test factory, wherein the first MAP comprises: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing; generating a second MAP based on a test result of a second test factory on the first test flow of the wafer; and merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein merging the first MAP and the second MAP based on the preset merging rule comprises: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag. The application can effectively avoid the situation that the failure chip is wrongly classified, thereby improving the accuracy of test data analysis.
Description
Technical Field
The application relates to the field of chips, in particular to a MAP generation method, a chip failure reason identification method and a chip failure reason identification system.
Background
With the increase of chip functional modules and the increase of application temperature ranges, when performing wafer (CP) testing, testing under multiple temperature conditions needs to be performed on different functional modules of a chip to fully evaluate the performance of the functional modules. In the current industry production mode, the testing of different functional modules of a chip is usually completed by different testing factories in cooperation with each other. For such cross-factory multi-flow CP testing, it is particularly important how to accurately distinguish in the final test MAP which test factory (which functional module test) detected the failed chip, which facilitates the engineer's targeted analysis and improvement.
Currently, the CP test flow generally adopts a write/read Pass Flag (Pass Flag) manner to complete the linking between the tests. The chips that passed the previous test in the test factory will be written into Pass Flag, while the chips that fail the test will not be written into. In the CP test flow of the subsequent test factory, a step of reading the Pass Flag is provided, if the Pass Flag is read, the chip continues to be tested until the Pass (Pass) or a certain test item (Bin) is finally invalid; if the Pass Flag is not read, the chip is marked as a feature Bin and the test is stopped, so that all the chips marked as the feature Bin are the failed chips tested in the previous test plant.
However, in the actual CP test process, in order to rapidly screen out the failed chip while checking electrical connectivity between the test device and the chip, an on/off circuit and leakage related test step is first performed, and then a Pass Flag reading step is performed. Based on this, there is a chip that fails in the actual test process in the previous test factory, which fails due to open/short or leakage before the step of reading Pass Flag in the subsequent test factory, and this chip is labeled as Bin related to open/short or leakage. Thus, in the final CP MAP analysis, the chip may be classified as a test failure of the subsequent test plant, rather than a test failure of the actual previous test plant, thereby seriously affecting the accuracy of the test data.
Disclosure of Invention
The application aims to provide a MAP generation method, a chip failure reason identification method and a chip failure reason identification system, which can effectively avoid the situation that a failed chip is wrongly classified, thereby improving the accuracy of test data analysis.
In order to achieve the above object, an aspect of the present application provides a MAP generation method, comprising: generating a first MAP of the wafer based on test results of a last test flow of the wafer by a first test factory, wherein the first MAP comprises: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing; generating a second MAP based on a test result of a second test factory on the first test flow of the wafer; and merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein merging the first MAP and the second MAP based on the preset merging rule comprises: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
Preferably, the merging the first MAP and the second MAP based on a preset merging rule further includes: and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
Preferably, the MAP generation method further comprises: obtaining a test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and updating the target MAP based on the test result of the second test flow of the second test factory to the other chips.
Preferably, the second MAP is a test item MAP.
Through the technical scheme, the method and the device for generating the first MAP of the wafer creatively generate the first MAP of the wafer based on the test result of the last test flow of the wafer by the first test factory; generating a second MAP based on a test result of a second test factory on the first test flow of the wafer; and merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein merging the first MAP and the second MAP based on the preset merging rule comprises: in the case where the flag of the first chip in the first MAP is a test failed flag, the first chip is marked as a specific flag. Therefore, the application can effectively avoid the situation that the failure chip is wrongly classified, thereby improving the accuracy of test data analysis.
The second aspect of the present application provides a method for identifying a failure cause of a chip, the method comprising: acquiring a target MAP according to the MAP generation method; and identifying a cause of failure of a chip in the target MAP based on the target MAP, wherein the identifying the cause of failure of the chip in the target MAP comprises: and in the case that the mark of a chip in the target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
Preferably, the identifying the failure cause of the chip in the target MAP further includes: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
Preferably, in the case of updating the target MAP according to the MAP generation method, the identifying the failure cause of the chip in the target MAP further includes: in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
Through the technical scheme, the method creatively acquires the target MAP according to the MAP generation method; and identifying a cause of failure of a chip in the target MAP based on the target MAP, wherein the identifying the cause of failure of the chip in the target MAP comprises: in the case that the mark of a chip in the target MAP is a specific mark, the failure reason of the chip is identified as the last test flow of the first test factory and/or the test object corresponding to the last test flow, so that the application can quickly and accurately identify the specific failure reason of the chip based on the target MAP.
A third aspect of the present application provides a MAP generation system comprising: the first generating device is configured to generate a first MAP of the wafer based on a test result of a last test procedure of the wafer by a first test factory, where the first MAP includes: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing; the second generating device is used for generating a second MAP based on the test result of the second test factory on the first test flow of the wafer; and a merging device for merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein the merging device for merging the first MAP and the second MAP based on the preset merging rule includes: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
Preferably, the merging means is configured to merge the first MAP and the second MAP based on a preset merge rule, and further includes: and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
Preferably, the MAP generation system further comprises: the obtaining device is used for obtaining the test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and updating means for updating the target MAP based on a test result of the second test flow of the second test factory to the other chip.
Preferably, the second MAP is a test item MAP.
Specific details and benefits of the MAP generation system provided in the embodiments of the present application can be found in the above description of the MAP generation method, and are not repeated here.
A fourth aspect of the present application provides an identification system of a failure cause of a chip, the identification system including: the MAP generation system is used for acquiring target MAP; and identifying means for identifying a failure cause of a chip in the target MAP based on the target MAP, wherein the identifying means for identifying a failure cause of a chip in the target MAP includes: and in the case that the mark of a chip in the target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
Preferably, the identifying means is configured to identify a failure cause of a chip in the target MAP further includes: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
Preferably, the identifying means is configured to identify a failure cause of a chip in the target MAP further includes: in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
Specific details and benefits of the system for identifying a failure cause of a chip provided in the embodiments of the present application can refer to the above description of the method for identifying a failure cause applicable to a chip, and are not repeated herein.
A fifth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the MAP generation method and/or the method of identifying a cause of failure of the chip.
A sixth aspect of the present application provides a chip for executing a computer program which, when executed by the chip, implements the MAP generation method and/or the method of identifying a cause of failure of the chip.
Additional features and advantages of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
fig. 1 is a flowchart of a MAP generation method according to an embodiment of the present application;
FIG. 2 is a flowchart of a MAP generation method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an Inkless MAP in a CP1 test according to an embodiment of the present application;
FIG. 4 is a diagram of a Bin MAP in a CP2 test according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a combined new MAP according to an embodiment of the application; and
fig. 6 is a schematic diagram of a target MAP provided in an embodiment of the present application.
Detailed Description
The following describes specific embodiments of the present application in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
Fig. 1 is a flowchart of a MAP generation method according to an embodiment of the present application. As shown in fig. 1, the MAP generation method may include: step S101, generating a first MAP of the wafer based on a test result of a last test procedure of the wafer by the first test factory, wherein the first MAP includes: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing; step S102, generating a second MAP based on a test result of a first test flow of the wafer by a second test factory; and step S103, merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP.
The following explanation and explanation are made with respect to the above steps S101 to S103, respectively. MAP herein refers to either "MAP" or "distribution MAP".
Step S101, based on the test result of the last test flow of the wafer by the first test factory, generating a first MAP of the wafer.
Wherein the first MAP may include: a first flag that characterizes the test as passing, and a second flag that characterizes the test as failing. For example, the first MAP may be an Inkless MAP shown in fig. 3, where "1" indicates that the test passes (the chip at the location is a test passing chip) and "x" indicates that the test fails (the chip at the location is a test failed chip). That is, the test results of the individual chips in the wafer may be characterized by the first MAP.
As shown in fig. 2, the previous test plant (e.g., test plant a) normally completes the test flow of "wafer (CP) test one" (which is the last test flow of test plant a), and then generates an Inkless MAP (as shown in fig. 3). In the MAP, the chip passing the test (Pass) and the chip failing the test (Fail) are marked by a distinction of '1' and 'x'. Of course, in practical application, other distinguishing marks can be used to distinguish and label different test results (Pass/Fail).
Step S102, a second MAP is generated based on the test results of the first test flow of the wafer by the second test factory.
Wherein the second MAP may be a test item MAP (i.e., bin MAP). For example, as shown in FIG. 4, the "pass" characterizes test pass; "Bin201/Bin202/Bin203 …/Bin209" indicates that the different test items related to open short circuit and leakage are failed, "Bin210" indicates that the first flag (test pass flag) is not read, and "Bin2XX" indicates that the other different test items in the 2 nd test flow in the test process (including the last test flow of the first test factory and the test flow of the second test factory) are failed (which can be reasonably defined according to practical applications). That is, the values in the different flags represent different test items that are unique, typically requiring testing of the test item corresponding to "Bin201/Bin202/Bin203 …/Bin209" before reading the test pass flag.
As shown in fig. 2, in the first "CP test two" of the subsequent test factory (e.g., test factory b), all chips in the wafer are tested according to the normal test procedure, and a Bin MAP is generated after the test is completed. In the MAP, the chip with the Pass (Pass), the different test items related to open short circuit and electric leakage do not Pass, the first mark is not read, and the other different test items are indicated to Pass through and can be marked by the differences of 'Pass', 'Bin 201/Bin202/Bin203 …/Bin 209', 'Bin 210', 'Bin 2 XX'.
Of course, in practical application, other distinguishing marks can be used to distinguish and label the test results of different test items.
Step S103, merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP.
For step S103, the merging the first MAP and the second MAP based on the preset merging rule may include: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
Wherein the specific tag may be a specially defined tag (e.g., a specially defined Bin), such as Bin999 in fig. 5.
As shown in fig. 2, the Bin MAP of "CP test two" is combined with the Inkless MAP of "CP test one" to form a new MAP (i.e., target MAP). Meanwhile, a preset merging rule is set: if the chip on the "CP test one" Inkless MAP is a Fail chip, then the chip on the combined new MAP is labeled as a specifically defined Bin (e.g., bin999 in FIG. 5).
In this way, whenever a chip fails in the previous "CP test one", the chip is finally grouped together on the new MAP into a specially defined Bin (e.g., bin999 in fig. 5). For example, 6 chips in FIG. 3 are failed chips, and accordingly, bin of the 6 chips in FIG. 5 is Bin999. Based on this, when the failure cause of the chip is identified, the failure of the CP test of the chip can be identified by a specially defined Bin (for example, bin999 in fig. 5), so that the problem that the chip is misclassified due to the fact that Bin202 and Bin203 (actually the chips failed in the previous test factory) are covered by the subsequent test Bin in the prior art is avoided.
For step S103, the merging the first MAP and the second MAP based on the preset merging rule may further include: and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
Specifically, the following preset merge rules are also set: if the chip on the Inkless MAP of "CP test one" is a Pass chip, the chip on the combined new MAP is marked as the Bin that actually fails in "CP test two". For example, bin of 3 chips in fig. 4 is Bin2XX, and correspondingly, the 3 chips in fig. 3 are pass-through chips, and Bin of the 3 chips in fig. 5 is Bin2XX; in the case where the marks in fig. 3 and 4 each show that the same chip is a pass chip, bin of the same chip in fig. 5 is also a pass.
In an embodiment, the MAP generation method may further include: obtaining a test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and updating the target MAP based on the test result of the second test flow of the second test factory to the other chips.
Wherein the specific chip is a chip having a specifically defined Bin (e.g., bin999 in fig. 5).
For example, "Bin3XX" may be used to indicate that other different test items in the 3 rd test flow in the test procedure (including the last test flow of the first test plant and the test flow of the second test plant) fail (which may be reasonably defined according to the actual application).
If the second test factory performs a subsequent test procedure on the wafer, the second test factory may perform a test based on the new MAP, and at the same time, for the chips marked as the specifically defined Bin (for example, bin999 in fig. 5) in the new MAP, the test system sets that none of the chips is tested in the subsequent test procedure. For example, the test system marks the coordinates of the chips corresponding to each Bin999, and then the test system skips the chips based on the marks without making subsequent measurements. Thus, test plant b may skip the particular chip to test for a subsequent test flow of other chips in the wafer, and based on the test result (e.g., other test items of chips at 3 locations failed, the other test items failed with a "Bin3XX" flag), the new MAP may be updated, with fig. 6 showing the flag of chips at 3 locations in the final MAP as "Bin3XX". Thus, the failed chip from the previous test plant (e.g., test plant A) can be retained in the final MAP as a specifically defined Bin (e.g., bin999 in FIG. 5) until it reaches the final MAP as shown in FIG. 6.
The embodiment is also applicable to other subsequent testing processes of the second testing factory. For example, the MAP generation method may further include: obtaining a test result of the second test factory skipping a third test flow of the specific chip in the wafer to other chips, wherein a mark of the specific chip in the target MAP is the specific mark; and updating the target MAP based on the test result of the second test factory on the third test flow of the other chips. For details, see the update process of the test result based on the second test procedure.
After the new MAP is formed by merging, the subsequent testing flow does not need to test the failed chip of the previous testing factory, so that the testing time is shortened, and the testing resources are saved.
Taking an actual CP test flow of a certain wafer product as an example, its functional modules can be divided into a Flash module and a Logic module. The CP test flow is 3 paths, namely CP1, CP2 and CP3 respectively, wherein CP1 is a Flash test (performed in test factory a), and CP2 and CP3 are Logic tests (the test conditions of the two tests can be different, for example, the test temperatures are different, and the test is performed in test factory b).
First, after the CP1 test of test plant A is completed, an Inkless MAP is generated. In this MAP, all chips that pass the test are labeled "1" and all chips that fail the test are labeled "x". Fig. 3 shows the Inkless MAP after CP1 testing is completed.
And secondly, performing CP2 test on all chips according to a normal test flow in a test factory B, and generating a normal Bin MAP after the test is finished. Fig. 4 shows the Bin MAP after the CP2 test is completed.
Thirdly, combining the Bin MAP obtained by the CP2 with the Inkless MAP obtained by the CP1, and simultaneously setting a preset combining rule: if the chip on the Inkless MAP is marked as '1', the chip on the combined new MAP is marked as Bin which is actually failed in the CP2 test; if the chip on the Inkless MAP is labeled "x", then the chip on the new MAP after merging is labeled "Bin999". Fig. 5 shows a new MAP after combining the Inkless MAP and the Bin MAP, which effectively avoids the situation that Bin202 and Bin203 (actually, the chips failed in the previous test factory) in fig. 3 are covered by the subsequent test Bin.
Finally, before the CP3 test, the new combined MAP is set on the test system, and the chips marked as Bin999 in the new combined MAP are not tested in the CP3 test flow, and remain until the chips are in the final MAP (namely the target MAP) shown in FIG. 6, so that whether the chips are failed in the Flash module of the test plant A or the Logic module of the test plant B can be confirmed by distinguishing Bin999 from other Bin on the target MAP.
The number of test factories is two in the above embodiments, but it is also applicable to cross-factory testing between multiple test factories, so the specific contents in the above embodiments can be adopted as long as the flow connection between the test factories is involved.
It should be noted that, in the above embodiment, the first chip and the second chip are any chip; and MAP refers to the correspondence between the locations of the individual chips on the wafer and the test results.
In summary, the present application creatively generates the first MAP of the wafer based on the test result of the last test flow of the wafer by the first test factory; generating a second MAP based on a test result of a second test factory on the first test flow of the wafer; and merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein merging the first MAP and the second MAP based on the preset merging rule comprises: in the case where the flag of the first chip in the first MAP is a test failed flag, the first chip is marked as a specific flag. Therefore, the application can effectively avoid the situation that the failure chip is wrongly classified, thereby improving the accuracy of test data analysis.
The embodiment of the application also provides a method for identifying the failure reason of the chip, which comprises the following steps: acquiring a target MAP according to the MAP generation method; and identifying a cause of failure of a chip in the target MAP based on the target MAP.
The process of acquiring the target MAP according to the MAP generating method can be described in detail in the above corresponding description, and will not be repeated here.
Wherein, the identifying the failure cause of the chip in the target MAP may include: and in the case that the mark of a chip in the first target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
If a second test factory (e.g., test factory b) performs a test process (CP 2) on the wafer, the target MAP obtained according to the MAP generation method is the new MAP shown in fig. 5. Where the flags of the chips at 6 locations are specific flags (e.g., bin 999), then this indicates that the reason for the failure of these 6 chips is the last test flow (e.g., CP 1) of the first test plant (e.g., test plant a) and/or the corresponding test object (e.g., flash module).
If a second test factory (e.g., test factory b) performs two test flows (CP 2 and CP 3) on the wafer, the target MAP obtained according to the MAP generating method is the new MAP shown in fig. 6. Where the flags of the chips at 6 locations are specific flags (e.g., bin 999), then this indicates that the reason for the failure of these 6 chips is the last test flow (e.g., CP 1) of the first test plant (e.g., test plant a) and/or the corresponding test object (e.g., flash module).
In another embodiment, the identifying the failure cause of the chip in the target MAP may further include: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
If a second test factory (e.g., test factory b) performs a test process (CP 2) on the wafer, the target MAP obtained according to the MAP generation method is the new MAP shown in fig. 5. Where the flag of the chip at 3 locations is Bin2XX (which is neither a specific flag nor a test pass flag (e.g., "pass")), then the failure cause of the chip at 3 locations is the first test flow (e.g., CP 2) and/or the corresponding test object (Logic module) of the second test plant (e.g., test plant b).
In the case of updating the target MAP according to the MAP generation method, the identifying the failure cause of the chip in the target MAP further includes: in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
For example, in the updated target MAP, the "Bin2XX" indicates that the other different test items in the 2 nd test flow in the test procedure (including the last test flow of the first test plant and the test flow of the second test plant) do not pass; the "Bin3XX" is used for indicating that other different test items in the 3 rd test flow in the test process (comprising the last test flow of the first test factory and the test flow of the second test factory) do not pass; by "BinmXX" is meant that the other different test items in the mth test flow in the test procedure (including the last test flow of the first test plant and the test flow of the second test plant) do not pass, and so on.
If a second test factory (e.g., test factory b) performs two test flows (CP 2 and CP 3) on the wafer, the target MAP obtained according to the MAP generating method is the new MAP shown in fig. 6. Wherein the flag of the chip at 3 locations is Bin2XX (which is neither a specific flag nor a test pass flag (e.g. "pass")), then the failure cause of the chip at 3 locations is the first test flow (e.g., CP 2) and/or the corresponding test object (Logic module) of the second test plant (e.g., test plant b); where the flag of the chip at 3 locations is Bin3XX (which is neither a specific flag nor a test pass flag (e.g., "pass")), then the failure cause of the chip at 3 locations is the second test flow (e.g., CP 3) of the second test plant (e.g., test plant b) and/or the corresponding test object (Logic module).
In summary, the present application creatively obtains the target MAP according to the MAP generation method; and identifying a cause of failure of a chip in the target MAP based on the target MAP, wherein the identifying the cause of failure of the chip in the target MAP comprises: in the case that the mark of a chip in the target MAP is a specific mark, the failure reason of the chip is identified as the last test flow of the first test factory and/or the test object corresponding to the last test flow, so that the application can quickly and accurately identify the specific failure reason of the chip based on the target MAP.
An embodiment of the present application provides a MAP generation system including: the first generating device is configured to generate a first MAP of the wafer based on a test result of a last test procedure of the wafer by a first test factory, where the first MAP includes: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing; the second generating device is used for generating a second MAP based on the test result of the second test factory on the first test flow of the wafer; and a merging device for merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP, wherein the merging device for merging the first MAP and the second MAP based on the preset merging rule includes: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
Preferably, the merging means is configured to merge the first MAP and the second MAP based on a preset merge rule, and further includes: and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
Preferably, the MAP generation system further comprises: the obtaining device is used for obtaining the test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and updating means for updating the target MAP based on a test result of the second test flow of the second test factory to the other chip.
Preferably, the second MAP is a test item MAP.
Specific details and benefits of the MAP generation system provided in the embodiments of the present application can be found in the above description of the MAP generation method, and are not repeated here.
An embodiment of the present application provides a system for identifying a failure cause of a chip, including: the MAP generation system is used for acquiring target MAP; and identifying means for identifying a failure cause of a chip in the target MAP based on the target MAP, wherein the identifying means for identifying a failure cause of a chip in the target MAP includes: and in the case that the mark of a chip in the target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
Preferably, the identifying means is configured to identify a failure cause of a chip in the target MAP further includes: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
Preferably, the identifying means is configured to identify a failure cause of a chip in the target MAP further includes: in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
Specific details and benefits of the system for identifying a failure cause of a chip provided in the embodiments of the present application can refer to the above description of the method for identifying a failure cause applicable to a chip, and are not repeated herein.
An embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor implements the MAP generation method and/or the method for identifying a failure cause of the chip.
An embodiment of the present application provides a chip for executing a computer program, where the computer program when executed by the chip implements the MAP generation method and/or the method for identifying a failure cause of the chip.
Specifically, the present embodiment provides a chip including: a processor; a memory for storing a computer program for execution by the processor; the processor is configured to read the computer program from the memory, and execute the computer program to implement the MAP generation method and/or the method for identifying a failure cause of the chip.
The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application.
In addition, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described further.
Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, including instructions for causing a single-chip microcomputer, chip or processor (processor) to perform all or part of the steps of the methods of the embodiments described herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Moreover, any combination of the various embodiments of the application can be made without departing from the spirit of the application, which should also be considered as disclosed herein.
Claims (16)
1. A MAP generation method, characterized in that the MAP generation method comprises:
generating a first MAP of the wafer based on test results of a last test flow of the wafer by a first test factory, wherein the first MAP comprises: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing;
generating a second MAP based on a test result of a second test factory on the first test flow of the wafer; and
merging the first MAP and the second MAP based on a preset merging rule to obtain a target MAP,
wherein the merging the first MAP and the second MAP based on the preset merging rule includes: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
2. The MAP generation method of claim 1, wherein the merging the first MAP and the second MAP based on a preset merge rule further comprises:
and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
3. The MAP generation method according to claim 1 or 2, characterized in that the MAP generation method further comprises:
obtaining a test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and
and updating the target MAP based on the test result of the second test flow of the second test factory to the other chips.
4. The MAP generation method according to claim 1 or 2, characterized in that the second MAP is a test item MAP.
5. A method for identifying a cause of failure of a chip, the method comprising:
the MAP generation method according to any one of claims 1 to 4, obtaining a target MAP; and
identifying a cause of failure of a chip in the target MAP based on the target MAP,
wherein, the identifying the failure cause of the chip in the target MAP includes: and in the case that the mark of a chip in the target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
6. The method of identifying as in claim 5, wherein the identifying a cause of failure of a chip in the target MAP further comprises: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
7. The identification method according to claim 5, wherein in the case of updating the target MAP according to the MAP generation method of claim 3, the identifying the failure cause of the chip in the target MAP further comprises:
in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
8. A MAP generation system, characterized in that the MAP generation system comprises:
the first generating device is configured to generate a first MAP of the wafer based on a test result of a last test procedure of the wafer by a first test factory, where the first MAP includes: a first flag that characterizes the test as passing and a second flag that characterizes the test as not passing;
the second generating device is used for generating a second MAP based on the test result of the second test factory on the first test flow of the wafer; and
combining means for combining the first MAP and the second MAP based on a preset combining rule to acquire a target MAP,
the merging means for merging the first MAP and the second MAP based on a preset merging rule includes: in the case where the first chip in the first MAP has the second flag as the flag, the first chip is marked as a specific flag.
9. The MAP generation system of claim 8, wherein the means for merging the first MAP and the second MAP based on a preset merge rule further comprises:
and in the case that the mark of the second chip in the first MAP is the first mark, marking the second chip as the mark of the second chip in the second MAP.
10. The MAP generation system according to claim 8 or 9, characterized in that the MAP generation system further comprises:
the obtaining device is used for obtaining the test result of the second test flow of the specific chip in the wafer to other chips skipped by the second test factory, wherein the mark of the specific chip in the target MAP is the specific mark; and
and the updating device is used for updating the target MAP based on the test result of the second test flow of the second test factory to the other chips.
11. The MAP generation system of claim 8 or 9, wherein the second MAP is a test item MAP.
12. A system for identifying a cause of failure of a chip, the system comprising:
the MAP generation system according to any one of claims 8 to 11, for acquiring a target MAP; and
identifying means for identifying a failure cause of a chip in the target MAP based on the target MAP,
the identifying means is configured to identify a failure cause of a chip in the target MAP, including: and in the case that the mark of a chip in the target MAP is a specific mark, identifying the failure reason of the chip as the last test flow of the first test factory and/or a test object corresponding to the last test flow.
13. The identification system of claim 12, wherein the means for identifying a cause of failure of a chip in the target MAP further comprises: and in the case that the mark of a chip in the target MAP is not the specific mark or the test passing mark, identifying the failure reason of the chip as a first test flow of a second test factory and/or a test object corresponding to the first test flow.
14. The identification system of claim 12, wherein in the case where the MAP generation system is the MAP generation system of claim 10, the identifying means for identifying a cause of failure of a chip in the target MAP further comprises:
in the case that the flag of a chip in the updated target MAP is not the specific flag or the test passing flag and the flag of the chip is associated with a test flow, identifying the failure cause of the chip as the test flow and/or a test object corresponding to the test flow of the second test factory.
15. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, which when executed by a processor, implements the MAP generation method of any one of claims 1 to 4 and/or the method of identifying a cause of failure of the chip of any one of claims 5 to 7.
16. A chip for executing a computer program which, when executed by the chip, implements the MAP generation method of any one of claims 1 to 4 and/or the method of identifying a cause of failure of the chip of any one of claims 5 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117976567A (en) * | 2024-04-01 | 2024-05-03 | 华羿微电子股份有限公司 | Processing method and equipment for double-core continuous scribing MAP (MAP) slice-taking product |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241439A (en) * | 1991-01-16 | 1992-08-28 | Nec Kyushu Ltd | Ic testing system |
| CN106949926A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Wafer automated visual inspection system and automatically visual inspection method |
| CN108807212A (en) * | 2018-08-09 | 2018-11-13 | 德淮半导体有限公司 | Crystal round test approach and wafer tester |
| CN110176420A (en) * | 2019-07-11 | 2019-08-27 | 上海艾为电子技术股份有限公司 | A kind of chip MAP coordinate marking method, device and encapsulation chip |
| CN110907796A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Integrated circuit measurement result imaging analysis method and system |
| CN111128779A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN114093784A (en) * | 2021-11-25 | 2022-02-25 | 上海物骐微电子有限公司 | Wafer packaging method and device, electronic equipment and storage medium |
-
2023
- 2023-09-04 CN CN202311127742.6A patent/CN116844989B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241439A (en) * | 1991-01-16 | 1992-08-28 | Nec Kyushu Ltd | Ic testing system |
| CN106949926A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Wafer automated visual inspection system and automatically visual inspection method |
| CN108807212A (en) * | 2018-08-09 | 2018-11-13 | 德淮半导体有限公司 | Crystal round test approach and wafer tester |
| CN110907796A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Integrated circuit measurement result imaging analysis method and system |
| CN110176420A (en) * | 2019-07-11 | 2019-08-27 | 上海艾为电子技术股份有限公司 | A kind of chip MAP coordinate marking method, device and encapsulation chip |
| CN111128779A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN114093784A (en) * | 2021-11-25 | 2022-02-25 | 上海物骐微电子有限公司 | Wafer packaging method and device, electronic equipment and storage medium |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117976567A (en) * | 2024-04-01 | 2024-05-03 | 华羿微电子股份有限公司 | Processing method and equipment for double-core continuous scribing MAP (MAP) slice-taking product |
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