CN116825836A - A gate commutated thyristor - Google Patents

Abstract

The invention discloses a gate commutation thyristor, which includes: a first conductive type conductive layer, a second conductive type base region and a first conductive type base region arranged in sequence. The second conductive type base region includes a protrusion located in the center. and a horizontal part located on the periphery of the raised portion, the raised portion penetrates the first conductive type base area; a plurality of second conductive type short-circuit emitter areas are provided in the first conductive type base area, and the second conductive type short-circuit emitter area is The first surface of the first conductivity type conductive layer is not covered by the first conductivity type base region; at least one amplification gate is disposed on the first surface of the second conductivity type short-circuit emitter region; and is disposed on the first conductivity type base region opposite to A first surface of the first conductive type conductive layer and a thyristor functional layer facing away from the first surface of the second conductive type base region. The invention solves the technical problem in the prior art that the maximum electric field in the chip body is distributed at the terminal of the chip table, which easily causes blocking failure.

Description

A gate commutated thyristor

Technical field

The invention relates to the technical field of power semiconductor devices, and in particular to a gate commutation thyristor.

Background technique

IGCT (Integrated Gate-Commutated Thyristor, integrated gate commutated thyristor IGCT), as a fully controlled power semiconductor device, will be used in the field of DC power grids in the future due to its advantages such as large blocking capability, low on-state loss, and large power capacity. Has huge potential. One of the application requirements in this field is that the IGCT device can quickly transform into an on-state function when the rated blocking value is exceeded, and it is required that the device has a reliable short-circuit failure function when it may fail.

When the GCT (Gate Commutated Thyristors) chip is in a blocking state, a reverse bias voltage within -20V (or short circuit) must be applied to the gate-cathode of the device to avoid forward bias due to the gate-cathode junction. The injection effect significantly reduces the device voltage. When a forward voltage is applied between the anode and the cathode, the device is in a forward blocking state, and the blocking voltage is mainly borne by the reverse-biased blocking voltage main junction. At this time, the maximum electric field in the chip body is distributed at the terminal of the chip table. When the external voltage exceeds the chip's ability to withstand, an avalanche phenomenon will occur there, which may cause blocking failure. Secondly, the position where the dynamic avalanche is generated in the blocking state is located at the terminal, so most of the blocking failure locations are also located at the terminal, causing the device to be in a blocking state when it fails.

Contents of the invention

In view of this, embodiments of the present invention provide a gate commutation thyristor to solve the technical problem in the prior art that the maximum electric field in the chip body is distributed at the terminal of the chip table, which easily causes blocking failure.

The technical solutions provided by the embodiments of the present invention are as follows:

A first aspect of an embodiment of the present invention provides a gate commutation thyristor, including: a first conductive type conductive layer, a second conductive type base region and a first conductive type base region arranged in sequence, the second conductive type base region It includes a raised portion at the center and a horizontal portion located at the periphery of the raised portion. The raised portion penetrates the first conductive type base area; a plurality of second conductive type base areas are arranged in the first conductive type base area. A conductive type short-circuit emission region, the first surface of the second conductivity type short-circuit emission region facing away from the first conductivity type conductive layer is not covered by the first conductivity type base region; provided in the second conductivity type short circuit At least one amplification gate on the first surface of the emission area, the plurality of second conductivity type short-circuit emission areas and the amplification gate are located within a preset range on the periphery of the protrusion; provided on the first conductivity type base The thyristor functional layer has a region facing away from the first surface of the first conductivity type conductive layer and the first surface of the first conductivity type conductive layer faces away from the second conductivity type base region.

Optionally, the first conductivity type base region includes: a first conductivity type lightly doped base region and a first conductivity type heavily doped base region arranged in sequence, and the plurality of second conductivity type short-circuit emitter regions are disposed in In the first conductivity type heavily doped base region, the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region are in contact or not in contact.

Optionally, the first surface of the raised portion facing away from the first conductive type conductive layer is not covered by the first conductive type base region, and the lateral width of the first surface of the raised portion is according to the The avalanche transition voltage of the gate commutated thyristor is determined.

Optionally, the first surface of the raised portion is provided with a protective layer.

Optionally, the radial width of the second conductivity type short-circuit emitter region, the number of the second conductivity type short-circuit emitter regions, and the distance between any two second conductivity type short-circuit emitter regions are determined according to the turn-on capability of the device. Sure.

Optionally, the preset range of the periphery of the protrusion includes a range with the center of the gate commutation thyristor as the center and a radius of less than or equal to 20 mm.

Optionally, the gate commutation thyristor further includes: a second conductivity type buffer layer disposed between the second conductivity type base region and the first conductivity type conductive layer.

Optionally, the second conductive type base region further includes: a recessed portion penetrating the first conductive type conductive layer, and the recessed portion is disposed within a preset range around the periphery of the protruding portion.

Optionally, the first conductive type conductive layer includes: a first conductive type heavily doped conductive layer and a first conductive type lightly doped conductive layer arranged in sequence.

Optionally, the thyristor functional layer includes: an anode disposed on a first surface of the first conductive type conductive layer facing away from the second conductive type base region; The gate electrode, the cathode and the second conductivity type emission area on the first surface of the first conductivity type conductive layer; the gate electrode, the cathode and the second conductivity type emission area are arranged on the periphery of the protrusion. Outside the preset range, the gate electrode and the second conductivity type emitter region are respectively in contact with the first surface of the first conductivity type base region, and the cathode is in contact with the second conductivity type emitter region.

The technical solution of the present invention has the following advantages:

The gate commutation thyristor provided by the embodiment of the present invention forms a PNP structure by forming a protruding portion penetrating the first conductive type base region from the second conductive type base region, thereby adjusting the dynamic avalanche occurrence position in the blocking state to the center. . Therefore, on the one hand, when the rated blocking voltage is exceeded, the thyristor is triggered to turn on again; on the other hand, a high-density current channel is formed in the center. If the blocking failure occurs, it will occur here first, ensuring that the gate When the commutation thyristor blocking failure fails, it will fail at the center of the chip and show a reliable short-circuit state, thereby solving the problem that the existing gate commutation thyristor blocking state will show a blocking state when the table terminal fails. At the same time, this structural design will not occupy the effective utilization area of the thyristor, so it will not reduce the on-state, turn-off and other characteristics of the thyristor. In addition, the gate-commutated thyristor structure is easy to process integration, has high chip area utilization, and has a more reliable short-circuit failure mode.

When the gate commutation thyristor provided by the embodiment of the present invention is applied to a reverse resistance gate commutation thyristor, the recessed portion penetrating the first conductivity type conductive layer is formed from the second conductivity type base region, thereby improving the reverse resistance gate. High temperature blocking characteristics of extremely commutated thyristors.

Description of the drawings

In order to more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort.

Figure 1 is a schematic structural diagram of a gate commutated thyristor in an embodiment of the present invention;

Figure 2 is a schematic structural diagram of a gate commutated thyristor in another embodiment of the present invention;

Figure 3 is a schematic structural diagram of a gate commutated thyristor in another embodiment of the present invention;

Figure 4 is a schematic top view of the BOD area in the embodiment of the present invention;

Figure 5 is a schematic top view of the BOD area in another embodiment of the present invention;

Figure 6 is a schematic structural diagram of a gate commutated thyristor in the prior art;

Figure 7 is a schematic top view of the cathode surface of a gate commutated thyristor in the prior art;

Figure 8 is a schematic structural diagram of a gate-commutated thyristor that is a reverse-resistance gate-commutated thyristor in an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a reverse-blocking gate-commutated thyristor in another embodiment of the present invention.

Detailed ways

The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations of the invention. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary; it can also be an internal connection between two components; it can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Example 1

An embodiment of the present invention provides a gate commutation thyristor, as shown in Figure 1, including: a first conductivity type conductive layer 1, a second conductivity type base region 2, and a first conductivity type base region 3 arranged in sequence. The second conductive type base area 2 includes a raised portion 21 in the center and a horizontal portion 22 located on the periphery of the raised portion 21. The raised portion 21 penetrates the first conductive type base area 3; At least one second conductivity type short-circuit emitter region 4 in the first conductivity type base region 3, the first surface of the second conductivity type short-circuit emitter region 4 facing away from the first conductivity type conductive layer 1 is not covered by the first conductivity type conductive layer 1. A conductive type base region 3 covers; at least one amplification gate 5 arranged on the first surface of the second conductivity type short-circuit emitter region 4, the at least one second conductivity type short-circuit emitter region 4 and the amplification gate 5 Located within a preset range on the periphery of the protruding portion 21; disposed on the first surface of the first conductive type base region 3 facing away from the first conductive type conductive layer 1 and behind the first conductive type conductive layer 1 A thyristor functional layer on the first surface of the second conductivity type base region 2 .

The first conductivity type may be a P-type semiconductor, and the second conductivity type may be an N-type semiconductor; or the first conductivity type may be an N-type semiconductor, and the second conductivity type may be a P-type semiconductor. In the following embodiments, the first conductivity type is a P-type semiconductor and the second conductivity type is an N-type semiconductor.

Specifically, the protruding portion formed by the second conductive type base region and the first conductive type base regions on both sides constitute a PNP structure. That is equivalent to a BOD (Break Over Diode) connected in parallel at the center of the gate commutated thyristor. At the same time, the PNP structure, the second conductivity type short-circuit emitter area and the amplification gate jointly form a high-density current channel, thereby adjusting the dynamic avalanche occurrence position to the center during the blocking state. When the thyristor fails to block, it will eventually It occurs here first to ensure that when the gate commutation thyristor fails to block, it will fail in the center and be in a reliable short-circuit state. In addition, when a dynamic avalanche occurs at the central PNP structure, the avalanche current flows laterally through the amplified gate and reaches the gate of the thyristor functional layer, thereby triggering the gate commutation thyristor, thus playing a role in voltage protection. In addition, it should be noted that multiple GCT functional areas can be set, that is, multiple GCT functional areas are set outside the BOD area, that is, GCT functional areas are continued to be set outside the GCT functional area in the current figure 1, or in other words, the BOD area is Multiple GCT and multiple functional areas are set up in sequence on the periphery. Each functional area has the same function, and the layered structures of multiple functional areas and BOD areas can be formed at the same time. In addition, it should be noted that the gate-commutated thyristor can also be called a gate-commutated thyristor chip (hereinafter referred to as the chip).

The gate commutation thyristor provided by the embodiment of the present invention forms a PNP structure by forming a protruding portion penetrating the first conductive type base region from the second conductive type base region, thereby adjusting the dynamic avalanche occurrence position in the blocking state to the center. . Therefore, on the one hand, when the rated blocking voltage is exceeded, the thyristor is triggered to turn on again; on the other hand, a high-density current channel is formed in the center. If the blocking failure occurs, it will occur here first, ensuring that the gate When the commutation thyristor blocking failure fails, it will fail at the center of the chip and show a reliable short-circuit state, thereby solving the problem that the existing gate commutation thyristor blocking state will show a blocking state when the table terminal fails. At the same time, this structural design will not occupy the effective utilization area of the thyristor, so it will not reduce the on-state, turn-off and other characteristics of the thyristor. In addition, the gate-commutated thyristor structure is easy to process integration, has high chip area utilization, and has a more reliable short-circuit failure mode.

In one embodiment, as shown in FIG. 1 , the first conductive type base region 3 includes: a first conductive type lightly doped base region and a first conductive type heavily doped base region, and the at least one The second conductivity type short-circuit emitter region is disposed in the first conductivity type heavily doped base region, and the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region are in contact or not in contact. Wherein, when the first conductive type lightly doped base region is in contact with the first conductive type short-circuit emitter region, the first conductive type lightly doped base region may be arranged in a polygonal shape, a round spot shape or a circular ring shape.

It should be noted that when the second conductivity type short-circuit emitter region is connected to the first conductivity type heavily doped base region, or is connected to the first conductivity type lightly doped base region and the first conductivity type heavily doped base region, a The short-circuited PN junction is caused by the transverse flow of current, causing the short-circuited PN junction to be in forward amplification, and then through the amplified gate structure, the avalanche current is amplified.

Among them, the radial width ΔR _n of the second conductivity type short-circuit emission region, the number n of the second conductivity type short-circuit emission region, and the distance between any two second conductivity type short-circuit emission regions L _{n-(n -1)} It can realize the regulation of the current amplification coefficient of the amplified gate, which can be determined according to the turn-on capability of the device. The second conductivity type short-circuit emitter region is located on the same surface as the cathode in the thyristor functional layer, and the second conductivity type short-circuit emitter region is a circular, spot-shaped or polygonal structure. In addition, the second conductivity type short-circuit emitter region forms a short-circuit connection through the amplification electrode with the first conductivity type lightly doped base region and the first conductivity type heavily doped base region outside, wherein the amplification gate and the second conductivity type are connected by controlling the amplification gate and the first conductivity type heavily doped base region. The width of the contact surface of the short-circuit emission area, that is, the short-circuit connection distance, can change the turn-on ability of the gate commutated thyristor.

Specifically, as shown in Figure 1, it is a schematic structural diagram in which the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region are not in contact. Figures 2 and 3 are the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region. Schematic diagram of the structure of the two-conductivity-type short-circuit emitter area contact. As shown in Figure 4, when the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region are in contact, the first surface of the protrusion is circular and the second conductivity type short-circuit emitter region is circular. Structural diagram, that is, a top view of the corresponding structure in Figure 2. As shown in Figure 5, when the first conductivity type lightly doped base region and the second conductivity type short-circuit emitter region are in contact, the first surface of the protrusion is circular and the second conductivity type short-circuit emitter region is circular spot-shaped. Structural diagram, that is, a top view of the corresponding structure in Figure 3.

In one embodiment, the first surface of the raised portion facing away from the first conductive type conductive layer is not covered by the first conductive type base region, and the lateral width of the first surface of the raised portion is according to The avalanche breakover voltage of the gate commutated thyristor is determined. The first surface of the raised portion is provided with a protective layer. Specifically, as shown in Figure 1, the first surface of the protrusion is exposed outside the first conductive type base region, and the lateral width W of the first surface of the protrusion, that is, the lateral width of the top of the PNP structure, depends on the avalanche breakover voltage V _BOD . That is, the BOD protection voltage value can be determined by designing the lateral width and length of the top of the PNP structure. In addition, designing a protective layer 10 on the first surface of the protrusion can achieve passivation protection of the protrusion. The protective layer can be an oxide layer or other passivation layer and other structures.

In one embodiment, the existing gate commutated thyristor structure is shown in Figures 6 and 7. In this structure, viewed from the lateral direction, there are many "strip cathodes" arranged in a radial pattern. Usually these "Strip cathode" is called cathode comb. The cathode comb strips are evenly arranged in a wafer using sector arcs or circles. According to the size of the GCT turn-off current, the GCT gate lead-out part is arranged in the center of the wafer, which is called the center gate, or it is arranged in the center or periphery of the wafer, which is called the middle ring gate or edge ring gate. At the edge terminal of the chip, a mesa design is used, and passivation material is used to protect the terminal surface to ensure the chip's blocking capability. The structure adopted in the embodiment of the present invention can be designed on the basis of the existing structure. Without affecting other parameters of the chip, the table design and cathode comb arrangement are kept unchanged, as shown in Figure 1. The preset peripheral range of the gate commutated thyristor includes a range with the center of the convex portion as the center and a radius R less than or equal to 20mm. The radius can be determined according to actual needs, such as 4mm, 5mm, 10mm, 15mm or 20mm, etc. That is, the preset range around the convex portion serves as the BOD area of the gate commutated thyristor.

In one embodiment, as shown in FIG. 1 , the gate commutation thyristor further includes: a second conductivity type buffer layer disposed between the second conductivity type base region 2 and the first conductivity type conductive layer 1 11. The thyristor functional layer includes: an anode 6 disposed on a first surface of the first conductive type conductive layer 1 facing away from the second conductive type base region 2 and an anode 6 disposed on a first surface facing away from the first conductive type base region 3 The gate electrode 7, the cathode 8 and the second conductivity type emission area 9 on the first surface of the first conductivity type conductive layer 1; the gate electrode 7, the cathode 8 and the second conductivity type emission area 9 are provided Outside the preset range of the periphery of the protrusion, the gate electrode 7 and the second conductive type emitter region 9 are in contact with the first surface of the first conductive type base region 3 respectively, and the cathode 8 and the The second conductivity type emitter area 9 is in contact.

In one embodiment, as shown in Figure 2, the gate commutation thyristor includes an N ⁺ short-circuit emitter region, which is the second conductivity type short-circuit emitter region, and a P ⁺ base region, which is the first conductivity type heavily doped region, in order from cathode to anode. The base region, the P base region is the first conductivity type lightly doped base region, the N ^- base region is the second conductivity type base region, the N′ buffer layer is the second conductivity type buffer zone and the P ⁺ transparent emitting anode is the first conductivity type Type conductive layer. A voltage protection zone (BOD zone) is formed at the center through the bulge of the N ^- base region, which is a PNP structure designed on the cathode surface. The BOD zone includes an N ⁺ short-circuit emitter region, a P ⁺ base region, a P base region, and an ^N- The base area, N' buffer layer and P ⁺ transparent emitter anode are all formed at the same time as the thyristor layer structures outside the BOD area. The N ⁺ short-circuit emitter area is connected to the P+ base area or the P base area by a short-circuit connection through the amplification gate, forming Multi-stage amplification gate. Secondly, the bulge of the N ^- base region and the P ⁺ base region and P-base region on both sides form a PNP BOD structure.

Among them, the doping concentration of the P ⁺ transparent anode emitter region is 1E17cm ^-3 ~ 1E18cm ^-3 , and the diffusion depth is about 0.2μm ~ 5μm. The doping concentration of the P ⁺ base region is 1E15cm ^-3 ~ 1E18cm ^-3 , and the diffusion depth is about 40μm ~ 100μm. The doping concentration of the P base region is 1E14cm ^-3 ~ 2E16cm ^-3 . The diffusion junction depth is usually designed according to the blocking voltage, which is about 50μm to 200μm. The doping concentration of the N ⁺ short-circuit emitter region is 1E19 cm ^-3 ~ 1E21cm ^-3 , and the diffusion depth is about 5 μm ~ 40 μm. The gate digging depth is about 0μm~40μm. The doping concentration of the N ^' buffer layer is 1E15 cm ^-3 ~ 1E17cm ^-3 , and the diffusion depth is about 20 μm ~ 90 μm, depending on the compromise adjustment design between chip blocking, on-state and off characteristics. The doping concentration of the N ^- base region and its base region width depend on the blocking voltage level.

Example 2

An embodiment of the present invention provides a gate commutated thyristor. As shown in Figure 8, the gate commutated thyristor is a reverse-resistance gate commutated thyristor and includes: a first conductive type conductive layer 1, a second conductive type conductive layer 1, and a second conductive type conductive layer 1. Type base area 2 and a first conductive type base area 3. The second conductive type base area 2 includes a raised portion 21 in the center and a horizontal portion 22 located on the periphery of the raised portion 21. The raised portion 21 Penetrating the first conductivity type base region 3; at least one second conductivity type short-circuit emitter region 4 is provided in the first conductivity type base region 3, and the second conductivity type short-circuit emitter region 4 faces away from the first conductivity type base region 3. The first surface of a conductive type conductive layer 1 is not covered by the first conductive type base region 3; at least one amplification gate 5 is provided on the first surface of the second conductive type short-circuit emitter region 4, and the at least one The second conductivity type short-circuit emitter region 4 and the amplification gate 5 are located within a preset range on the periphery of the protrusion 21; they are arranged on the first conductivity type base region 3 facing away from the first conductivity type conductive layer 1 The first surface of the first conductive type conductive layer 1 faces away from the thyristor functional layer of the first surface of the second conductive type base region 2 . The second conductive type base region 2 also includes: a recessed portion 23 that penetrates the first conductive type conductive layer 1 and is disposed within a preset range around the protruding portion 21 . At this time, the first conductivity type conductive layer 1 includes: a first conductivity type heavily doped conductive layer, that is, a P ⁺ anode region, and a first conductivity type, a lightly doped conductive layer, that is, a P + anode region.

As shown in FIG. 8 , the thyristor functional layer includes: an anode 6 disposed on the first surface of the first conductive type conductive layer 1 facing away from the second conductive type base region 2 and an anode 6 disposed on the first conductive type conductive layer 1 . Type base region 3 faces away from the gate electrode 7, cathode 8 and second conductivity type emitter region 9 on the first surface of the first conductivity type conductive layer 1; the gate electrode 7, the cathode 8 and the second conductivity type emitter region The conductive type emission region 9 is arranged outside the preset range on the periphery of the protrusion, and the gate 7 and the second conductivity type emission region 9 are respectively in contact with the first surface of the first conductivity type base region 3, so The cathode 8 is in contact with the second conductivity type emitter region 9 .

The first conductivity type may be a P-type semiconductor, and the second conductivity type may be an N-type semiconductor; or the first conductivity type may be an N-type semiconductor, and the second conductivity type may be a P-type semiconductor. In the following embodiments, the first conductivity type is a P-type semiconductor and the second conductivity type is an N-type semiconductor.

Specifically, the recessed portion 23 is formed below the amplification gate 5. After the recessed portion 23 penetrates the first conductive type conductive layer 1, the recessed portion 23 contacts the anode 6 with the first surface facing away from the first conductive type base region 3, forming A short-circuit connection between the base region 2 of the second conductivity type and the anode 6 . At the same time, the recessed portion 23 and the first conductive type conductive layer 1 on both sides form an anode PNP short-circuit isolation structure. The first surface of the recessed portion 23 may be annular, polygonal or circular. The lateral width of the first surface of the recessed portion 23, that is, the lateral width of the anode top of the second conductive type base region 2, depends on the reverse avalanche transition voltage and the anode injection efficiency.

When the gate commutation thyristor provided by the embodiment of the present invention is applied to a reverse resistance gate commutation thyristor, the recessed portion penetrating the first conductivity type conductive layer is formed from the second conductivity type base region, thereby improving the reverse resistance gate. High temperature blocking characteristics of extremely commutated thyristors.

In one embodiment, as shown in Figure 9, the gate commutation thyristor includes an N ⁺ short-circuit emitter region, which is the second conductivity type short-circuit emitter region, and a P ⁺ base region, which is the first conductivity type heavily doped region, in order from cathode to anode. The base region, the P base region is the first conductivity type lightly doped base region, the N ^- base region is the second conductivity type base region, the P anode region is the first conductivity type lightly doped conductive layer and the P ⁺ anode region is the first Conductive type heavily doped conductive layer. A voltage protection zone (BOD zone) is formed at the center through the bulge of the N ^- base region, which is a PNP structure designed on the cathode surface. The BOD zone includes an N ⁺ short-circuit emitter region, a P ⁺ base region, a P base region, and an ^N- The base area, P anode area and P ⁺ anode area are all formed at the same time as the thyristor layer structures outside the BOD area. The N ⁺ short-circuit emitter area is connected to the P ⁺ base area or the P base area by a short circuit through the amplification gate, forming multiple amplifier gate. Secondly, the bulge of the N ^- base region and the P ⁺ base region and P-base region on both sides form a PNP BOD structure. At the same time, an anode PNP short-circuit isolation structure formed by a recessed portion and first conductive type conductive layers on both sides is provided below the gate.

Among them, the doping concentration of the P anode region is 1E14cm ^-3 ~ 2E16cm ^-3 , and the diffusion junction depth is usually designed according to the blocking voltage, which is about 50μm to 200μm. The doping concentration of the P ⁺ anode region is 1E15cm ^-3 ~ 1E18cm ^-3 , and the diffusion depth is about 40μm ~ 100μm, depending on the compromise adjustment design between reverse blocking, pass-state and reverse recovery characteristics. The doping concentration of the P ⁺ base region is 1E15cm ^-3 ~ 1E18cm ^-3 , and the diffusion depth is about 40μm ~ 100μm. The doping concentration of the P base region is 1E14 cm ^-3 ~ 2E16cm ^-3 . The diffusion junction depth is usually designed based on the blocking voltage, which is about 50 μm ~ 200 μm. The doping concentration of the N ⁺ short-circuit emitter region is 1E19 cm ^-3 ~ 1E21cm ^-3 , and the diffusion depth is about 5 μm ~ 40 μm. The gate digging depth is about 0μm~40μm. The doping concentration of the N ^- base region and its base region width depend on the blocking voltage level.

It should be noted that in this embodiment, the structural design of the protruding portion and the second conductivity type short-circuit emission region refers to the corresponding structural design of Embodiment 1, and will not be described again here.

Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions and modifications to these embodiments without departing from the spirit of the invention and the scope of protection defined by the appended claims. Such modifications and variations are within the scope defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the application scope of the present invention is not limited to the process, mechanism, manufacture, material composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that there are processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, which perform the same functions as the present invention. Corresponding embodiments are described that function substantially the same or achieve substantially the same results, and may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufactures, material compositions, means, methods or steps within the scope of protection thereof.

Claims (10)

1. A gate commutated thyristor, comprising:

the semiconductor device comprises a first conductive type conductive layer, a second conductive type base region and a first conductive type base region which are sequentially arranged, wherein the second conductive type base region comprises a convex part positioned at the center and a horizontal part positioned at the periphery of the convex part, and the convex part penetrates through the first conductive type base region;

a plurality of second conductivity type short circuit emitter regions disposed within the first conductivity type base region, a first surface of the second conductivity type short circuit emitter regions facing away from the first conductivity type conductive layer being uncovered by the first conductivity type base region;

the amplifying gates are arranged on the first surface of the second conductivity type short-circuit emission area, and the plurality of second conductivity type short-circuit emission areas and the amplifying gates are located in the periphery preset range of the protruding part;

and the thyristor functional layer is arranged on the first surface of the first conductive type base region, which is opposite to the first conductive type conductive layer, and the first surface of the first conductive type conductive layer, which is opposite to the second conductive type base region.

2. The gate commutated thyristor of claim 1, wherein the first conductivity type base region comprises: the first conductive type lightly doped base region and the first conductive type heavily doped base region are sequentially arranged, the plurality of second conductive type short circuit emitter regions are arranged in the first conductive type heavily doped base region, and the first conductive type lightly doped base region and the second conductive type short circuit emitter regions are in contact or not in contact.

3. The gate commutated thyristor of claim 1, wherein a first surface of the raised portion facing away from the first conductivity type conductive layer is uncovered by the first conductivity type base region, and wherein a lateral width of the first surface of the raised portion is determined from an avalanche breakover voltage of the gate commutated thyristor.

4. A gate commutated thyristor according to claim 3, wherein the first surface of the protruding portion is provided with a protective layer.

5. The gate commutated thyristor of claim 1, wherein the radial width of the second conductivity type short-circuited emitter regions, the number of second conductivity type short-circuited emitter regions, and the distance between any two second conductivity type short-circuited emitter regions are determined according to the turn-on capability of the device.

6. The gate commutated thyristor of claim 1, wherein the predetermined range of the periphery of the boss comprises a range of 20mm or less in radius with the center of the gate commutated thyristor as the center of the circle.

7. The gate commutated thyristor of any one of claims 1-6, further comprising: and a second conductivity type buffer layer disposed between the second conductivity type base region and the first conductivity type conductive layer.

8. The gate commutated thyristor of claim 1, wherein the second conductivity type base region further comprises: and the concave part penetrates through the first conductive type conductive layer, and is arranged in a preset range of the periphery of the convex part.

9. The gate commutated thyristor of claim 8, wherein the first conductivity type conductive layer comprises: the first conductive type heavily doped conductive layer and the first conductive type lightly doped conductive layer are sequentially arranged.

10. The gate commutated thyristor of any one of claims 1-9, wherein the thyristor functional layer comprises: an anode arranged on a first surface of the first conductive type conductive layer opposite to the second conductive type base region, and a gate electrode, a cathode and a second conductive type emitter arranged on a first surface of the first conductive type base region opposite to the first conductive type conductive layer;

the gate electrode, the cathode and the second conductive type emitter region are arranged outside the preset range of the periphery of the protruding portion, the gate electrode and the second conductive type emitter region are respectively contacted with the first surface of the first conductive type base region, and the cathode is contacted with the second conductive type emitter region.