CN116803550B - Test assembly method and device for on-chip system - Google Patents

Abstract

The invention discloses a test assembly method and device for a system on a chip, and belongs to the technical field of integrated circuits. The power supply testing device comprises a PCB, a power supply module, a test probe and a debugging interface module, wherein the power supply module, the test probe and the debugging interface module are loaded on the PCB, and independent power supply rails are distributed for all voltage domains in a single heterogeneous processing unit, so that the working state of each core particle and each voltage domain can be monitored. The invention also provides a method for testing and assembling the system on a crystal by using the power supply testing device, which is used for gradually detecting whether the core particle in each heterogeneous unit in the system is normal or not in the assembling process of the system on the crystal, and cutting off the power supply path of the failed core particle so that the power supply path of the failed core particle does not consume the electric energy of the system on the crystal and does not influence the normal work of other core particles. The invention can find possible faults and failure problems of the system on a crystal in step-by-step assembly in advance, process the faults and failure circuits and provide guarantee for reliable and stable operation of the system on a crystal after assembly.

Description

A test assembly method and device for on-chip systems

Technical field

The invention relates to the technical field of integrated circuits, and in particular to a test assembly method and device for on-chip systems.

Background technique

As the demand for processor computing power continues to increase in general computing, supercomputing and intelligent computing, a single processor can no longer meet large-scale data processing application scenarios. As a result, wafer-level processors have been re-proposed with their extremely high interconnect bandwidth and computing power density. By integrating multiple homogeneous or heterogeneous processor cores on a large-size wafer or similar high-speed media On the computer, each chip is interconnected by a high-speed bus, thereby realizing an ultra-large-scale processor cluster.

On-wafer systems generally include components such as heat dissipation devices, wafer-level processors composed of a large number of die and silicon substrates, wafer connectors containing a large number of micro elastic connectors, high-density power supply units, high-density external high-speed connectors, etc. They are combined to form a high-density computing processing system.

For on-wafer systems made of silicon substrates, because the silicon substrate contains a large number of TSVs, and the TSV length can reach up to about 100um according to the current process, the silicon substrate needs to be thinned to a thickness of about 100um, and thinning will cause The silicon substrate warps and has low toughness, which may result in poor contact or even open circuits in the interconnect between the silicon substrate and the elastomeric connector in the wafer connector. At the same time, when the on-wafer system is working, the thermal expansion coefficient mismatch problem will cause the connection contacts between the wafer-level processor, the wafer connector, and the on-wafer system power supply device to shift, causing some connections to be disconnected or even short-circuited. In addition, the heterogeneous processing units in on-chip systems contain multiple cores of different types and processes and use many voltage domains. In order to achieve high-density power supply, some cores and heterogeneous processing units need to share a power rail. , a short circuit of part of the circuit in a chip will cause the chips in the entire shared power rail to fail to work properly, and may burn out its corresponding power supply module.

Therefore, it is necessary to continuously test and evaluate the status of each step during the on-wafer system packaging and assembly process, so as to promptly detect failed cores and avoid affecting the work of other cores.

On-chip systems feature high integration and high density. Among them, the power supply and heat dissipation density is generally ≥0.3W/mm ^2. After the wafer-level processor, wafer connector, and power supply unit are aligned and fixed in the system, there is not enough space to provide power supply network and signal for each core particle. The connection and disconnection test of the path requires a method and device to test the functional performance of the heterogeneous processing units and each core in the system without destroying the existing structure of the on-chip system.

At present, the industry and academia have mature testing methods, processes and corresponding equipment and instruments for chips, but there are no corresponding testing methods, processes and devices for on-chip systems. The large size, high integration level, high structural complexity, high warpage and other characteristics of on-chip systems make chip testing methods and methods unsuitable for on-chip systems. Therefore, a set of testing methods, processes and devices for on-chip systems is needed. During the assembly process of the on-chip system, each installation link can be tested, and the failed cores in this link can be processed and counted so that the failures can be reported. Minimize the impact and analyze the cause of failure.

Contents of the invention

The purpose of the present invention is to provide a testing method and device for conducting on-off testing of the power supply network and signal paths for heterogeneous processing units and each core in an on-chip system. During the assembly process of the on-chip system, each chip can be tested. Test each installation link to gradually screen out failed core particles to avoid the impact of failed core particles.

In order to achieve the above objects, the present invention adopts the following technical solutions:

The invention provides a power supply testing device for an on-wafer system. The on-wafer system includes a wafer-level processor, a wafer connector, and an on-wafer system power supply unit. The wafer-level processor includes a silicon substrate and an assembly. Several heterogeneous processing units on the silicon substrate; the wafer connector includes an elastic connector for connecting the round-level processor and the power supply unit and a matching rigid support structure; the on-wafer system power supply unit is composed of It is composed of multiple PCB carrier boards (printed circuit boards) equipped with voltage conversion modules (VRM) and supporting structural parts. The upper PCB carrier board and the assembled VRM are mainly responsible for transforming the input high voltage to an intermediate voltage; The middle PCB carrier board and the assembled VRM are mainly responsible for converting the intermediate voltage into the core voltage and IO voltage required by the heterogeneous processing unit; the back of the bottom PCB carrier board has a PAD that is connected to the elastic connector in the wafer connector. The carrier board There are high-frequency decoupling capacitors formed by buried capacitance processing inside, and the front side includes welded mid-frequency decoupling capacitors and PAD connected to the middle PCB carrier board.

The power supply test device includes a PCB board and a power supply module, a test probe and a debugging interface module mounted on the PCB board,

The power supply module includes a power rail that independently supplies power to each voltage domain in the heterogeneous processing unit and a debugging test circuit for monitoring the power supply parameters of each voltage domain;

The test probe is connected to the power supply module and the debugging interface module, and is used to interface with the PAD of a single heterogeneous processing unit, transmit power to the heterogeneous processing unit, and transmit the working parameter signal fed back by the configuration interface of the heterogeneous processing unit to the debugging interface module ;

The debugging interface module includes a micro control unit and a bus interface interconnected with the host computer. The micro control unit connects the power supply module and the configuration interface of the heterogeneous processing unit; the host computer controls the power output of the power supply module and monitors the power supply module and the heterogeneous processing unit. The signal fed back by the structural processing unit.

The PCB is provided with supporting circuits for connecting each module.

The power supply testing device provided by the present invention performs power supply testing on the system at the completion stage of assembly of the wafer-level processor, wafer connector and bottom PCB carrier board of the power supply unit during the on-chip system assembly process.

The power supply test device provided by the present invention integrates the power supply module, test probe and debugging interface module onto a whole PCB board. The size is not limited by the size of the heterogeneous processing unit. More power supply modules can be assembled. The PCB board carries All supporting circuits required for the operation and testing of a heterogeneous processing unit, allocate independent power rails and feedback loops to each voltage domain in a single heterogeneous processing unit, and realize the working status of each chip and its voltage domain Monitor.

The working principle of the power supply test device is as follows:

During the test, the test probe is connected to the PAD point on the bottom PCB carrier board of the power supply unit of the on-chip system under test, that is, the PAD is connected to a single heterogeneous processing unit. The power supply module converts the externally input high DC voltage into the power supply test device. The DC voltage and the core voltage required by the heterogeneous processing unit are supplied through test probes to each voltage domain in the heterogeneous processing unit. The micro control unit (MCU) of the debugging interface module is connected to the configuration interface of the power supply module and the heterogeneous processing unit (through the test probe). The management software of the host computer controls and monitors the working status of the power supply module and the heterogeneous processing unit. Specifically, the host computer sets the thresholds of the power supply parameters of each power rail in the power supply module, and saves the working parameter thresholds of the core particles in the machine. When the power supply module detects that the power supply parameters of a certain power rail exceed the set threshold, it is determined to be a fault, the power output of this power rail is turned off, and reported to the host computer; the host computer monitors the working parameters of each core in the heterogeneous processing unit in real time, and the host computer monitors the internally saved thresholds and the feedback results of the power supply module. Determine whether the working status of the heterogeneous processing unit is normal. If any abnormality is found, mark it as an abnormal core particle and heterogeneous processing unit.

Further, the power supply parameters monitored by the debugging test circuit in the power supply module include voltage, current, and temperature; the working parameters fed back by the configuration interface of the heterogeneous processing unit include the node temperature of the core particles, whether the external interface establishes a link, and whether the internal registers work normally. .

Further, the size of the PCB board is larger than the area of a single heterogeneous processing unit, and the power supply module is installed in the central area of the front of the PCB board; the debugging interface module is located on the periphery of the power supply module; and the test probe is located on the PCB board. On the back, it is connected to the power supply module and debugging interface module through the supporting circuit distributed on the PCB board.

Further, the power supply module also includes a power input interface, several voltage regulation modules (VRM) and filter capacitors. The power input interface is connected to an external power supply cable. The power input interface and the VRM module convert the high DC voltage into the DC voltage of the power supply test device and the core voltage required by the heterogeneous processing unit; the voltage adjustment module is in the heterogeneous processing unit. Each voltage domain is assigned an independent power rail; the filter capacitor is used to store and filter the voltage input and output of the voltage regulation module. The host computer is interconnected with the voltage regulation module through the configuration interface to control the enable/disable of the voltage regulation module, output voltage, threshold voltage/current/temperature, operating frequency, soft start mode, etc. The debugging and testing circuit inside the power supply module monitors the temperature, voltage, current and other parameters of each power rail, and feeds back the monitoring results to the host computer.

Further, the voltage regulation module is provided with heat sinks evenly distributed longitudinally on the side away from the PCB board. The voltage regulation module in the power supply test device provided by the present invention has a single-layer tiled layout, and the on-chip system has not yet completed the shell assembly during the test. The VRM is in a non-enclosed space, and the surrounding air can naturally convection. It is enough to set the heat sink and match the fan. Meet heat dissipation requirements.

Furthermore, the microcontrol unit is internally connected to the configuration interfaces of all cores of the heterogeneous processing unit and the power supply module in the form of a bus, and is externally connected to the host computer through an Ethernet interface.

Furthermore, the MCU connects the JTAG and IIC of the heterogeneous processing units through a bus, and monitors the node temperature of each core in the heterogeneous processing unit, whether the external interface is connected, and whether the internal registers are working normally. The MCU connects to the PMBus of the power supply module via a bus, sends power management signals (including enable/disable of power rails, parameters such as voltage, current and temperature thresholds), and monitors the voltage, current, temperature and other data of each power rail.

The present invention also provides a test assembly method for on-wafer systems, which includes the following steps:

(1) Bond several heterogeneous processing units to a silicon substrate to make a wafer-level processor, test each heterogeneous processing unit one by one according to the chip CP test process to see whether the function is normal, and mark the test results;

(2) Pull out the elastic connector corresponding to the failed heterogeneous processing unit or core particles in the wafer connector, or do not install the elastic connector corresponding to the failed heterogeneous processing unit or core particles during manufacturing; then remove the wafer The connector is assembled with the wafer-level processor, and the wafer-level processor is embedded in the heat sink;

(3) Install the underlying PCB carrier board and reinforcing ribs of the power supply unit on the wafer connector in sequence to obtain the on-wafer system to be tested, and use the power supply testing device to test the functions of the heterogeneous processing units in the on-wafer system to be tested one by one. Whether it is normal, screen out the failed core particles or isomeric processing units and mark them;

(4) Use the heat dissipation device and the power supply test device to conduct a bias high-temperature accelerated stress test on the system on the wafer to be tested, and screen out failed core particles or heterogeneous processing units and mark them;

(5) Remove the connector connected to the failed core die or heterogeneous processing unit from the middle PCB carrier board that is connected to the bottom PCB carrier board of the power supply unit, and then assemble the middle PCB carrier board with the bottom PCB carrier board until the entire crystal is completed. Assembly of the upper system.

In step (1), use the ATE test machine, probe card, probe station and other instruments and equipment in the chip CP test process to test whether the function of each heterogeneous processing unit of the wafer-level processor is normal.

For the failed heterogeneous processing unit or die detected in step (1), in step (2), pull out the elastic connector that connects and supplies power to it in the wafer connector, or do not install it during manufacturing. The elastic connector in this area cuts off the power supply path between the failed unit or core chip machine crystal oscillator and the power supply unit, so that it does not consume the power of the on-crystal system and does not affect the normal operation of other core chips.

Further, the test results of step (1) are judged. If the internal failed core function affects the operation of the entire heterogeneous processing unit, the elastic connection of the corresponding area of the failed processing unit in the wafer connector is The processor is removed (or not installed); if the failed core only affects part of the functions and performance of the entire heterogeneous processing unit, and the entire heterogeneous processing unit can still work, remove the core and its corresponding clock core. Flexible connector.

In step (3), the PAD on the back of the bottom PCB carrier board is aligned and connected to the elastic connector in the wafer connector, and the reinforcing rib is fixed and installed on the front of the bottom PCB carrier board through screws.

Further, the reinforcing ribs are made of rigid metal and are in the shape of a grid. Their edges are pressed against the edges of the heterogeneous processing units on the underlying PCB carrier board. The hollow area in the middle is the center corresponding area of each heterogeneous processing unit. Use Used for soldering decoupling capacitors and docking mid-layer PCB carrier boards. The intersection points of the stiffeners are fixed with the underlying PCB carrier board using screws to correct the warpage of the PCB carrier board and limit the thermal expansion of the PCB carrier board.

In steps (3)-(4), the test method of the power supply test device includes: setting the threshold values of the power supply parameters of each power rail of the heterogeneous processing unit through the software of the host computer to the power supply module of the power supply test device, and setting the working conditions of the core particles. The parameter thresholds are saved in the host computer; for the power supply module, if the power supply parameters of a certain power rail exceed the set threshold, it is determined to be a fault, the output of this power rail is directly turned off, and the status is reported to the host computer; the host computer real-time Monitor the working parameters of the core particles, and the host computer determines whether the working status of the core particles is normal based on the internally saved thresholds and the results fed back by the power supply module.

In step (3), the power supply test device is used to test the working status of the on-chip system under test under normal working environment. For the failed unit detected in step (1), skip testing.

In step (4), a bias voltage and high temperature are applied to the on-wafer system to perform an aging test. For the failed unit detected in step (3), the test is skipped.

Further, the high-temperature accelerated stress test includes: placing the on-chip system to be tested in a constant temperature box, turning on the heat dissipation device, and when the host computer monitors the internal temperatures of the core chips and power supply modules in the heterogeneous processing unit to reach the temperature to be measured, use the power supply test The device tests whether the function of each heterogeneous processing unit is normal one by one, and records the failed core particles.

Further, the temperature to be measured is 80~130°C.

Further, the bias accelerated stress test includes: controlling the output voltage of the power supply module of the power supply test device through the host computer, performing a pressurizing operation on each voltage domain of the heterogeneous processing unit, monitoring whether the heterogeneous processing unit is working normally, and recording failures. core particles.

Further, the voltage value applied by pressurization is the standard voltage value × 105% ~ the standard voltage value × 120%.

In step (5), for the core chips or heterogeneous processing units marked as failed in steps (3) and (4), remove the corresponding connectors in the middle PCB carrier board and cut off their power supply network-level signal transmission paths. . Then, the middle PCB carrier board for VRM assembly, the water cooling device, and the upper PCB carrier board for VRM assembly are assembled in sequence until the entire on-wafer system is assembled.

The invention has the following beneficial effects:

(1) The present invention provides a testing and assembly method for on-wafer systems, and tests, screens and processes the failed cores that may occur during the gradual assembly of various components of large-sized, high-complexity on-wafer systems. . The selected failed core particles will first be marked and counted for subsequent analysis of failure causes and program improvement. Then the power supply path of the failed core particle is disconnected, which saves electric energy and ensures that the failed core particle will not interfere with the normal operation of other core particles in the shared power supply unit.

The test assembly method of the present invention can be used to detect possible faults and failure problems in the on-chip system during step-by-step assembly in advance, and handle the faults and failed circuits, thereby ensuring reliable and stable operation of the on-chip system after assembly.

(2) The power supply test device provided by the present invention can conduct refined testing, monitoring and control for each independent heterogeneous processing unit in the on-chip system. Its size is not limited by the size of the heterogeneous processing unit, and it has the characteristics of simple structure, With the characteristics of convenient heat dissipation, powerful and complete functions, it can test the failure of heterogeneous processing units caused by warpage, alignment, thermal expansion coefficient mismatch and other issues during normal testing and aging tests during the on-wafer system assembly process.

Description of the drawings

Figure 1 is a schematic diagram of the overall structure of the on-chip system.

Figure 2 is a schematic diagram of the heterogeneous processing unit of the on-wafer system.

Figure 3 is a schematic diagram of the installation of stiffeners in the on-chip system.

Figure 4 is a schematic diagram of the power supply test device testing the on-wafer system.

Figure 5 is a schematic connection diagram of the debugging interface module in the power supply test device.

Figure 6 is a flow chart of steps for completing the present invention.

Figure 7 is a schematic diagram of the on-chip system CP test.

Explanation of labels in Figures 1 and 4: 1-water cooling structural parts, 2-heterogeneous processor unit (Die), 3-large size silicon substrate, 4-elastic connector, 5-wafer connector support structural parts , 6-The bottom PCB carrier board of the power supply unit, 7-Reinforcing ribs, 8-Intermediate frequency decoupling capacitor, 9-The inter-layer docking PAD of the power supply unit, 10-The middle PCB carrier board of the power supply unit, 11-VRM water-cooling structural parts, 12-Power supply Unit upper PCB carrier board, 13-power supply test device PCB board, 14-power supply test device power input interface, 15-power supply test device VRM module heat sink, 16-power supply test device debugging interface, 17-power supply test device filter capacitor, 18 - Elastic test probe of the power supply test device, 19 - Die or heterogeneous processing unit with failed bonding, 20 - Elastic connector area with poor contact, 21 - Remove the connector area between layers of the power supply unit.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. It should be noted that, as long as there is no conflict, the features in the following embodiments and implementation modes can be combined with each other.

FIG. 1 is a schematic structural diagram of an on-chip system provided by an embodiment of the present invention. As shown in Figure 1, the entire on-wafer system includes a water cooling structure 1, a wafer-level processor composed of a large-size silicon substrate 3 and multiple heterogeneous processor units (Dies) 2, and a rigid support structure 5 and A wafer connector composed of a large number of elastic connectors 4, an on-wafer system power supply unit and supporting structural parts formed by stacking multiple PCB boards.

Heterogeneous processor unit (Die) 2 is a heterogeneous processing unit, as shown in Figure 2, which includes CPU, GPU, DSA and other various acceleration engine cores, Router (routing core) and individual cores Matching MEMS clock core particles (clock area shown in the picture), these core particles "organically" constitute a new macro system (heterogeneous processing unit), whose size is smaller than the maximum photomask size. The entire system contains several identical heterogeneous processing units, which are responsible for completing the computing and processing tasks of the on-chip system.

Large-size silicon substrate 3, usually an 8-inch or 12-inch passive silicon substrate, with passive circuits such as metal wires and TSVs inside, is responsible for interconnecting routing cores, control signal extraction, and power/ground of each heterogeneous processing unit. bump merge and lead out.

The on-chip system power supply unit, as shown in Figure 1, is composed of multiple PCB boards equipped with VRMs and supporting structural parts. The upper PCB carrier board 12 and VRM1 are mainly responsible for transforming the input high voltage. to the intermediate voltage (such as 48VDC to 12VDC); VRM2/VRM3 on the middle PCB carrier board 10 is mainly responsible for converting the intermediate voltage into the core voltage and IO voltage required by the heterogeneous processing unit (such as 1.2VDC and 3.3VDC); for its The bottom PCB carrier board 6 has a PAD on the back that is connected to the elastic connector 4 in the wafer connector. The interior of the carrier board undergoes buried capacitance processing, that is, high dielectric constant material is filled between the power supply and the ground to form a high-frequency decoupling capacitor. , the front side contains the soldered intermediate frequency decoupling capacitor 8 and the PAD9 connected to the upper PCB carrier board.

The bottom PCB carrier board 6 of the power supply unit has problems of warping and thermal expansion due to its large size. Therefore, reinforcing ribs 7 are used to process the PCB carrier board. The reinforcing rib is made of rigid metal, as shown in Figure 3. Its shape is grid-like, and its edge is pressed against the edge of the heterogeneous processing unit on the PCB carrier board. The hollow area in the middle corresponds to the center of each heterogeneous processing unit. The area is used to weld the decoupling capacitor and connect to the upper power supply PCB carrier board 10. The intersection point of the reinforcing rib 7 is fixed with the bottom PCB carrier board 6 using screws to correct the warpage of the PCB carrier board 6 and limit the PCB at the same time. Thermal expansion of carrier plate 6.

The power supply PCB carrier board 10 connected to the bottom PCB carrier board 6 in the power supply unit has a VRM module that supplies power to all voltage domains of the heterogeneous processing unit welded on it, because each heterogeneous processing unit contains many various processes. , core chips with various functions have many voltage domains and require high power supply density (generally ≥0.3W/mm ² ). Mature modules on the market cannot meet high power supply density and multiple independent power rail outputs at the same time. Therefore, the slicing power supply method is used to divide the entire system into several identical power supply areas. Each area contains several heterogeneous processing units. The same voltage domain in each area shares the power rail of a VRM module. All power supply areas in each power supply area The XY-axis area of the power supply circuit is no larger than the area of its corresponding heterogeneous processing unit.

Because the VRM in the power supply unit of the on-chip system is in a relatively closed space, a PCB board will be installed above it for system management and power input, and then a shell of the on-chip system may be installed to protect the internal circuits and structures. Therefore, in the Water-cooling structural parts 11 and peripheral supporting water-cooling heat dissipation devices are added to VRM2 and VRM3, as shown in Figure 1.

Figure 4 is a schematic structural diagram of a power supply test device provided by an embodiment of the present invention. As shown in Figure 4, the power supply test device consists of a PCB board 13, a power input interface 14, multiple VRM modules and heat sinks 15, a debugging interface 16, a filter It is composed of capacitor 17 and elastic test probe 18.

The PCB board 13 of the power supply test device has an area larger than that of a single Die (heterogeneous processing unit). The size of the power supply unit of the on-chip system does not need to be limited by the size of a single Die as shown in Figure 1. In this way, the heterogeneous processing unit can be The power supply circuit and debugging test circuit fan out a larger area, thereby achieving more comprehensive functions.

The VRM module of the power supply test device contains various monitoring and control circuits such as temperature, voltage, and current. All VRMs required for a single heterogeneous processing unit are installed in the front center area of the PCB board 13 to minimize power supply. voltage drop in the network. Unlike the power supply unit in the on-chip system in Figure 1, which uses regionally shared power rails, the power supply test device uses more VRM modules to allocate independent power rails and feedback to each voltage domain in a single heterogeneous processing unit. loop, so that the voltage and current values of each voltage domain of the heterogeneous processing units can be individually controlled and monitored, thereby achieving more fine-grained power supply management.

The heat sink 15 of the power supply test device is in a single-layer tiled layout, and the on-chip system has not yet completed the shell assembly during the test. The VRM is in an unenclosed space, and the surrounding air can naturally convection, so only the heat sink is needed near the heat sink. A fan can meet the heat dissipation requirements, and there is no need to use a water cooling device to dissipate heat from the VRM like the on-chip system power supply unit in Figure 1.

The debugging interface 16 of the power supply test device uses an MCU to summarize the debugging interfaces of all cores in the heterogeneous processing unit and all VRMs on the power supply test device. It uses an Ethernet interface to connect to the host computer externally, and is controlled by the management software in the host computer. To monitor the status of heterogeneous processing units and VRMs, the signal lines of the debugging interface are basically low-speed signal lines with a long effective transmission distance, so they are laid out on the periphery of the PCB board 13 .

The filter capacitor 17 of the power supply test device is welded on the bottom of the PCB board 13 and is used to store energy and filter the voltage input and output of the VRM.

The elastic test probe 18 of the power supply test device is located at the bottom of the PCB board 13 of the power supply test device and is connected to the power and signal PAD at the bottom of the PCB board for docking with the PAD of a single heterogeneous processing unit and transmitting power and signals. The signal PAD transmits information such as the temperature of the core particles in the heterogeneous processing unit, interface link status, internal register working status and other information, and is used to test a single heterogeneous processing unit.

Example 1

The components of the on-chip system provided in this embodiment include: water cooling structural components, a number of heterogeneous processing units (Dies), silicon substrates, wafer connectors, on-chip system power supply units and supporting structural components.

Among them, the length and width of the water cooling structure are 400×400mm ² , and a 12-inch circular groove of the same size as the wafer-level processor is milled inside for placing the wafer-level processor.

Die is actually multiple cores, as shown in Figure 2. It contains CPU, DDR, GPU, DSA, Router (routing), and MEMS clock cores of each processing core. These cores form a heterogeneous processing unit ( That is, Die in Figure 1), these heterogeneous processing units are connected through SerDes in the routing core (Router) to form a 2D-Mesh high-speed on-chip network topology to achieve normalized high-speed communication. This heterogeneous processing unit The size is 24×24mm ² .

The silicon substrate is a 12-inch passive silicon substrate, on which a total of 64 sets of identical heterogeneous processing units in 8 rows and 8 columns are bonded.

The wafer connector has a size of 400×400mm ² and is installed on the water-cooling structure as shown in Figure 1, sealing the wafer processor in a sealed space.

The shared power supply unit in the power supply unit of the on-chip system uses a total of 2×2 heterogeneous processing units as one shared area, and the entire on-chip system is divided into 16 shared power supply areas.

For the above-mentioned on-chip system, the power supply test device provided in this embodiment has a PCB board size of 48×48mm ² and contains 3 VRMs and related circuits. The 12V input is converted into the core voltage of each core in the heterogeneous processing unit and IO voltage. As shown in Figure 5, the debugging interface module includes an MCU, which internally connects the JTAG, IIC and PMBus of the VRM of the heterogeneous processing units via a bus, and monitors the nodes of each core in the heterogeneous processing units through JTAG and IIC. Temperature, whether the external interface is connected, and whether the internal registers are working normally; monitor the voltage, current, temperature, etc. of each voltage rail in the VRM through PMBus, and can also send parameters such as enabling/disabling power rails, voltage/current/temperature thresholds, etc. The MCU uses a 100M Ethernet interface to connect to the host computer through a network cable.

The power supply test device contains the power rails of all voltage domains of a heterogeneous processing unit and summarizes the debugging test interfaces of all core chips and VRMs.

This embodiment provides a test and assembly method for the above-mentioned on-chip system. The process is shown in Figure 6. The specific steps are as follows:

S1. First test the wafer-level processor. The test bump of each die in the silicon substrate has been led out to the back of the silicon substrate through metal wires and TSVs. As shown in Figure 7, use a probe card, probe station, and ATE. The test machines cooperate with each other to detect the DFT signal and related test pins of each heterogeneous processing unit in the 12-inch silicon substrate, conduct functional and electrical parameter testing of a single heterogeneous processing unit, and repeat 64 times to complete the entire wafer-level processor test , the specific test steps are as follows:

① The probe station automatically transfers the wafer-level processor to the test position one by one, and the Pad points on the silicon substrate are connected to the functional module (probe card) of the test machine through the probe;

②The testing machine applies input signals to the chip and collects output signals to determine whether the function and performance of the core particles in the heterogeneous processing unit meet the design specification requirements under different working conditions;

③The test results are transmitted to the probe station through the communication interface, and the probe station marks the corresponding area of the core of each heterogeneous processing unit on the silicon substrate to form a map of the core of the wafer-level processor. .

S2. For the heterogeneous processing unit that failed in the test in the previous step, if its internal failed core function affects the operation of the entire heterogeneous processing unit, elastically connect the corresponding area of the failed processing unit in the wafer connector. The device is pulled out (or not installed). If the failed core only affects part of the functions and performance of the entire heterogeneous processing unit, but the entire heterogeneous processing unit can still work, remove the elastic connector corresponding to the core and its clock core. The wafer connector is then assembled.

Specifically, for the heterogeneous processing unit or core particle whose failure is detected in step S1, that is, the die or heterogeneous processing unit 19 with bonding failure in Figure 1, in step S2, the power supply to it in the wafer connector is The elastic connector is pulled out, or the elastic connector in this area is not installed during manufacturing, cutting off the power supply path between the failed unit or core machine crystal oscillator and the power supply module.

When assembling the wafer connector, first embed the wafer processor into the groove of the water cooling structure, use glue to fix the four sides of the wafer-level processor, and then assemble the wafer connector on the wafer-level processor superior.

S3. After installing the wafer connector, first install the bottom PCB carrier board of the power supply unit (size 400×400mm ² ), and then install the reinforcement ribs of the PCB carrier board. As shown in Figure 3, the reinforcement ribs are connected to the PCB carrier board through a large number of screws. The PCB carrier board is fixed to prevent the PCB carrier board from warping. After the installation is completed, use the above-mentioned power supply test device and precision manipulator to test the functions and performance of the effective heterogeneous processing units in the system one by one. If a failed unit detected in step 1 is encountered, skip the test.

Specifically, the power supply test device uses an MCU to aggregate the various debugging interfaces of the heterogeneous processing units and the PMBus interface of the VRM. As shown in Figure 5, it is connected to the host computer through the Ethernet interface. The software of the host computer first sets up the heterogeneous processing unit. The threshold values of parameters such as voltage, current, and temperature of each power rail are stored in the VRM, and the threshold values of the core chip temperature and other parameters are saved in the local machine.

During the test, the power supply test device is connected to the PAD 9 on the bottom PCB carrier board of the power supply unit of the on-wafer system under test through the test probe 18, and supplies power to each voltage domain of the heterogeneous processing unit. The host computer monitors the VRM and each core of the heterogeneous processing unit. Grain feedback.

For the VRM module, if the output voltage, output current and internal temperature of a certain power rail are monitored to exceed the set threshold, it is determined to be a fault, the output of the power rail is directly turned off, and the status is reported to the host computer; for heterogeneous The information in the processing unit is reported in real time to its internal temperature changes, whether the external interface is connected, whether the internal register is working normally, and other information; for the host computer, it is judged whether the working status of the core is normal based on the internally saved threshold and the feedback result of the VRM. If any abnormalities are found, they are marked as abnormal core particles and heterogeneous processing units.

S4. Use the heat dissipation device of the on-wafer system and the above-mentioned power supply test device to conduct a bias high-temperature accelerated stress test on the system assembled with the wafer-level processor and wafer connector. First, place the entire on-wafer system to be tested in a constant temperature box , control the temperature of the thermostat, and then control the flow rate of the coolant in the water-cooling device. Through monitoring by the host computer, the temperature of the core particles in the heterogeneous processing unit reaches the temperature to be measured (such as 125°C), and the power supply test device is used for the specified time. Test the function of each heterogeneous processing unit one by one; if a failed unit detected in step 3 is encountered, skip testing.

In the same way, use the host computer software to control the output voltage of each VRM (such as 105%, 110%, 115%, 120% of the core voltage) through Ethernet and PMBus, and conduct a fixed-duration voltage test. Marker bias and high temperature accelerate the screening out of failed cores or heterogeneous processing units.

S5. For the core chips or heterogeneous processing units marked as failed in step S4, as shown in Figure 1, remove the corresponding connector at the bottom of the power supply middle PCB carrier board 10, cut off its power supply network level signal transmission path, and then Assemble the power supply PCB carrier board 10 that carries VRM2/VRM2, the water-cooling structural component 11, and the upper power supply PCB carrier board 12 that mainly carries VRM1 until the entire power supply system is assembled.

Specifically, for the elastic connector area 20 where poor contact is detected in step S4, see FIG. 1, and in step S5, the connector area 21 between the power supply unit layers is removed.

This embodiment describes in detail the testing method after installation of the wafer-level processor, wafer connector, and power supply unit in the supra-wafer system, which can screen out failed cores in each link. A power supply test device for testing on-chip systems is introduced. It has more comprehensive debugging and testing functions than the power supply device actually installed in the on-chip system. It can provide independent power rails for all voltage domains of the core in each heterogeneous processing unit. Provides complete debugging methods for all core chips and VRMs of a single heterogeneous processing unit, which can be used to fine-tune testing of chip bonding process defects, 12-inch silicon substrate warpage, and power supply PCB carrier board warpage during the production and installation of on-chip systems. Core particle failure caused by problems such as warpage, thermal expansion coefficient mismatch, and poor contact of elastic connectors in wafer-level connectors.

In summary, the present invention provides a testing method, process and device for on-chip systems, which screen out failed cores through step-by-step installation and step-by-step testing. For failed cores, the power supply network is cut off. This method saves the power consumption of the system, avoids the impact of failed cores on the power supply network of other cores in the shared unit, and achieves fault isolation.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations within the spirit and principles of the present invention. Any modifications, equivalent substitutions, improvements, etc. shall be included in the protection scope of the present invention.

Claims (10)

1. The power supply testing device for the system on a wafer comprises a wafer level processor, a wafer connector and a power supply unit of the system on a wafer, wherein the wafer level processor comprises a silicon substrate and a plurality of heterogeneous processing units assembled on the silicon substrate; the wafer connector comprises an elastic connector for connecting the wafer level processor and the power supply unit and a rigid supporting structure matched with the elastic connector; the on-chip system power supply unit is formed by stacking and combining a plurality of PCB (printed circuit board) carrier boards provided with voltage conversion modules and matched structural members, wherein the upper PCB carrier boards and the voltage conversion modules are responsible for transforming input high voltage to intermediate voltage; the middle-layer PCB carrier board and the assembled voltage conversion module are responsible for converting the middle voltage into core voltage and IO voltage required by the heterogeneous processing unit; the back of the bottom PCB carrier plate is provided with a PAD which is in butt joint with an elastic connector in the wafer connector, the inside of the carrier plate is provided with a high-frequency decoupling capacitor formed by capacity burying treatment, and the front of the carrier plate comprises a welded medium-frequency decoupling capacitor and a PAD which is in butt joint with the middle PCB carrier plate; the power supply unit adopts a scribing power supply mode to divide the whole system into a plurality of identical power supply areas, each area comprises a plurality of heterogeneous processing units, the identical voltage domains in each area share a power rail of a voltage conversion module, the XY axis area of all power supply circuits in each power supply area is not larger than the area of the corresponding heterogeneous processing units, the power supply testing device is characterized by comprising a PCB board, a power supply module, a test probe and a debugging interface module which are loaded on the PCB board,

the power supply module comprises a power rail for independently supplying power to each voltage domain in the heterogeneous processing unit and a debugging and testing circuit for monitoring power supply parameters of each voltage domain;

the test probe is connected with the power supply module and the debugging interface module, and is used for docking with the PAD of the single heterogeneous processing unit, transmitting a power supply to the heterogeneous processing unit, and transmitting a working parameter signal fed back by the configuration interface of the heterogeneous processing unit to the debugging interface module;

the debugging interface module comprises a micro control unit and a bus interface which is interconnected with the upper computer, and the micro control unit is connected with the power supply module and the configuration interface of the heterogeneous processing unit; the upper computer controls the power output of the power supply module and monitors signals fed back by the power supply module and the heterogeneous processing unit.

2. The power supply testing device for a system on a chip of claim 1, wherein the power supply parameters monitored by the debug testing circuit in the power supply module include voltage, current, temperature; the working parameters fed back by the heterogeneous processing unit configuration interface comprise the node temperature of the core particle, whether a link is established between an external interface and whether the internal register works normally.

3. The power supply testing device for a system on a chip of claim 1, wherein the PCB board is sized larger than an area of a single heterogeneous processing unit, and the power supply module is mounted to a front center area of the PCB board; the debugging interface module is arranged at the periphery of the power supply module; the test probe is arranged on the back of the PCB and is connected with the power supply module and the debugging interface module through matched circuits distributed on the PCB.

4. The power test apparatus for a system on a chip of claim 1, wherein the power module further comprises a power input interface, a number of voltage regulation modules, and a filter capacitor.

5. The power supply testing device for a system on a chip of claim 4, wherein the voltage regulating modules are longitudinally and uniformly provided with cooling fins on a side surface far away from the PCB.

6. The power supply testing device for the on-chip system according to claim 1, wherein the micro control unit is connected with all the core grains of the heterogeneous processing unit and the configuration interface of the power supply module in a bus mode, and is connected with the upper computer through an Ethernet interface.

7. A test assembly method for a system on a chip, comprising the steps of:

(1) Bonding a plurality of heterogeneous processing units with a silicon substrate to obtain a wafer-level processor, testing whether the function of each heterogeneous processing unit is normal one by one according to a chip CP test flow, and marking a test result;

(2) Extracting the elastic connector corresponding to the failure heterogeneous processing unit or the core particle from the wafer connector, or not installing the elastic connector corresponding to the failure heterogeneous processing unit or the core particle during production and manufacture; then assembling the wafer connector and the wafer-level processor, wherein the wafer-level processor is embedded in the heat dissipation device;

(3) Sequentially installing a bottom layer PCB carrier plate and a reinforcing rib of a power supply unit on a wafer connector to obtain a system on a wafer to be tested, using the power supply testing device for the system on the wafer to be tested according to any one of claims 1-6 to test whether the functions of heterogeneous processing units in the system on the wafer to be tested are normal one by one, screening out invalid core particles or heterogeneous processing units and marking;

(4) Carrying out a biased high-temperature acceleration stress test on the system on the wafer to be tested by utilizing the heat dissipation device and the power supply test device, screening out failed core particles or heterogeneous processing units and marking;

(5) And removing the connector connected with the failure core particle or the heterogeneous processing unit from the middle-layer PCB carrier which is in butt joint with the bottom-layer PCB carrier of the power supply unit, and then assembling the middle-layer PCB carrier with the bottom-layer PCB carrier until the whole system on a crystal is assembled.

8. The method of assembling a test for a system on a chip according to claim 7, wherein in the step (2), the test result of the step (1) is judged, and if the internal failed core function affects the operation of the whole heterogeneous processing unit, the elastic connector of the corresponding area of the failed heterogeneous processing unit is extracted or not installed in the wafer connector; if the failed core particle only affects part of functions and performances of the whole heterogeneous processing unit, the whole heterogeneous processing unit can still work, and the elastic connector corresponding to the core particle and the clock core particle thereof is removed.

9. The test assembly method for a system on a chip according to claim 7, wherein in the steps (3) - (4), the test method of the power supply test device comprises: setting thresholds of power supply parameters of all power supply rails of the heterogeneous processing unit into a power supply module of a power supply testing device through software of an upper computer, and storing working parameter thresholds of core particles in the upper computer; for the power supply module, if the power supply parameter of a certain power supply rail is monitored to exceed a set threshold value, judging that the power supply rail is faulty, directly closing the output of the power supply rail, and reporting the state to the upper computer; the upper computer monitors working parameters of the core particles in real time, and judges whether the working state of the core particles is normal or not according to the threshold value stored in the upper computer and the feedback result of the power supply module.

10. The method of test assembly for a system on a chip of claim 7, wherein in step (4), the high temperature accelerated stress test comprises: placing a system on a crystal to be tested in an incubator, starting a heat dissipation device, and when the internal temperature of a core particle and a power supply module in the heterogeneous processing units monitored by an upper computer reaches the temperature to be tested, testing whether the function of each heterogeneous processing unit is normal one by using a power supply testing device; the temperature to be measured is 80-130 ℃;

the bias acceleration stress test includes: and controlling the output voltage of a power supply module of the power supply testing device through the upper computer, pressurizing each voltage domain of the heterogeneous processing unit, and monitoring whether the heterogeneous processing unit works normally or not, wherein the voltage value applied by pressurizing is a standard voltage value multiplied by 105% -a standard voltage value multiplied by 120%.