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CN116801617A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN116801617A
CN116801617A CN202310741243.XA CN202310741243A CN116801617A CN 116801617 A CN116801617 A CN 116801617A CN 202310741243 A CN202310741243 A CN 202310741243A CN 116801617 A CN116801617 A CN 116801617A
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China
Prior art keywords
layer
semiconductor
doping
word line
semiconductor doping
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Chinese (zh)
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孔令滔
王梓杰
汪治城
何家庆
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310741243.XA priority Critical patent/CN116801617A/en
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Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method of fabricating the same. The method comprises the following steps: providing a substrate, wherein a word line groove is formed in the substrate; forming a gate dielectric layer covering the word line groove along with the shape; forming a conductive layer which covers part of the gate dielectric layer and fills the bottom of the word line groove; forming a semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove; forming a protective layer which covers the semiconductor doping structure and fills the top of the word line groove; the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, and the performance of the semiconductor structure is improved.

Description

Semiconductor structure and preparation method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
Due to the high concentration doping of the drain, a lateral electric field near the drain is increased, resulting in GIDL (gate-induced drain leakage, gate induced drain leakage current). As the feature size of DRAM (Dynamic Random Access Memory ) shrinks, GIDL of memory transistors in DRAM increases, affecting the performance of the memory transistors, and controlling the threshold voltage of the memory transistors is required to improve the performance of the memory transistors.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can optimize gate-induced drain leakage current and threshold voltage.
The present disclosure provides a method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a word line groove is formed in the substrate;
forming a gate dielectric layer covering the word line groove along with the shape;
forming a conductive layer which covers part of the gate dielectric layer and fills the bottom of the word line groove;
forming a semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove;
forming a protective layer which covers the semiconductor doping structure and fills the top of the word line groove;
the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, wherein the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, and the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer.
In one embodiment, forming a semiconductor doping structure covering a portion of a sidewall of the gate dielectric layer and filling a middle portion of the word line trench includes:
forming a first semiconductor doping material layer covering the side wall of the gate dielectric layer and the top surface of the conductive layer along with the shape;
Etching back the first semiconductor doped material layer, and reserving the first semiconductor doped material layer on the side wall of the gate dielectric layer, which is close to the conductive layer, as a first semiconductor doped layer;
forming a second semiconductor doping material layer which covers the first semiconductor doping layer and fills the word line groove;
and etching back the second semiconductor doping material layer, and reserving the second doping material layer positioned in the middle of the word line groove as the second semiconductor doping layer.
In one embodiment, forming a second semiconductor doped material layer that covers the first semiconductor doped layer and fills the word line trench includes:
and forming a plurality of semiconductor doped material sublayers which are sequentially stacked, wherein the next semiconductor doped material sublayer covers the previous semiconductor doped material sublayer in a conformal manner, the doping concentration of the next semiconductor doped material sublayer is greater than that of the previous semiconductor doped material sublayer, and the first semiconductor doped material sublayer covers the top surfaces of the first semiconductor doped layer and the conductive layer in a conformal manner.
In one embodiment, the doping concentration of the second semiconductor doping layer increases gradually in a direction along the bottom of the word line trench toward the top of the word line trench and through the center of the top surface of the second semiconductor doping layer;
The doping concentration of the second semiconductor doping layer gradually decreases in a direction along the top center of the second semiconductor doping layer toward the top edge of the second semiconductor doping layer.
In one embodiment, forming a semiconductor doping structure covering a portion of a sidewall of the gate dielectric layer and filling a middle portion of the word line trench includes:
forming a third semiconductor doping material layer which covers the top surface of the first semiconductor doping layer and the top surface of the second semiconductor doping layer and fills the word line trench;
etching back the third semiconductor doping material layer, and reserving the third semiconductor doping material layer located on the top surface of the first semiconductor doping layer and the top surface of the second semiconductor doping layer as the third semiconductor doping layer;
the semiconductor doping structure further comprises a third semiconductor doping layer, and the doping concentration of the third semiconductor doping layer is greater than or equal to that of the first semiconductor doping layer.
In one embodiment, the substrate includes an active region, the wordline trench passes through the active region, and the method of fabricating the semiconductor structure further includes:
and doping the portions of the active region located on opposite sides of the word line trench to form source and drain regions, wherein the source and drain regions laterally overlap the semiconductor doping structure and the source and drain regions do not laterally overlap the conductive layer.
In one embodiment, forming a conductive layer that covers a portion of the gate dielectric layer and fills the bottom of the word line trench includes:
forming a diffusion barrier material layer covering the gate dielectric layer along with the shape;
forming a metal material layer which covers the diffusion barrier material layer and fills the word line trench;
etching back the metal material layer and the diffusion barrier material layer, and reserving the diffusion barrier material layer and the metal material layer which are positioned at the bottom of the word line trench as a diffusion barrier layer and a metal layer respectively;
wherein the conductive layer comprises a diffusion barrier layer and a metal layer.
The preparation method of the semiconductor structure comprises the steps of forming a semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle of the word line groove, wherein the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, compared with the mode that the middle of the word line groove is only filled with the first semiconductor doping layer, the first semiconductor doping layer which covers part of the side wall of the gate dielectric layer in the semiconductor doping structure enables the gate induced drain leakage current of the semiconductor structure to be kept unchanged, meanwhile, the doping concentration of the second semiconductor doping layer in the semiconductor doping structure is smaller than that of the first semiconductor doping layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and the top surface of the conducting layer, threshold voltage of the semiconductor structure is increased, and performance of the semiconductor structure (buried transistor) is improved.
The present disclosure also provides a semiconductor structure comprising:
a substrate in which a word line trench is formed;
a gate dielectric layer covering the word line trench in a conformal manner;
the conducting layer covers part of the gate dielectric layer and fills the bottom of the word line groove;
the semiconductor doping structure covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove;
a protective layer covering the semiconductor doping structure and filling the top of the word line trench;
the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, wherein the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, and the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer.
In one embodiment, the doping concentration of the second semiconductor doping layer is gradually increased in a direction along the bottom of the word line trench toward the top of the word line trench and passing through the center of the top surface of the second semiconductor doping layer;
the doping concentration of the second semiconductor doping layer gradually decreases in a direction along the top center of the second semiconductor doping layer, which refers to the top edge of the second semiconductor doping layer.
In one embodiment, the semiconductor doping structure further includes a third semiconductor doping layer covering the top surface of the first semiconductor doping layer and the top surface of the second semiconductor doping layer, the doping concentration of the third semiconductor doping layer being greater than or equal to the doping concentration of the first semiconductor doping layer.
In one embodiment, the substrate includes an active region through which the word line trench passes, the active region including source and drain regions located on opposite sides of the word line trench, the source and drain regions laterally overlapping the semiconductor doping structure and the source and drain regions not laterally overlapping the conductive layer.
In one embodiment, the first semiconductor doped layer covers a portion of the top surface of the conductive layer.
In the semiconductor structure, the semiconductor doping structure covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove, the semiconductor doping structure comprises the first semiconductor doping layer and the second semiconductor doping layer, the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, compared with the situation that the middle part of the word line groove is only filled with the first semiconductor doping layer, the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, so that the gate-induced drain leakage current of the semiconductor structure is kept unchanged, and meanwhile, the side wall of the first semiconductor doping layer and the top surface of the conducting layer are covered, and the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, so that the threshold voltage of the semiconductor structure is increased, and the performance of the semiconductor structure (embedded transistor) is improved.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure after forming a wordline trench in one embodiment;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure after forming a conductive layer according to one embodiment;
FIG. 4 is a schematic flow chart of forming a conductive layer covering a portion of a sidewall of a gate dielectric layer and filling a bottom of a word line trench in one embodiment;
FIG. 5 is a schematic flow chart of a semiconductor doping structure formed to cover a portion of the sidewall of the gate dielectric layer and fill the middle of the word line trench in one embodiment;
FIG. 6 is a schematic cross-sectional view of a semiconductor structure after forming a second semiconductor doping material layer according to an embodiment;
FIG. 7 is a schematic cross-sectional view of the semiconductor structure after forming the semiconductor doped structure according to the embodiment shown in FIG. 6;
FIG. 8 is a schematic cross-sectional view of the semiconductor structure after forming the semiconductor doped structure according to another embodiment corresponding to FIG. 6;
fig. 9 is a schematic cross-sectional view of a semiconductor structure after forming a passivation layer in an embodiment.
Reference numerals illustrate:
102. a substrate; 104. word line trenches; 106. a source/drain region; 108. a gate dielectric layer; 110. a conductive layer; 112. a semiconductor doping structure; 114. a protective layer; 202. a first semiconductor doped layer; 204. a second semiconductor doped layer; 206. a third semiconductor doped layer; 302. a second semiconductor doping material layer; 304. a first semiconductor doped material sub-layer; 306. an intermediate semiconductor doped material sub-layer; 308. a top semiconductor doped material sub-layer; 310. a first semiconductor doping sub-layer; 312. an intermediate semiconductor doping sub-layer; 314. the top semiconductor doping sub-layer.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first semiconductor doped layer may be referred to as a second semiconductor doped layer, and similarly, the second semiconductor doped layer may be referred to as a first semiconductor doped layer; the first semiconductor doped layer and the second semiconductor doped layer are different semiconductor doped layers, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
As used herein, the terms "substrate," "base" mean and include the base material or construction of the materials of the transistors described in the present disclosure. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.
In the present disclosure, the upper surface of the substrate is the surface of the substrate near the wordline trench opening, the lower surface of the substrate is the surface of the substrate near the wordline trench opening, the upper and lower surfaces of other structures or layers are the upper surface of the substrate, the upper/top surface of the two surfaces in the longitudinal direction near the upper surface of the substrate, and the lower/bottom surface facing away from the upper surface of the substrate. For a structure or layer on a substrate, the opposite of the two surfaces is the lower/bottom surface, which is adjacent to the upper surface of the substrate, and the upper/top surface, which is remote from the upper surface of the substrate. For a structure, trench, hole, or layer in a semiconductor structure, the surface in the horizontal direction is the sidewall of the structure, trench, hole, or layer.
By forming a double-gate buried word line structure using heavily doped polysilicon and titanium nitride, the effect of feature size shrinkage on gate-induced drain leakage current of the memory transistor can be improved, but forming a double-gate buried word line structure from heavily doped polysilicon and titanium nitride reduces the threshold voltage of the memory transistor and increases power consumption and leakage of the memory transistor. How to avoid the influence on the threshold voltage while reducing the gate induced leakage current of the memory transistor is a problem to be solved.
Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment, and fig. 2 is a schematic cross-sectional view of the semiconductor structure after forming a word line trench according to an embodiment, as shown in fig. 1 and fig. 2, in which the method for manufacturing a semiconductor structure is provided, and includes:
s102, providing a substrate, wherein a word line groove is formed in the substrate.
A substrate 102 is provided, a plurality of word line trenches 104 are formed in the substrate 102 extending from a surface of the substrate 102 into the substrate 102, the word line trenches 104 being used to fill and form word line structures. Constituent materials of the substrate 102 include, but are not limited to, undoped monocrystalline silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. As an example, in the present embodiment, the constituent material of the substrate 102 is selected from single crystal silicon.
S104, forming a gate dielectric layer covering the word line grooves in a conformal mode.
Fig. 3 is a schematic cross-sectional view of a semiconductor structure after forming a conductive layer in an embodiment, as shown in fig. 3, a gate dielectric layer 108 is formed in the word line trench 104 to cover an inner wall of the word line trench 104, wherein the inner wall of the word line trench 104 includes a bottom surface of the word line trench 104 and a sidewall of the word line trench 104, by using an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process. Exemplary, the constituent materials of gate dielectric layer 108 The material includes, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., al 2 O 3 ) Metal oxynitride (e.g., alON), metal silicide, and low-k dielectric materials (dielectric constant greater than or equal to 2.5, less than 3.9). At process nodes below 65nm, the feature size of the gate structure is small, and the material constituting the gate dielectric layer 108 is preferably a high-k dielectric material. The high-k dielectric material includes hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like. Hafnium oxide, zirconium oxide and aluminum oxide are preferred embodiments.
And S106, forming a conductive layer which covers part of the gate dielectric layer and fills the bottom of the word line groove.
A conductive layer 110 is formed at the bottom of the word line trench 104, the conductive layer 110 covering the gate dielectric layer 108 at the bottom of the word line trench 104 and on the sidewalls of the word line trench 104 near the bottom and filling the space at the bottom of the word line trench 104. The direction in which the bottom surface of the word line trench 104 points to the opening of the word line trench is labeled as a first direction X, dividing the word line trench 104 into a bottom portion near the bottom surface of the word line trench 104, a top portion near the opening of the word line trench 104, and a middle portion between the bottom portion and the top portion.
S108, forming a semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove.
And forming a semiconductor doping structure on the surface of the conductive layer, wherein the semiconductor doping structure fills the middle part of the word line groove and is contacted with part of the side wall of the gate dielectric layer, namely covers part of the side wall of the gate dielectric layer, and the side wall of the gate dielectric layer is the surface of the gate dielectric layer, which is away from the side wall of the word line groove. The semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, namely, the first semiconductor doping layer is in contact with the gate dielectric layer close to the conducting layer, the second semiconductor doping layer is filled in a space surrounded by the first semiconductor doping layer and the top surface of the conducting layer in the word line groove, the top surface of the second semiconductor doping layer does not exceed the top surface of the first semiconductor doping layer, the top surface of the conducting layer is the surface of the conducting layer close to the upper surface of the substrate, and the threshold voltage of the semiconductor structure can be adjusted by adjusting the doping concentration of the second semiconductor doping layer.
S110, forming a protective layer which covers the semiconductor doping structure and fills the top of the word line groove.
And forming a protective layer filling the top of the word line groove on the semiconductor doping structure, wherein the protective layer covers the top surface of the semiconductor doping structure and is in contact with the gate dielectric layer.
The preparation method of the semiconductor structure comprises the steps of forming the semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove, wherein the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer, compared with the mode that the middle part of the word line groove is only filled with the first semiconductor doping layer, the first semiconductor doping layer which covers part of the side wall of the gate dielectric layer in the semiconductor doping structure enables the gate induced drain leakage current of the semiconductor structure to be kept unchanged, meanwhile, the doping concentration of the second semiconductor doping layer in the semiconductor doping structure is smaller than that of the first semiconductor doping layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and the top surface of the conducting layer, threshold voltage of the semiconductor structure is increased, power consumption and electric leakage of the semiconductor structure are reduced, and performance of the semiconductor structure (buried transistor) is improved.
As shown in fig. 3, in one embodiment, the substrate 102 includes an active region, the word line trench 104 penetrates the active region, and the method for manufacturing the semiconductor structure further includes: the portions of the active region on opposite sides of the word line trench 104 are doped to form source and drain regions 106, wherein the same active region is used as the source of a transistor and the other is used as the drain of a transistor, both of which are interchangeable, source and drain regions 106 on opposite sides of the word line trench 104.
In one embodiment, source drain region 106 laterally overlaps the semiconductor doped structure, and source drain region 106 does not laterally overlap conductive layer 110. In other embodiments, the source drain regions 106 do not laterally overlap the semiconductor doping structure.
Fig. 4 is a schematic flow chart of forming a conductive layer covering a portion of a sidewall of the gate dielectric layer and filling a bottom of the word line trench, as shown in fig. 3 and 4, in one embodiment, forming a conductive layer 110 covering a portion of a sidewall of the gate dielectric layer 108 and filling a bottom of the word line trench 104, including:
s202, forming a diffusion barrier material layer covering the gate dielectric layer in a conformal manner.
A diffusion barrier material layer is formed on the surface of the gate dielectric layer 108 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, and the diffusion barrier material layers on opposite sidewalls of the wordline trenches 104 are not in contact, i.e., the diffusion barrier material layers in the wordline trenches 104 have gaps in the horizontal direction. Illustratively, the constituent materials of the diffusion barrier material layer include, but are not limited to, one or more of metallic titanium or titanium nitride.
S204, forming a metal material layer which covers the diffusion barrier material layer and fills the word line groove.
A metal material layer filling the word line trenches 104 is formed on the surface of the diffusion barrier material layer by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, and fills at least the bottoms of the word line trenches 104.
Alternatively, the constituent materials of the metal material layer include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, and the metal may be, for example, tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2); the metal silicide includes tungsten silicon (WSi).
S206, etching back the metal material layer and the diffusion barrier material layer, and reserving the diffusion barrier material layer and the metal material layer which are positioned at the bottom of the word line trench as a diffusion barrier layer and a metal layer respectively;
etching the metal material layer and the diffusion barrier material layer in the word line groove 104, and removing the metal material layer and the diffusion barrier material layer filled at the top and the middle of the word line groove 104 to obtain a diffusion barrier layer formed by the diffusion barrier material layer at the bottom of the word line groove 104 and a metal layer formed by the metal material layer at the bottom of the word line groove 104; wherein the conductive layer comprises a diffusion barrier layer and a metal layer.
Fig. 5 is a schematic flow chart illustrating a process of forming a semiconductor doped structure covering a portion of a sidewall of a gate dielectric layer and filling a middle portion of a word line trench in one embodiment, fig. 6 is a schematic cross-sectional view illustrating a semiconductor structure after forming a second semiconductor doped material layer in one embodiment, fig. 7 is a schematic cross-sectional view illustrating a semiconductor structure after forming a semiconductor doped structure in one embodiment corresponding to fig. 6, and fig. 8 is a schematic cross-sectional view illustrating a semiconductor structure after forming a semiconductor doped structure in another embodiment corresponding to fig. 6, as shown in fig. 5, 6, 7, and 8, in one embodiment, forming a semiconductor doped structure 112 covering a portion of a sidewall of a gate dielectric layer 108 and filling a middle portion of a word line trench 104, comprising:
s302, forming a first semiconductor doping material layer covering the side wall of the gate dielectric layer and the top surface of the conductive layer in a conformal manner.
Specifically, a first semiconductor doped material layer is formed on the inner wall of the word line trench 104 by an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process or an epitaxy process, and covers the sidewall of the gate dielectric layer 108 and the top surface of the conductive layer 110 in a conformal manner, where the first semiconductor doped material layer has first doped ions. Illustratively, the process temperature for forming the first semiconductor doping material layer includes 430-550 ℃, such as 430 ℃, 440 ℃, 450 ℃, 460 ℃, 470 ℃, 480 ℃, 490 ℃, 500 ℃, 510 ℃, 520 ℃, 530 ℃, 550 ℃, etc.; the process gas for forming the first semiconductor doping material layer includes, but is not limited to, phosphine (PH) 3 ) The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the first semiconductor doping material layer is more than 0 and less than or equal to 30nm; first semiconductor doping material layer of first semiconductor doping material layerThe doping concentration of the doping ions is greater than or equal to 20 x 10 20 ions/cm 2 。
S304, etching back the first semiconductor doped material layer, and reserving the first semiconductor doped material layer on the side wall of the gate dielectric layer, which is close to the conductive layer, as the first semiconductor doped layer.
The first semiconductor doped material layer adjacent to the opening of the word line trench 104 and on the conductive layer 110 is etched away, and the remaining first semiconductor doped material layer on the sidewall of the gate dielectric layer 108 adjacent to the conductive layer 110 serves as the first semiconductor doped layer 202. Illustratively, the first semiconductor doped layer 202 overlies sidewalls of the gate dielectric layer 108 in the middle of the wordline trench 104, and a bottom surface of the first semiconductor doped layer 202 contacts a top surface of the conductive layer 110.
S306, forming a second semiconductor doping material layer which covers the first semiconductor doping layer and fills the word line groove.
A second semiconductor doping material layer 302 is formed in the wordline trench 104 by an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or an epitaxy process, covering the first semiconductor doping layer 202 and filling the wordline trench 104, the second semiconductor doping material layer 302 at least filling the middle of the wordline trench 104, and the second semiconductor doping material layer 302 extending along the sidewalls of the wordline trench 104 to cover the substrate 102. The second semiconductor dopant material layer 302 has second dopant ions therein. Illustratively, the process temperature for forming the second semiconductor doping material layer 302 includes 430-550 ℃, such as 430 ℃, 440 ℃, 450 ℃, 460 ℃, 470 ℃, 480 ℃, 490 ℃, 500 ℃, 510 ℃, 520 ℃, 530 ℃, 550 ℃, etc.; the process gas for forming the second semiconductor doping material layer 302 includes, but is not limited to, phosphine (PH) 3 ) The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the second dopant ions in the second semiconductor dopant material layer 302 is less than 2 x 10 21 ions/cm 2 Greater than or equal to 1 x 10 20 ions/cm 2 For example 5 x 10 20 ions/cm 2 。
And S308, etching back the second semiconductor doping material layer, and reserving the second doping material layer positioned in the middle of the word line groove as the second semiconductor doping layer.
The second semiconductor doped material layer 302 in the wordline trench 104 and on the substrate 102 is etched to remove the second semiconductor doped material layer 302 filled at the top of the wordline trench 104, resulting in a second semiconductor doped layer 204 composed of the second semiconductor doped material layer 302 in the middle of the wordline trench 104.
In other embodiments, the step of forming the semiconductor doping structure 112 that covers a portion of the sidewall of the gate dielectric layer 108 and fills the middle of the word line trench 104 is similar to the steps S302-S308 described above, except that step S304 is to etch back the first semiconductor doping material layer, leave the first semiconductor doping material layer on the sidewall of the gate dielectric layer as an initial first semiconductor doping layer, and etch immediately remove the first semiconductor doping material layer on the conductive layer 110 to obtain an initial first semiconductor doping layer on the sidewall of the gate dielectric layer. Illustratively, the bottom surface of the initial first semiconductor doped layer is in contact with the top surface of the conductive layer 110. Step S308 is to etch back the second semiconductor doped material layer 302 and the initial first semiconductor doped layer, leave the second semiconductor doped material layer 302 located in the middle of the word line trench 104 as the second semiconductor doped layer 204, and leave the initial first semiconductor doped layer located on the sidewall of the gate dielectric layer 108 in the middle of the word line trench 104 as the first semiconductor doped layer 202.
As shown in fig. 6, in one embodiment, forming a second semiconductor doping material layer 302 that covers the first semiconductor doping layer 202 and fills the word line trenches 104 includes: forming a plurality of semiconductor doped material sublayers stacked in sequence, dividing the stacked plurality of semiconductor doped material sublayers into a first semiconductor doped material sublayer 304, an intermediate semiconductor doped material sublayer 306, and a top semiconductor doped material sublayer 308, the number of intermediate semiconductor doped material sublayers 306 being illustratively greater than or equal to 0; wherein the latter semiconductor dopant material sub-layer conformally covers the former semiconductor dopant material sub-layer. When the number of the intermediate semiconductor doped material sub-layers 306 is 0, the top semiconductor doped material sub-layer 308 is formed to cover the surface of the first semiconductor doped material sub-layer 304, and the top semiconductor doped material sub-layer 308 at least fills the middle of the word line trench 104. When the number of the intermediate semiconductor doped material sub-layers 306 is greater than 0, the intermediate semiconductor doped material sub-layers 306 cover the surface of the first semiconductor doped material sub-layer 304 facing away from the inner wall of the word line trench 104 in a conformal manner, and the intermediate semiconductor doped material sub-layers 306 facing away from the first semiconductor doped material sub-layer 304 cover the surface of the intermediate semiconductor doped material sub-layer 306 adjacent to the first semiconductor doped material sub-layer 304 in a conformal manner; the top semiconductor dopant material sub-layer 308 is conformal over the surface of the intermediate semiconductor dopant material sub-layer 306 facing away from the first semiconductor dopant material sub-layer 304, and the top semiconductor dopant material sub-layer 308 fills at least a middle portion of the word line trench 104. The number of intermediate semiconductor dopant material sublayers 306 greater than 0 is exemplified below. Illustratively, the top semiconductor dopant material sub-layer 308 fills the wordline trenches 104.
In some embodiments, as shown in fig. 6, a first semiconductor doped material sub-layer (first semiconductor doped material sub-layer 304) covers the top surface of conductive layer 110 and is in contact with first semiconductor doped layer 202. In another embodiment, the first semiconductor doped material sub-layer (the first semiconductor doped material sub-layer 304) covers the top surfaces of the first semiconductor doped layer 202 and the conductive layer 110 along with the shape, at this time, the preparation process of the second semiconductor doped material layer 302 is simple, so that the damage of multiple etching to the gate dielectric layer 108 is avoided, and the risk of electric leakage is reduced.
The doping concentration of each semiconductor dopant material sub-layer may be varied by adjusting the concentration of the dopant gas during formation of each semiconductor dopant material sub-layer, and in some embodiments, the doping concentration of the top semiconductor dopant material sub-layer 308 is greater than or equal to the doping concentration of the first semiconductor dopant material sub-layer 304. In some embodiments, there is at least one intermediate semiconductor dopant material sub-layer 306 having a doping concentration greater than or equal to the doping concentration of the first semiconductor dopant material sub-layer 304. In some embodiments, the doping concentration of the top semiconductor doping material sub-layer 308 is greater than or equal to the doping concentration of the at least one middle semiconductor doping material sub-layer 306. The regulation and control of the threshold voltage of the semiconductor structure can be realized by adjusting the doping concentration of each semiconductor doping material sub-layer, so that the read-write performance of the semiconductor structure is improved.
In one embodiment, the first semiconductor doping material layer is formed using an in-situ doping process. Illustratively, the concentration of the dopant gas in the process gas is adjusted during formation of the first semiconductor dopant material layer to obtain a first semiconductor dopant material layer having a different dopant concentration.
In one embodiment, the second semiconductor doping material layer 302 is formed using an in-situ doping process. Illustratively, the concentration of the dopant gas in the process gas is adjusted during the formation of the second semiconductor dopant material layer 302 to obtain semiconductor dopant material sublayers having different dopant concentrations.
In some embodiments, the doping concentration of the semiconductor doping material sub-layer of the intermediate semiconductor doping material sub-layer 306 that is away from the first semiconductor doping material sub-layer 304 is greater than the doping concentration of the semiconductor doping material sub-layer that is proximate to the first semiconductor doping material sub-layer 304.
In some embodiments, the doping concentration of the top semiconductor doping material sub-layer 308 is greater than the doping concentration of each of the intermediate semiconductor doping material sub-layers 306, and the doping concentration of each of the intermediate semiconductor doping material sub-layers 306 is greater than the doping concentration of the first semiconductor doping material sub-layer 304. Illustratively, the doping concentration of the latter semiconductor doping material sub-layer is greater than or equal to the doping concentration of the former semiconductor doping material sub-layer. Compared with the doping concentration of each semiconductor doping material sub-layer being equal to the doping concentration of the top semiconductor doping material sub-layer 308, the gate induced drain leakage current of the semiconductor structure is kept unchanged, the threshold voltage of the semiconductor structure is further increased, and the reliability of the semiconductor structure is improved.
In one embodiment, the doping concentration of the second semiconductor doped layer 204 increases gradually in a direction along the bottom of the word line trench 104 toward the top of the word line trench 104 and past the top center O of the second semiconductor doped layer 204, i.e., in a first direction X from the bottom of the word line trench 104 toward the top of the word line trench 104 past the top center O of the second semiconductor doped layer 204; illustratively, the doping concentration of the second semiconductor doped layer 204 increases in sequence in a direction along the bottom of the word line trench 104 toward the top of the word line trench 104 and through the top center O of the second semiconductor doped layer 204; the doping concentration of the second semiconductor doping layer 204 gradually decreases in a direction along the top surface center O of the second semiconductor doping layer 204 toward the top surface edge of the second semiconductor doping layer 204, i.e., in a direction along which the top surface center O of the second semiconductor doping layer 204 is directed toward any contact point of the top surface of the second semiconductor doping layer 204 with the first semiconductor doping layer 202; illustratively, the doping concentration of the second semiconductor doping layer 204 decreases in sequence in a direction along the top center O of the second semiconductor doping layer 204 toward the top edge of the second semiconductor doping layer 204.
In some embodiments, the top surface of the second semiconductor doped layer 204 is flush with the top surface of the first semiconductor doped layer 202. In other embodiments, the top surface of the second semiconductor doped layer 204 is lower than the top surface of the first semiconductor doped layer 202, so that the problem that the gate-induced drain leakage current of the semiconductor structure is increased due to the fact that the top surface of the second semiconductor doped layer 204 is higher than the top surface of the first semiconductor doped layer 202 in part of the region due to process deviation is avoided.
As shown in fig. 8, in one embodiment, forming the semiconductor doped structure 112 that covers a portion of the gate dielectric layer 108 and fills the middle of the wordline trench 104 further includes:
forming a third semiconductor doping material layer that covers the top surface of the first semiconductor doping layer 202 and the top surface of the second semiconductor doping layer 204 and fills the word line trench 104;
etching back the third semiconductor doping material layer, leaving the third semiconductor doping material layer located on the top surface of the first semiconductor doping layer 202 and the top surface of the second semiconductor doping layer 204 as the third semiconductor doping layer 206;
the semiconductor doping structure 112 further includes a third semiconductor doping layer 206, where the doping concentration of the third semiconductor doping layer 206 is greater than or equal to the doping concentration of the first semiconductor doping layer 202. The second semiconductor doped layer 204 with the smallest doping concentration in the semiconductor doped structure 112 is located in a closed space surrounded by the first semiconductor doped layer 202 and the third semiconductor doped layer 206, so that the problem that the gate-induced drain leakage current of the semiconductor structure is increased due to the fact that the top surface of the second semiconductor doped layer 204 is higher than the top surface of the first semiconductor doped layer 202 in a partial area due to process deviation is avoided.
Illustratively, the constituent material of the first semiconductor doped layer 202, the constituent material of the second semiconductor doped layer 204, and the constituent material of the third semiconductor doped layer 206 include, but are not limited to, polysilicon.
Fig. 9 is a schematic cross-sectional view of the semiconductor structure after forming the protection layer, as shown in fig. 9, in this embodiment, forming the protection layer 114 covering the semiconductor doped structure 112 and filling the top of the word line trench 104 includes: forming a protective material layer covering the semiconductor doping structure 112 and filling the word line trench 104, wherein a top surface of the protective material layer is higher than a top surface of the substrate 102; a CMP process is used to remove the protective material layer above the top surface of the substrate 102, the protective material layer on top of the wordline trenches acting as a protective layer 114. Exemplary materials of construction for the protective layer 114 include, but are not limited to, one or more of oxides, nitrides and oxynitrides, carbides, with the oxide including, illustratively, silicon dioxide (SiO 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The nitride includes silicon nitride (SiN); oxynitride includes silicon oxynitride (SiON), and carbide includes silicon carbide.
It should be understood that, although the steps in the flowcharts of fig. 1, 4, and 5 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1, 4, and 5 may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
As shown in fig. 9, in the present embodiment, there is provided a semiconductor structure including: substrate 102, gate dielectric layer 108, conductive layer 110, semiconductor doped structure 112, and protective layer 114; a word line trench 104 is formed in the substrate 102; gate dielectric layer 108 conformally covers word line trench 104; conductive layer 110 covers a portion of gate dielectric layer 108 and fills the bottom of wordline trench 104; the semiconductor doping structure 112 covers part of the sidewall of the gate dielectric layer 108 and fills the middle of the word line trench 104; the protective layer 114 covers the semiconductor doped structure 112 and fills the top of the word line trench 104; the semiconductor doped structure 112 includes a first semiconductor doped layer 202 and a second semiconductor doped layer 204, where the first semiconductor doped layer 202 covers a portion of the sidewall of the gate dielectric layer 108, the second semiconductor doped layer 204 covers the sidewall of the first semiconductor doped layer 202 and covers the top surface of the conductive layer 110, and the doping concentration of the second semiconductor doped layer 204 is less than the doping concentration of the first semiconductor doped layer 202.
Specifically, a plurality of word line trenches 104 are formed in the substrate 102 extending from the surface of the substrate 102 into the substrate 102, the word line trenches 104 being filled to form a word line structure. Constituent materials of the substrate 102 include, but are not limited to, undoped monocrystalline silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. As an example, in the present embodiment, the constituent material of the substrate 102 is selected from single crystal silicon. Gate dielectric layer 108 conformally covers the inner walls of word line trench 104, including the bottom surface of word line trench 104 and the sidewalls of word line trench 104. The conductive layer 110 covers the gate dielectric layer 108 at the bottom of the word line trench 104 and on the sidewalls of the word line trench 104 near the bottom and fills the space at the bottom of the word line trench 104. The direction in which the bottom surface of the word line trench 104 points to the opening of the word line trench is labeled as a first direction X, dividing the word line trench 104 into a bottom portion near the bottom surface of the word line trench 104, a top portion near the opening of the word line trench 104, and a middle portion between the bottom portion and the top portion. The semiconductor doped structure 112 is located on the surface of the conductive layer 110, fills the middle of the word line trench 104, and contacts a portion of the sidewall of the gate dielectric layer 108, i.e., covers a portion of the sidewall of the gate dielectric layer 108, where the sidewall of the gate dielectric layer 108 is the surface of the gate dielectric layer 108 facing away from the sidewall of the word line trench 104. The first semiconductor doped layer 202 is in contact with the gate dielectric layer 108 near the conductive layer 110, the second semiconductor doped layer 204 is filled in an open space in the word line trench 104 surrounded by the first semiconductor doped layer 202 and the top surface of the conductive layer 110, that is, the second semiconductor doped layer 204 fills the middle of the word line trench 104, and the top surface of the second semiconductor doped layer 204 does not exceed the top surface of the first semiconductor doped layer 202, and the top surface of the conductive layer 110 is the surface of the conductive layer 110 near the upper surface of the substrate 102. The protective layer 114 covers the top surface of the semiconductor doped structure 112 and contacts the gate dielectric layer 108.
In the above semiconductor structure, the semiconductor doped structure 112 covers a portion of the sidewall of the gate dielectric layer 108 and fills the middle of the word line trench 104, the semiconductor doped structure 112 includes the first semiconductor doped layer 202 and the second semiconductor doped layer 204, the doping concentration of the second semiconductor doped layer 204 is smaller than that of the first semiconductor doped layer 202, compared with the case that only the first semiconductor doped layer 202 is filled in the middle of the word line trench 104, the first semiconductor doped layer 202 covering a portion of the sidewall of the gate dielectric layer 108 allows the gate induced drain leakage current of the semiconductor structure to remain unchanged, and simultaneously covers the sidewall of the first semiconductor doped layer 202 and the top surface of the conductive layer 110, and the second semiconductor doped layer 204 with the doping concentration smaller than that of the first semiconductor doped layer 202 increases the threshold voltage of the semiconductor structure, reduces the power consumption and leakage of the semiconductor structure, and improves the performance of the semiconductor structure (buried transistor).
Exemplary materials of construction for gate dielectric layer 108 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., al) 2 O 3 ) Metal oxynitride (e.g., alON), metal silicide, and low-k dielectric materials (dielectric constant greater than or equal to 2.5, less than 3.9). At process nodes below 65nm, the feature size of the gate structure is small, and the material constituting the gate dielectric layer 108 is preferably a high-k dielectric material. The high-k dielectric material comprises hafnium oxide, hafnium silicon oxynitride, Lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like. Hafnium oxide, zirconium oxide and aluminum oxide are preferred embodiments.
In one embodiment, the substrate 102 includes an active region through which the word line trench 104 passes, the active region including source drain regions 106 on opposite sides of the word line trench 104, the source drain regions 106 laterally overlapping the semiconductor doped structures 112, and the source drain regions 106 not laterally overlapping the conductive layer 110. Wherein the source and drain regions 106 on opposite sides of the wordline trench 104 in the same active region, one of which serves as the source of the transistor and the other serves as the drain of the transistor, are interchangeable.
In one embodiment, source drain region 106 laterally overlaps the semiconductor doped structure, and source drain region 106 does not laterally overlap conductive layer 110. In other embodiments, the source drain regions 106 do not laterally overlap the semiconductor doping structure.
In one embodiment, conductive layer 110 comprises a top flush diffusion barrier layer and a metal layer, the diffusion barrier layer conformally covering the sidewalls of gate dielectric layer 108 at the bottom of wordline trench 104, the diffusion barrier layers on opposite sidewalls of wordline trench 104 not contacting, i.e., the diffusion barrier layers in wordline trench 104 have gaps in the horizontal direction, exemplary materials of construction for the diffusion barrier material layer include, but are not limited to, one or more of metallic titanium or titanium nitride. The metal layer fills the bottoms of the wordline trenches 104, i.e., the metal layer fills the gaps between the diffusion barriers. Alternatively, the constituent materials of the metal layer include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, and the metal may be, by way of example, tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2); the metal silicide includes tungsten silicon (WSi).
In some embodiments, the thickness of the first semiconductor doped layer 202 is greater than 0 and less than or equal to 1nm; the doping concentration of the first semiconductor doping layer 202 is greater than orEqual to 2 x 10 21 ions/cm 2 。
Illustratively, the first semiconductor doped layer 202 overlies sidewalls of the gate dielectric layer 108 in the middle of the wordline trench 104. The doping concentration of the second semiconductor doping layer 204 is less than 2 x 10 21 ions/cm 2 Greater than or equal to 1 x 10 20 ions/cm 2 For example 5 x 10 20 ions/cm 2 . Optionally, the doping ions of the first semiconductor doping layer 202 and the doping ions of the second semiconductor doping layer 204 are the same, for example, phosphorus ions; the dopant ions of the first semiconductor doped layer 202 and the dopant ions of the second semiconductor doped layer 204 may be different. In some embodiments, the first semiconductor doped layer covers a portion of the top surface of the conductive layer, i.e., the bottom surface of the first semiconductor doped layer 202 is in contact with the top surface of the conductive layer 110.
As shown in fig. 7, in one embodiment, the second semiconductor doped layer 204 includes a plurality of semiconductor doped sublayers stacked in sequence, and the stacked plurality of semiconductor doped sublayers is divided into a first semiconductor doped sublayer 310, an intermediate semiconductor doped sublayer 312 and a top semiconductor doped sublayer 314, and the number of intermediate semiconductor doped sublayers 312 is greater than or equal to 0 as an example; wherein the latter semiconductor doped sub-layer is conformal over the former semiconductor doped sub-layer. When the number of the intermediate semiconductor doped sublayers 312 is 0, the top semiconductor doped sublayers 314 cover the surface of the first semiconductor doped sublayers 310 in a conformal manner, and the top semiconductor doped sublayers 314 fill the middle of the word line trench 104. When the number of the intermediate semiconductor doping sub-layers 312 is greater than 0, the intermediate semiconductor doping sub-layers 312 cover the surface of the first semiconductor doping sub-layer 310 facing away from the inner wall of the word line trench 104 in a conformal manner, and the intermediate semiconductor doping sub-layer 310 facing away from the first semiconductor doping sub-layer 310 covers the surface of the intermediate semiconductor doping sub-layer 312 close to the first semiconductor doping sub-layer 310 in a conformal manner; the top semiconductor doped sub-layer 314 conformally overlies the surface of the intermediate semiconductor doped sub-layer 312 facing away from the first semiconductor doped sub-layer 310, and the top semiconductor doped sub-layer 314 fills the middle of the word line trench 104. The number of intermediate semiconductor doped sublayers 319 is greater than 0 as exemplified below. Illustratively, the top semiconductor doped sub-layer 314 fills the wordline trench 104.
In some embodiments, as shown in fig. 7, a first semiconductor doped sub-layer (first semiconductor doped sub-layer 310) covers the top surface of conductive layer 110 and is in contact with first semiconductor doped layer 202. In another embodiment, the first semiconductor doped sub-layer (the first semiconductor doped sub-layer 310) covers the sidewall of the first semiconductor doped layer 202 and the top surface of the conductive layer 110 along with the shape, at this time, the preparation process of the second semiconductor doped layer 204 is simple, so that the damage to the gate dielectric layer 108 caused by multiple etching in the process of forming the second semiconductor doped layer 204 is avoided, and the risk of leakage is reduced.
The doping concentration of each semiconductor doping sub-layer may be varied by adjusting the concentration of the doping gas during formation of each semiconductor doping sub-layer, and in some embodiments, the doping concentration of the top semiconductor doping sub-layer 314 is greater than or equal to the doping concentration of the first semiconductor doping sub-layer 310. In some embodiments, there is at least one intermediate semiconductor doping sub-layer 312 having a doping concentration greater than or equal to the doping concentration of the first semiconductor doping sub-layer 310. In some embodiments, the doping concentration of the top semiconductor doping sub-layer 314 is greater than or equal to the doping concentration of the at least one middle semiconductor doping sub-layer 312. The regulation and control of the threshold voltage of the semiconductor structure can be realized by adjusting the doping concentration of each semiconductor doping sub-layer, so that the read-write performance of the semiconductor structure is improved.
In some embodiments, the doping concentration of the semiconductor doping sub-layer of the intermediate semiconductor doping sub-layer 312 that faces away from the first semiconductor doping sub-layer 310 is greater than the doping concentration of the semiconductor doping material sub-layer that is adjacent to the first semiconductor doping sub-layer 310.
In some embodiments, the doping concentration of the top semiconductor doping sub-layer 314 is greater than the doping concentration of each intermediate semiconductor doping sub-layer 312, and each intermediate semiconductor doping sub-layer 312 has a doping concentration greater than the doping concentration of the first semiconductor doping sub-layer 310. Illustratively, the doping concentration of the latter semiconductor doping sub-layer is greater than or equal to the doping concentration of the former semiconductor doping sub-layer. Compared with the doping concentration of each semiconductor doping sub-layer being equal to the doping concentration of the top semiconductor doping sub-layer 314, the gate-induced drain leakage current of the semiconductor structure is kept unchanged, the threshold voltage of the semiconductor structure is further increased, and the reliability of the semiconductor structure is improved.
In one embodiment, the doping concentration of the second semiconductor doped layer 204 increases gradually in a direction along the bottom of the word line trench 104 toward the top of the word line trench 104 and past the top center O of the second semiconductor doped layer 204, i.e., in a first direction X from the bottom of the word line trench 104 toward the top of the word line trench 104 past the top center O of the second semiconductor doped layer 204; illustratively, the doping concentration of the second semiconductor doped layer 204 increases in sequence in a direction along the bottom of the word line trench 104 toward the top of the word line trench 104 and through the top center O of the second semiconductor doped layer 204; the doping concentration of the second semiconductor doping layer 204 gradually decreases in a direction along the top surface center O of the second semiconductor doping layer 204 toward the top surface edge of the second semiconductor doping layer 204, i.e., in a direction along which the top surface center O of the second semiconductor doping layer 204 is directed toward any contact point of the top surface of the second semiconductor doping layer 204 with the first semiconductor doping layer 202; illustratively, the doping concentration of the second semiconductor doping layer 204 decreases in sequence in a direction along the top center O of the second semiconductor doping layer 204 toward the top edge of the second semiconductor doping layer 204.
In some embodiments, the top surface of the second semiconductor doped layer 204 is flush with the top surface of the first semiconductor doped layer 202. In other embodiments, the top surface of the second semiconductor doped layer 204 is lower than the top surface of the first semiconductor doped layer 202, so that the problem that the gate-induced drain leakage current of the semiconductor structure is increased due to the fact that the top surface of the second semiconductor doped layer 204 is higher than the top surface of the first semiconductor doped layer 202 in part of the region due to process deviation is avoided.
As shown in fig. 8, in one embodiment, the semiconductor doping structure 112 further includes a third semiconductor doping layer 206, the third semiconductor doping layer 206 covers the top surface of the first semiconductor doping layer 202 and the top surface of the second semiconductor doping layer 204, and the doping concentration of the third semiconductor doping layer 206 is greater than or equal to the doping concentration of the first semiconductor doping layer 202. The second semiconductor doped layer 204 with the smallest doping concentration in the semiconductor doped structure 112 is located in a closed space surrounded by the first semiconductor doped layer 202 and the third semiconductor doped layer 206, so that the problem that the gate-induced drain leakage current of the semiconductor structure is increased due to the fact that the top surface of the second semiconductor doped layer 204 is higher than the top surface of the first semiconductor doped layer 202 in a partial area due to process deviation is avoided.
Illustratively, the constituent material of the first semiconductor doped layer 202, the constituent material of the second semiconductor doped layer 204, and the constituent material of the third semiconductor doped layer 206 include, but are not limited to, polysilicon.
The embodiment of the disclosure also provides a semiconductor structure, which is manufactured by adopting the preparation method of any one of the semiconductor structures.
The embodiment of the disclosure also provides electronic equipment comprising the semiconductor structure. The electronic device may include a smart phone, computer, tablet, artificial intelligence, wearable device, or intelligent mobile terminal. The embodiment of the application does not limit the specific form of the electronic device.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few implementations of the disclosed examples, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made to the disclosed embodiments without departing from the spirit of the disclosed embodiments.

Claims (12)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a word line groove is formed in the substrate;
forming a gate dielectric layer covering the word line groove along with the shape;
forming a conductive layer which covers part of the gate dielectric layer and fills the bottom of the word line groove;
forming a semiconductor doping structure which covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove;
forming a protective layer covering the semiconductor doping structure and filling the top of the word line groove;
the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, and the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer.
2. The method of claim 1, wherein forming the semiconductor doping structure covering a portion of the sidewall of the gate dielectric layer and filling the middle of the wordline trench comprises:
Forming a first semiconductor doping material layer covering the side wall of the gate dielectric layer and the top surface of the conductive layer along with the shape;
etching the first semiconductor doping material layer back, and reserving the first semiconductor doping material layer on the side wall, close to the conducting layer, of the gate dielectric layer as the first semiconductor doping layer;
forming a second semiconductor doping material layer which covers the first semiconductor doping layer and fills the word line groove;
and etching back the second semiconductor doping material layer, and reserving the second doping material layer positioned in the middle of the word line groove as the second semiconductor doping layer.
3. The method of manufacturing of claim 2, wherein forming the second semiconductor doping material layer that covers the first semiconductor doping layer and fills the word line trench comprises:
and forming a plurality of semiconductor doped material sublayers which are sequentially stacked, wherein the next semiconductor doped material sublayer covers the previous semiconductor doped material sublayer in a conformal manner, the doping concentration of the next semiconductor doped material sublayer is greater than that of the previous semiconductor doped material sublayer, and the first semiconductor doped material sublayer covers the first semiconductor doped layer and the top surface of the conductive layer in a conformal manner.
4. The method of manufacturing according to claim 3, wherein the doping concentration of the second semiconductor doping layer gradually increases in a direction along the bottom of the word line trench toward the top of the word line trench and passing through the center of the top surface of the second semiconductor doping layer;
the doping concentration of the second semiconductor doping layer gradually decreases in a direction along a top center of the second semiconductor doping layer toward a top edge of the second semiconductor doping layer.
5. The method of claim 1, wherein forming the semiconductor doping structure covering a portion of the sidewall of the gate dielectric layer and filling the middle of the wordline trench further comprises:
forming a third semiconductor doping material layer which covers the top surface of the first semiconductor doping layer and the top surface of the second semiconductor doping layer and fills the word line trench;
etching back the third semiconductor doping material layer, and reserving the third semiconductor doping material layer on the top surface of the first semiconductor doping layer and the top surface of the second semiconductor doping layer as a third semiconductor doping layer;
the semiconductor doping structure further comprises a third semiconductor doping layer, and the doping concentration of the third semiconductor doping layer is larger than or equal to that of the first semiconductor doping layer.
6. The method of manufacturing of claim 1, wherein the substrate includes an active region through which the wordline trench passes, the method of manufacturing further comprising:
and doping the parts of the active region, which are positioned on two opposite sides of the word line groove, to form a source-drain region, wherein the source-drain region transversely overlaps with the semiconductor doping structure, and the source-drain region does not transversely overlap with the conductive layer.
7. The method of manufacturing of claim 1, wherein forming the conductive layer that covers a portion of the gate dielectric layer and fills the bottom of the word line trench comprises:
forming a diffusion barrier material layer covering the gate dielectric layer in a conformal manner;
forming a metal material layer covering the diffusion barrier material layer and filling the word line trench;
etching back the metal material layer and the diffusion barrier material layer, and reserving the diffusion barrier material layer and the metal material layer which are positioned at the bottom of the word line groove as a diffusion barrier layer and a metal layer respectively;
wherein the conductive layer comprises the diffusion barrier layer and the metal layer.
8. A semiconductor structure, comprising:
A substrate in which a word line trench is formed;
the gate dielectric layer covers the word line groove along with the shape;
the conducting layer covers part of the gate dielectric layer and fills the bottom of the word line groove;
the semiconductor doping structure covers part of the side wall of the gate dielectric layer and fills the middle part of the word line groove;
a protective layer covering the semiconductor doping structure and filling the top of the word line trench;
the semiconductor doping structure comprises a first semiconductor doping layer and a second semiconductor doping layer, the first semiconductor doping layer covers part of the side wall of the gate dielectric layer, the second semiconductor doping layer covers the side wall of the first semiconductor doping layer and covers the top surface of the conducting layer, and the doping concentration of the second semiconductor doping layer is smaller than that of the first semiconductor doping layer.
9. The semiconductor structure of claim 8, wherein a doping concentration of the second semiconductor doped layer increases gradually in a direction along a bottom of the word line trench toward a top of the word line trench and past a center of a top surface of the second semiconductor doped layer;
the doping concentration of the second semiconductor doping layer gradually decreases in a direction along a top center of the second semiconductor doping layer toward a top edge of the second semiconductor doping layer.
10. The semiconductor structure of claim 8, further comprising a third semiconductor doped layer covering a top surface of the first semiconductor doped layer and a top surface of the second semiconductor doped layer, the third semiconductor doped layer having a doping concentration greater than or equal to a doping concentration of the first semiconductor doped layer.
11. The semiconductor structure of claim 8, the substrate comprising an active region through which the wordline trench passes, the active region comprising source and drain regions on opposite sides of the wordline trench, the source and drain regions laterally overlapping the semiconductor doped structure and the source and drain regions not laterally overlapping the conductive layer.
12. The semiconductor structure of claim 8, wherein the first semiconductor doped layer covers a portion of a top surface of the conductive layer.
CN202310741243.XA 2023-06-20 2023-06-20 Semiconductor structure and preparation method thereof Pending CN116801617A (en)

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