CN116799038A - An epitaxial structure and its preparation method - Google Patents

Abstract

An epitaxial structure and a preparation method thereof are disclosed. The epitaxial structure includes: a silicon substrate having a first surface; an epitaxial layer disposed on the first surface; the epitaxial layer It includes several sub-epitaxial layers and grid-like cracks, the plurality of sub-epitaxial layers are configured to be separated by the grid-shaped cracks, and the material of the epitaxial layer is a III-V group material. The disclosed epitaxial structure and its preparation method can utilize the grid-like cracks to release thermal mismatch tensile stress, thereby obtaining thicker and higher-quality epitaxial materials and reducing the warping of the silicon substrate during high-temperature epitaxial growth.

Description

An epitaxial structure and its preparation method

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular to an epitaxial structure and a preparation method thereof.

Background technique

III-V semiconductor materials are widely used in light-emitting devices due to their excellent properties such as direct band gap, large band gap, high breakdown field strength, easy preparation of heterojunction structures, radiation resistance, corrosion resistance and good thermal stability. and the production of high-frequency and high-power electronic devices. Taking gallium nitride devices as an example, currently due to the lack of high-quality and large-sized gallium nitride substrates, gallium nitride-based device films are usually prepared on sapphire, silicon carbide, silicon and other substrates through heteroepitaxial growth methods.

Compared with sapphire and silicon carbide substrates, silicon substrates have the advantages of large wafer size, high crystal quality, good thermal conductivity, low single-chip price, and easy adjustment of substrate conductivity. At the same time, the preparation and subsequent processing technology of silicon substrates are relatively mature, making silicon substrates an important substrate currently used for gallium nitride epitaxy. When a III-V material film is heterogeneously grown on a silicon substrate, due to the large thermal mismatch between the epitaxial film and the substrate, sufficient compressive stress needs to be stored during high-temperature epitaxial growth in order to obtain an epitaxial wafer with low warpage. Compensate for the tensile stress caused by thermal mismatch during cooling. For example, when epitaxially growing gallium nitride on a silicon substrate, insufficient stored compressive stress will cause cracks on the surface of the epitaxial wafer, affecting the quality and yield of the epitaxial wafer. The compressive stress that can be stored on a silicon substrate during high-temperature epitaxial growth of gallium nitride is limited. Excessive compressive stress will cause plastic deformation of the silicon substrate and ultimately affect the warpage of the epitaxial wafer.

Contents of the invention

In order to reduce the impact of large thermal mismatch between the epitaxial film and the substrate on the quality of the epitaxial structure, the present disclosure provides an epitaxial structure and a preparation method thereof.

In one aspect of the present disclosure, an epitaxial structure is provided, which includes:

A silicon substrate having a first surface;

An epitaxial layer, the epitaxial layer is provided on the first surface;

The epitaxial layer includes a plurality of sub-epitaxial layers and grid-shaped cracks, the plurality of sub-epitaxial layers are configured to be separated by the grid-shaped cracks, and the material of the epitaxial layer is a III-V group material.

In one aspect of the present disclosure, an epitaxial structure is provided, which includes:

A silicon substrate having a first surface and a second surface facing away from the first surface;

An epitaxial layer, the epitaxial layer is provided on the first surface;

The epitaxial layer includes a plurality of sub-epitaxial layers and grid-like cracks, the plurality of sub-epitaxial layers are configured to be separated by the grid-shaped cracks, and the material of the epitaxial layer is a III-V group material;

The second surface is provided with a grid-like pattern that is depressed toward the first surface, and the projection of the grid-like cracks on the second surface coincides or overlaps with the grid-like pattern.

In one aspect of the present disclosure, an epitaxial structure is provided, which includes:

A silicon substrate having a first surface;

An epitaxial layer, the epitaxial layer is provided on the first surface;

The epitaxial layer includes a plurality of sub-epitaxial layers and grid-like cracks, the plurality of sub-epitaxial layers are configured to be separated by the grid-shaped cracks, and the material of the epitaxial layer is a III-V group material;

A grid-like pattern buried layer is provided inside the silicon substrate, and the projection of the grid-like cracks on the plane of the grid-like pattern buried layer coincides or overlaps with the grid-like pattern buried layer.

One aspect of the present disclosure provides a method for preparing an epitaxial structure, including the following steps:

Provide a silicon substrate, the silicon substrate having a first surface and a second surface away from the first surface, the second surface being provided with a grid-like pattern that is recessed toward the first surface;

Several sub-epitaxial growths are performed on the first surface of the silicon substrate, and an epitaxial layer is obtained on the first surface of the silicon substrate. The epitaxial layer includes several sub-epitaxial layers and grid-like cracks. The plurality of sub-epitaxial growths are The epitaxial layer is configured to be separated by the grid-like cracks, the material of the epitaxial layer is a III-V group material, and the projection of the grid-like cracks on the second surface is consistent with the grid-like pattern. coincide or overlap.

One aspect of the present disclosure provides a method for preparing an epitaxial structure, including the following steps:

A silicon substrate is provided, the silicon substrate has a first surface, and a grid-like pattern buried layer is provided inside the silicon substrate;

Perform epitaxial growth several times to obtain an epitaxial layer on the first surface of the silicon substrate. Perform sub-epitaxial growth several times on the first surface of the silicon substrate to obtain an epitaxial layer. The epitaxial layer includes several sub-epitaxial layers. and grid-shaped cracks, the plurality of sub-epitaxial layers are configured to be separated by the grid-shaped cracks, the material of the epitaxial layer is a III-V group material; the grid-shaped cracks are in the grid-shaped The projection of the pattern buried layer on the plane coincides or overlaps with the grid-shaped pattern buried layer.

The epitaxial layer of the present disclosure has grid-like cracks. Using the epitaxial structure and the preparation method of the epitaxial structure of the present disclosure, since the grid-like cracks are orderly, the mismatched tensile stress of the epitaxial layer is released in an orderly manner, and high temperature is reduced. The silicon substrate warps during epitaxial growth.

Description of the drawings

Figure 1 is a schematic diagram of the preparation process of the epitaxial structure of the present disclosure;

Figure 2 is a schematic diagram of the preparation process of another epitaxial structure of the present disclosure;

Figure 3 is a partially enlarged schematic diagram of the epitaxial layer and its grid-mounted cracks of the present disclosure;

Figure 4 is a schematic structural diagram of the first epitaxial structure of the present disclosure;

Figure 5 is a schematic structural diagram of the second epitaxial structure of the present disclosure;

Figure 6 is a schematic structural diagram of the third epitaxial structure of the present disclosure;

Among them, 1. Silicon substrate, 11. Grid pattern, 12. First silicon wafer, 13. Second silicon wafer, 2. Nitride buffer layer, 21. First nitride film, 22. First crack, 23 , the second nitride film, 24. the second crack, 3. the device functional layer, 31. the HEMT device functional layer, 32. the third crack, 33. the LED device functional layer, 4. grid-like cracks, 40. epitaxial layer , 41. Sub-epitaxial layer.

Detailed ways

The present disclosure will be further described in detail below with reference to the accompanying drawings and examples; however, an epitaxial structure and its preparation method of the present disclosure are not limited to these embodiments.

Some embodiments of the present disclosure provide a method for preparing an epitaxial structure, including the following steps:

Provide a silicon substrate, the silicon substrate having a first surface and a second surface away from the first surface, the second surface being provided with a grid-like pattern that is recessed toward the first surface;

Several times of epitaxial growth are performed to obtain an epitaxial layer on the first surface of the silicon substrate. The epitaxial layer includes several sub-epitaxial layers and grid-like cracks. The several sub-epitaxial layers are configured by the grid-shaped cracks. The cracks are separated, the material of the epitaxial layer is a III-V group material, and the projection of the grid-shaped cracks on the second surface coincides or overlaps with the grid-shaped pattern. The overlap means that the projection of the grid-like cracks on the second surface is the same size and position as the grid-like pattern, and the overlap means that the projection of the grid-like cracks on the second surface is the same. The projections are not the same size as the grid-like pattern, but are partially aligned and superimposed.

The preparation method of the epitaxial structure according to the embodiment of the present disclosure is because the silicon substrate has a grid-like pattern on the second surface that is away from the first surface of the epitaxial growth, and because the grid-like pattern has a definite pattern, the epitaxial growth is It can induce the epitaxial layer to grow along the grid-like pattern, so that the release of thermal mismatch tensile stress can be controlled in an orderly manner during the epitaxial growth process, instead of causing the release of thermal mismatch tensile stress to appear in a disordered state and produce Disordered cracks and corresponding patterns on the second surface can also make the epitaxial growth more continuous, reduce defects, eliminate the need for secondary epitaxy, and save processes.

During the epitaxial growth process, the thermal mismatch tensile stress in the growth of the epitaxial layer is released through grid-like pattern control. The grid-like cracks of the epitaxial layer correspond to the grid-like pattern one-to-one. Therefore, in some embodiments, , the projection of the grid-shaped cracks on the second surface completely falls within the grid-shaped pattern, and the projection of the grid-shaped cracks on the second surface overlaps with the grid-shaped pattern . Since at the beginning of each epitaxial growth, grid-like cracks corresponding to the grid-like pattern will be generated, the final epitaxial layer is separated by these grid-like cracks, forming the grid-like cracks. separated sub-epitaxial layers.

In some embodiments, the grid units of the grid-like pattern are parallelograms. For example, in some embodiments, the grid units of the grid-like cracks are rectangles, squares, etc. In order to achieve better stress relief effect and meet the requirements of later chip manufacturing process. In some embodiments, the distance between two opposite sides in the grid unit is 100um-10mm. In some embodiments, the depth of the grid pattern is 10-200um. In some embodiments, the silicon substrate is a silicon (111) silicon wafer, and the grid lines on the grid pattern are configured to extend along the <110> crystallographic direction of the silicon substrate. Because the cubic symmetry of the Si (111) plane is conducive to the epitaxial growth of hexagonally close-packed (0001) plane III-V group films. The two main technical difficulties in the heteroepitaxial growth of III-V films on silicon (111) substrates are: the huge thermal mismatch between the silicon substrate and the III-V films makes the growth of III-V films on the silicon substrate The warpage of the material is difficult to control and cracks are easy to occur on the surface of the epitaxial wafer. Limited by the mechanical strength of the silicon substrate at high temperatures, the thickness of silicon-based gallium nitride epitaxial films is generally less than 6um. When epitaxially growing III-V materials at high temperatures, it can The stored compressive stress is limited. Excessive compressive stress will cause plastic deformation of the silicon substrate and ultimately affect the warpage of the epitaxial wafer. In some embodiments, for example, when a III-V group film is grown on a silicon substrate, cracks in the epitaxial film caused by thermal mismatch tensile stress generally start from the edge and extend toward the center of the substrate along the atomic close-packing direction: [11 -2 0 ],[-1 2 -1 0],[2 -1-1 0]. In silicon-based III-V epitaxy, the crystal orientation of the silicon (111) substrate corresponding to the direction of cracks caused by thermal mismatch in the III-V film is <110>. In order to control the release of thermal mismatch stress in a more orderly manner, in some embodiments, the grid lines on the grid-like pattern are configured to extend along the <110> crystallographic direction of the second surface. In some embodiments, the grid cells are diamond-shaped. In embodiments of the present disclosure, the material type and structure of the epitaxial layer can be flexibly selected according to the epitaxial structure that needs to be prepared. In some embodiments, the epitaxial layer includes a nitride buffer layer disposed on the first surface of the silicon substrate. In other embodiments, the epitaxial layer includes a nitride buffer layer disposed on the first surface of the silicon substrate and a device functional layer disposed on the nitride buffer layer. In some embodiments, the nitride buffer layer is a stack composed of one or more groups of AlN, AlGaN, and GaN. In some embodiments, the device functional layer is a HEMT device functional layer. Depending on the stage at which the epitaxial structure is obtained, for example, it can be a GaN and AlGaN heterojunction layer, or it can also be a GaN and AlGaN heterojunction layer and grown on GaN and AlGaN. GaN cap layer on AlGaN heterojunction layer. In some embodiments, the device functional layer is an LED device functional layer. In some embodiments, the LED device functional layer is an InGaN and GaN multi-quantum well stack.

In some embodiments, epitaxial growth may be performed several times on the first surface of the silicon substrate. In some embodiments, each epitaxial growth step includes: providing a growth surface, growing an epitaxial material at a high temperature on the growth surface, and lowering the temperature to induce the grid-like cracks in the epitaxial material. In some embodiments, during the first epitaxial growth, the first surface is used as the growth surface, a layer of epitaxial material is first grown at a high temperature, and then the temperature is lowered so that the grown epitaxial material generates grid-like cracks along the grid-like pattern. And the thermal mismatch tensile stress of the epitaxial material is released at the grid-like cracks. In some embodiments, in several subsequent epitaxial growth processes, the surface where the epitaxial material was produced in the previous time is used as the growth surface, another layer of epitaxial material is grown, and then the temperature is cooled so that the grown epitaxial material grows along the grid-shaped surface. The pattern corresponds to the grid-like cracks and causes the thermal mismatch tensile stress of the epitaxial material to be released at the grid-like cracks. The latter grid-like cracks are also induced corresponding to the grid-like pattern, so they are different from the previous grid. Corresponding to the location where the cracks are generated, the epitaxial material is separated into several sub-layers. The final epitaxial layer includes several sub-epitaxial layers separated by grid-like cracks. Specifically, in some embodiments, in the process of growing the buffer layer, during the first epitaxial growth, a layer of AlN material is grown on the first surface at high temperature, and then the temperature is lowered so that the grown AlN material is formed along the grid-shaped The pattern corresponds to grid-like cracks and allows the thermal mismatch tensile stress of the epitaxial material to be released at the grid-like cracks. The number of subsequent epitaxial growths is determined by the thickness and process of the AlN material. That is, the AlN material of the corresponding thickness can be grown at one time and then other materials can be continued to grow using the AlN material as the growth surface (for example, AlGaN can be grown once or multiple times. After growing AlGaN and then growing GaN one or more times), you can also grow AlN material to a certain thickness multiple times, then grow AlGaN one or more times and grow GaN one or more times. In some embodiments, the above-mentioned process is used to grow the buffer layer. A buffer layer composed of AlN, AlGaN and GaN is epitaxially grown. Multiple sub-layers of AlN, AlGaN and GaN superimposed can also be epitaxially grown to form a buffer layer. Likewise, in some embodiments, the above-described process is used to epitaxially grow device functional layers. The preparation process of a specific embodiment will be described in detail below by taking the epitaxial growth of GaN-based HEMT epitaxial wafers on a silicon substrate as an example.

The preparation process of epitaxially growing GaN-based HEMT epitaxial wafers on silicon substrates is shown in Figure 1, including the following steps:

(1) Select a 6-inch silicon substrate 1 with a thickness of 1000um, a resistivity of 0.01ohm.cm, and a silicon (111) surface, and use ICP etching equipment to etch on the back side of the silicon substrate 1 (i.e., the second surface) A grid pattern 11 is etched (as shown in Figure 1-b). The etching depth of the grid pattern 11 is 100um. The grid units of the grid pattern 11 are parallelograms, specifically rhombuses, and The distance between the two opposite sides in the grid unit is 2mm, and the adjacent sides of the grid unit are along the [1-10] and [0-11] directions of silicon respectively; use the RCA method to clean the surface of silicon substrate 1 and Spin dry for nitride epitaxy;

(2) Use MOCVD to grow a 200nm AlN layer on the surface of the above silicon substrate at a high temperature of 1080°C, and then lower the temperature to 1000°C to grow 300nm Al0.75Ga0.25N, 600nm Al0.5Ga0.5N and 800nm Al0.2Ga0. 8N layer; then lower the temperature to 980°C to grow a 1800nm GaN layer to obtain the first nitride film 21 (as shown in Figure 1-c);

(3) The temperature is lowered to 200°C, and the tensile stress caused by the thermal mismatch between the silicon substrate and the nitride is used to form grid-like first cracks 22 on the surface of the above-mentioned first nitride film 22 (as shown in Figure 1-d). to release tensile stress;

(4) Continue to raise the temperature to 1000°C to grow 20nm AlN, 300nm Al0.5Ga0.5N, 500nm Al0.2Ga0.8N and 1800nm GaN layers to obtain the second nitride film 23 (as shown in Figure 1-e);

(5) The temperature is lowered to 200°C, and the tensile stress caused by the thermal mismatch between the silicon substrate and the nitride is used to form grid-like second cracks 24 on the surface of the second nitride film 23 (as shown in Figure 1-f). to release tensile stress;

(6) Use MOCVD to raise the temperature to 1050°C and continue to continue high-temperature epitaxial growth of 300 nm GaN and 20 nm GaN on the nitride buffer layer 2 (composed of the first nitride film 21 and the second nitride film 23) obtained in step (5). The Al0.25Ga0.75N barrier layer and the 3nm GaN cap layer are used to obtain the HEMT device functional layer 31 (as shown in Figure 1-g);

(7) The temperature is lowered to room temperature, causing the HEMT device functional layer 31 to form a grid-shaped third crack 32 (as shown in Figure 1-h).

The first crack 22, the second crack 24 and the third crack 31 correspond up and down, and the projections of the first crack 22, the second crack 24 and the third crack 31 on the second surface overlap and completely fall. into the grid-like pattern 11, therefore, the first cracks 22, the second cracks 24 and the third cracks 31 together constitute the grid-like cracks.

Some embodiments of the present disclosure provide a method for preparing an epitaxial structure, including the following steps:

A silicon substrate is provided, the silicon substrate has a first surface, and a grid-like pattern buried layer is provided inside the silicon substrate;

Several epitaxial growths are performed on the first surface of the silicon substrate to obtain an epitaxial layer. The epitaxial layer includes a number of sub-epitaxial layers and grid-shaped cracks. The several sub-epitaxial layers are configured by the grid-shaped cracks. The cracks are separated, and the material of the epitaxial layer is a III-V group material; the projection of the grid-shaped cracks on the plane where the grid-shaped pattern buried layer is coincident or overlaps with the grid-shaped pattern buried layer.

Different from the preparation method of the epitaxial structure provided by the above embodiments, some embodiments of the present disclosure are provided with a grid-like pattern buried layer inside the silicon substrate, so that the epitaxial layer can be induced to grow along the Growth in a grid-like pattern allows the release of thermal mismatch tensile stress to be controlled in an orderly manner during the epitaxial growth process, instead of causing the release of thermal mismatch tensile stress to appear in a disordered state and produce disordered cracks. The method of arranging a grid-like pattern buried layer inside the silicon substrate can also make the epitaxial growth more continuous, reduce defects, eliminate the need for secondary epitaxy, and save processes.

Specifically, in some embodiments,

The silicon substrate includes a first silicon wafer and a second silicon wafer. The second silicon wafer has the first surface and a second surface away from the first surface. The first silicon wafer has a third surface. , the second surface of the second silicon wafer is overlapped with the third surface of the first silicon wafer by providing a grid-like pattern that is recessed toward the direction of the first surface on the second surface, so that The gap generated between the second surface of the second silicon wafer and the third surface of the first silicon wafer forms the grid-like pattern buried layer.

In some embodiments, the second silicon wafer is a silicon (111) silicon wafer; in some embodiments, the second silicon wafer and the first silicon wafer are silicon (111) silicon wafers.

Specifically, in some embodiments, the silicon substrate includes a first silicon wafer and a second silicon wafer, the second silicon wafer has the first surface and a second surface away from the first surface, so The first silicon wafer has a third surface and a fourth surface away from the third surface, and a grid-like pattern recessed toward the fourth surface is provided on the third surface; the second silicon wafer is The second surface of the wafer is overlapped with the third surface of the first silicon wafer, so that the gap generated between the second surface of the second silicon wafer and the third surface of the first silicon wafer forms the network. Grid pattern buried layer. In some embodiments, the second silicon wafer and the first silicon wafer are silicon (111) silicon wafers. The preparation process of a specific embodiment of the present disclosure will be described in detail below by taking the epitaxial growth of GaN-based LED epitaxial wafers on a silicon substrate as an example.

The preparation process of epitaxially growing GaN-based LED epitaxial wafers on silicon substrates is shown in Figure 2, including the following steps:

(1) Select a first silicon wafer 12 with a thickness of 750um, an N-type doping resistivity of 0.02ohm.cm, and a 6-inch silicon (111) surface, and then use the ICP method to place the first silicon wafer 12 on the front side (that is, the so-called The third surface) is etched with a grid pattern 11 (as shown in Figure 2-b). The etching depth of the grid pattern 11 is 50um. The grid units of the grid pattern 11 are parallel. Quadrilateral, specifically a rhombus, and the distance between the two opposite sides in the grid unit is 1mm, and the adjacent sides of the grid unit are along the [1-10] and [0-11] directions of silicon respectively. ; Use the RCA method to clean the surface of the first silicon substrate 12 and spin dry;

(2) Select a second silicon wafer 13 with a thickness of 200um. The second silicon wafer 13 is a 6-inch double-polished substrate with a silicon (111) surface. Place the back side of the second silicon wafer 13 (that is, the second surface) and the front surface of the first silicon wafer 12 (that is, the third surface) are bonded at high temperature to obtain a silicon substrate 1 with a grid-like pattern buried layer inside (as shown in Figure 2-c) ; Clean the bonded silicon substrate 1 with RCA solution and dry it for nitride epitaxy;

(3) Use MOCVD to grow a 200nm AlN layer on the front surface of the silicon substrate 1 (ie, the first surface) at a high temperature of 1080°C, and then lower the temperature to 1000°C to grow 300nm Al0.75Ga0.25N and 400nm Al0.5Ga0.5N. and a 500nm Al0.2Ga0.8N layer; then lower the temperature to 980°C to grow a 1800nm GaN layer to obtain the first nitride film 21 (as shown in Figure 2-d);

(4) Cool the temperature to 200°C, and use the tensile stress of the thermal mismatch between the silicon substrate 1 and the nitride to form a grid-like first crack 22 on the surface of the first nitride film 22 (as shown in Figure 2-e) , to release tensile stress;

(5) Continue to raise the temperature to 1000°C to grow 20nm AlN, 300nm Al0.5Ga0.5N, 500nm Al0.2Ga0.8N and 2000nm Si-doped N-type GaN layers to obtain the second nitride film 23 (as shown in Figure 2-f shown);

(6) Cool the temperature to 200°C, and use the tensile stress of the thermal mismatch between the silicon substrate 1 and the nitride to form grid-like second cracks 24 on the surface of the second nitride film 23 (as shown in Figure 2-g). Release tensile stress;

(7) Use MOCVD to raise the temperature to 780°C and continue to grow In0.17Ga0 on the nitride buffer layer 2 (composed of the first nitride film 21 and the second nitride film 23) obtained in step (6) for 5 cycles. 83N/GaN multiple quantum well layer, in which the thickness of the GaN barrier layer is 12nm and the thickness of the In0.17Ga0.83N potential well layer is 3nm; then the temperature is raised to 880°C to grow a 150nm Mg-doped P-type GaN cap layer to obtain the functional layer of the LED device 33 (shown in Figure 2-h);

(8) Cooling to room temperature causes the LED device functional layer 33 to form a grid-shaped third crack 32 (as shown in Figure 2-i).

The first crack 22 , the second crack 24 and the third crack 32 correspond up and down, and the projections of the first crack 22 , the second crack 24 and the third crack 32 on the second surface overlap and completely fall. into the grid-like pattern 11, therefore, the first cracks 22, the second cracks 24 and the third cracks 32 together constitute the grid-like cracks.

Please refer to Figures 3 and 4. In some embodiments, an epitaxial structure of the present disclosure includes:

Silicon substrate 1, said silicon substrate 1 having a first surface;

Epitaxial layer 40, the epitaxial layer 40 is provided on the first surface;

The epitaxial layer 40 includes a plurality of sub-epitaxial layers 41 and grid-like cracks 4. The plurality of sub-epitaxial layers 41 are configured to be separated by the grid-shaped cracks 4. The material of the epitaxial layer 40 is III-V. family material.

In the embodiment of the present disclosure, the grid-shaped cracks 4 have an ordered structure. In some embodiments, the epitaxial layer includes a nitride buffer layer disposed on the first surface of the silicon substrate. In other embodiments, the epitaxial layer 40 includes a nitride buffer layer 2 disposed on the first surface of the silicon substrate 1 and a device functional layer 3 disposed on the nitride buffer layer 2, as shown in FIG. 4 shown. In some embodiments, the nitride buffer layer is a stack composed of one or more groups of AlN, AlGaN, and GaN. In some embodiments, the device functional layer is a HEMT device functional layer. Depending on the stage at which the epitaxial structure is obtained, for example, it can be a GaN and AlGaN heterojunction layer, or it can also be a GaN and AlGaN heterojunction layer and grown on GaN and AlGaN. GaN cap layer on AlGaN heterojunction layer. In some embodiments, the device functional layer is an LED device functional layer. In some embodiments, the LED device functional layer is an InGaN and GaN multi-quantum well stack.

In embodiments of the present disclosure, different epitaxial structures can be used as needed, and the material type and structure of the epitaxial layer can be flexibly selected. In some embodiments, the epitaxial layer includes a nitride buffer layer disposed on the first surface of the silicon substrate. In other embodiments, in this embodiment, the epitaxial layer 40 includes a nitride buffer layer 2 disposed on the first surface of the silicon substrate 1 and a nitride buffer layer 2 disposed on the nitride buffer layer 2 . Device functional layer 3, as shown in Figure 1. In some embodiments, the nitride buffer layer is a stack composed of one or more groups of AlN, AlGaN, and GaN. In some embodiments, the device functional layer is a HEMT device functional layer. Depending on the stage at which the epitaxial structure is obtained, for example, it can be a GaN and AlGaN heterojunction layer, or it can also be a GaN and AlGaN heterojunction layer and grown on GaN. and GaN cap layer on AlGaN heterojunction layer. In some embodiments, the device functional layer is a LED device functional layer. In some embodiments, the LED device functional layer is an InGaN and GaN multi-quantum well stack.

An epitaxial structure of the present disclosure can be prepared by using the above-mentioned preparation method of an epitaxial structure of the present disclosure, and then the silicon substrate is thinned to remove the grid pattern or grid pattern buried layer of the silicon substrate. The epitaxial structure of the embodiment is obtained. Since during the epitaxial growth process, the thermal mismatch tensile stress in the growth of the epitaxial layer is released through grid pattern control, and the grid cracks of the epitaxial layer correspond to the grid pattern one-to-one, therefore, in some embodiments, In The grid-like patterns overlap. Since at the beginning of each epitaxial growth, grid-like cracks corresponding to the grid-like pattern will be generated, the final epitaxial layer is separated by these grid-like cracks, forming a structure separated by the grid-like cracks. Open sub-epitaxial layer. Since the release of thermal mismatch tensile stress is controlled in an orderly manner during the epitaxial growth process, instead of causing the release of thermal mismatch tensile stress to appear in a disordered state and produce disordered cracks, the epitaxial growth method of the embodiment of the present disclosure is adopted. The structure has fewer defects (reduced dislocation density, threading dislocations in the epitaxial film), better thickness uniformity and reduced substrate warpage.

Please refer to Figures 3 and 5. In some embodiments, the silicon substrate is not thinned. An epitaxial structure of the present disclosure includes:

A silicon substrate 1 having a first surface and a second surface facing away from the first surface;

Epitaxial layer 40, the epitaxial layer 40 is provided on the first surface;

The epitaxial layer 40 includes a plurality of sub-epitaxial layers 41 and grid-like cracks 4. The plurality of sub-epitaxial layers 41 are configured to be separated by the grid-shaped cracks 4. The material of the epitaxial layer 40 is III-V. family material;

The second surface is provided with a grid pattern 11 that is concave toward the first surface, and the projection of the grid cracks 4 on the second surface overlaps with the grid pattern 11 .

In some embodiments, the grid units of the grid-like pattern 11 are parallelograms. For example, in some embodiments, the grid units of the grid-like cracks are rectangles, squares, etc. In order to achieve better stress relief effect and meet the requirements of later chip manufacturing process. In some embodiments, the distance between two opposite sides in the grid unit is 100um-10mm. In some embodiments, the depth of the grid pattern is 10-200um. In some embodiments, the silicon substrate is a silicon (111) silicon wafer, and the grid lines on the grid pattern are configured to extend along the <110> crystallographic direction of the silicon substrate. Because the cubic symmetry of the Si (111) plane is conducive to the epitaxial growth of the hexagonally close-packed (0001) plane GaNIII-V family film. The two main technical difficulties in the heteroepitaxial growth of III-V GaN-based films on silicon (111) substrates are: the huge thermal mismatch between the silicon substrate and the III-V gallium nitride film makes the When growing III-V gallium nitride materials, warpage is difficult to control and cracks are easy to occur on the surface of the epitaxial wafer. This is limited by the mechanical strength of the silicon substrate at high temperatures. The thickness of silicon-based gallium nitride epitaxial films is generally less than 6um. In high-temperature epitaxy, The compressive stress that can be stored when growing III-V gallium nitride is limited. Excessive compressive stress will cause plastic deformation of the silicon substrate and ultimately affect the warpage of the epitaxial wafer. In some embodiments, for example, when a III-V group film is grown on a silicon substrate, cracks in the epitaxial film caused by thermal mismatch tensile stress generally start from the edge and extend toward the center of the substrate along the atomic close-packing direction: [1 1 -2 0],[-1 2 -1 0],[2 -1-1 0]. In silicon-based III-V epitaxy, the crystal orientation of the silicon (111) substrate corresponding to the direction of cracks caused by thermal mismatch in the III-V film is <110>. In order to control the release of thermal mismatch stress in a more orderly manner, in some embodiments, the grid lines on the grid-like pattern are configured to extend along the <110> crystallographic direction of the second surface. In some embodiments, the grid unit is specifically rhombus-shaped, and the distance between two opposite sides of the grid unit is 100um-10mm. The depth of the grid pattern is 10-200um.

Please refer to Figures 3 and 6. In some embodiments, the substrate is not thinned. An epitaxial structure of the present disclosure includes:

Silicon substrate 1, said silicon substrate 1 having a first surface;

Epitaxial layer 40, the epitaxial layer 40 is provided on the first surface;

The epitaxial layer 40 includes a plurality of sub-epitaxial layers 41 and grid-like cracks 4. The plurality of sub-epitaxial layers 41 are configured to be separated by the grid-shaped cracks 4. The material of the epitaxial layer 40 is III-V. family material;

A grid-like pattern buried layer is provided inside the silicon substrate 1 , and the projection of the grid-like cracks 4 on the plane of the grid-like pattern buried layer overlaps with the grid-like pattern buried layer.

Specifically, in some embodiments,

In this embodiment, the projection of the grid-shaped cracks 4 on the plane where the grid-shaped pattern buried layer overlaps the grid-shaped pattern buried layer, and the grid-shaped cracks 4 are located on the grid-shaped buried layer. The projection on the plane of the grid-shaped pattern buried layer completely falls into the grid-shaped pattern buried layer.

In this embodiment, the silicon substrate 1 includes a first silicon wafer 12 and a second silicon wafer 13. The second silicon wafer 13 has the first surface and a second surface away from the first surface, The first silicon wafer 12 has a third surface and a fourth surface facing away from the third surface,

A recessed grid-like pattern is provided on the second surface or the third surface, and the second surface of the second silicon wafer overlaps the third surface of the first silicon wafer, so that the second surface of the second silicon wafer overlaps with the third surface of the first silicon wafer. The gap generated between the second surface of the silicon wafer and the third surface of the first silicon wafer forms the grid-like pattern buried layer.

In some embodiments, the second silicon wafer is a silicon (111) silicon wafer; in some embodiments, the second silicon wafer and the first silicon wafer are silicon (111) silicon wafers.

Specifically, in some embodiments, the third surface is provided with a grid-like pattern 11 that is recessed toward the fourth surface; the second surface of the second silicon wafer 13 is connected to the first surface. The third surface of the silicon wafer 12 is overlapped, so that the gap generated between the second surface of the second silicon wafer 13 and the third surface of the first silicon wafer 12 forms the grid-like pattern buried layer. In some embodiments, the second silicon wafer 13 and the first silicon wafer 12 are silicon (111) silicon wafers.

In some embodiments, the epitaxial layer includes a nitride buffer layer disposed on the first surface of the silicon substrate. In other embodiments, the epitaxial layer 40 includes a nitride buffer layer 2 disposed on the first surface of the silicon substrate 1 and a device functional layer 3 disposed on the nitride buffer layer 2, as shown in FIG. 6 shown. In some embodiments, the nitride buffer layer is a stack composed of one or more groups of AlN, AlGaN, and GaN. In some embodiments, the device functional layer is a HEMT device functional layer. Depending on the stage at which the epitaxial structure is obtained, for example, it can be a GaN and AlGaN heterojunction layer, or it can also be a GaN and AlGaN heterojunction layer and grown on GaN and AlGaN. GaN cap layer on AlGaN heterojunction layer. In some embodiments, the device functional layer is an LED device functional layer. In some embodiments, the LED device functional layer is an InGaN and GaN multi-quantum well stack.

In some embodiments, the grid units of the grid-like pattern 11 are parallelograms. For example, in some embodiments, the grid units of the grid-like cracks are rectangles, squares, etc. In order to achieve better stress relief effect and meet the requirements of later chip manufacturing process. In some embodiments, the distance between two opposite sides in the grid unit is 100um-10mm. In some embodiments, the depth of the grid pattern is 10-200um. In some embodiments, the silicon substrate is a silicon (111) silicon wafer, and the grid lines on the grid pattern are configured to extend along the <110> crystallographic direction of the silicon substrate. Because the cubic symmetry of the Si (111) plane is conducive to the epitaxial growth of the hexagonally close-packed (0001) plane GaNIII-V family film. The two main technical difficulties in the heteroepitaxial growth of III-V GaN-based films on silicon (111) substrates are: the huge thermal mismatch between the silicon substrate and the III-V gallium nitride film makes the When growing III-V gallium nitride materials, warpage is difficult to control and cracks are easy to occur on the surface of the epitaxial wafer. This is limited by the mechanical strength of the silicon substrate at high temperatures. The thickness of silicon-based gallium nitride epitaxial films is generally less than 6um. In high-temperature epitaxy, The compressive stress that can be stored when growing III-V gallium nitride is limited. Excessive compressive stress will cause plastic deformation of the silicon substrate and ultimately affect the warpage of the epitaxial wafer. In some embodiments, for example, when a III-V group film is grown on a silicon substrate, cracks in the epitaxial film caused by thermal mismatch tensile stress generally start from the edge and extend toward the center of the substrate along the atomic close-packing direction: [1 1 -2 0],[-1 2 -1 0],[2 -1-1 0]. In silicon-based III-V epitaxy, the crystal orientation of the silicon (111) substrate corresponding to the direction of cracks caused by thermal mismatch in the III-V film is <110>. In order to control the release of thermal mismatch stress in a more orderly manner, in some embodiments, the grid lines on the grid-like pattern are configured to extend along the <110> crystallographic direction of the second surface. In some embodiments, the grid unit is specifically rhombus-shaped, and the distance between two opposite sides of the grid unit is 100um-10mm. The depth of the grid pattern is 1-100um.

The above embodiments are used to further illustrate an epitaxial structure and its preparation method of the present disclosure. However, the present disclosure is not limited to the above embodiments. Any simple modifications or equivalent changes to the above embodiments can be made based on the technical essence of the present disclosure. and modifications, all fall within the protection scope of the technical solution of the present disclosure.

Claims (10)

1. An epitaxial structure, comprising:

a silicon substrate having a first surface and a second surface facing away from the first surface, wherein the first surface is planar;

the epitaxial layer is arranged on the first surface;

the epitaxial layer includes a number of sub-epitaxial layers and a number of patterned cracks, each of the number of sub-epitaxial layers being configured to be separated by the patterned cracks in a direction away from the silicon substrate.

2. The epitaxial structure of claim 1, wherein,

the second surface is provided with a pattern recessed towards the first surface, and the projection of the patterned crack on the second surface is overlapped with or overlapped with the pattern.

3. The epitaxial structure of claim 1, wherein,

and a pattern buried layer is arranged in the silicon substrate, and the projection of the pattern crack on the plane of the pattern buried layer is overlapped with or overlapped with the pattern buried layer.

4. The epitaxial structure of claim 2, wherein the silicon substrate is a silicon (111) wafer and the pattern disposed on the second surface comprises a plurality of first pattern lines configured to extend along a <110> crystal orientation of the silicon substrate.

5. An epitaxial structure according to claim 3, wherein the silicon substrate is a silicon (111) wafer, and the patterned buried layer provided inside the silicon substrate comprises a plurality of first pattern lines configured to extend along a <110> crystal orientation of the silicon substrate.

6. The epitaxial structure of any one of claims 1 to 5, wherein the patterned crack is a grid-like patterned crack.

7. The epitaxial structure of claim 6, wherein the patterned crack is a diamond patterned crack, the pattern disposed on the second surface is a diamond pattern, adjacent sides of grid cells of the diamond pattern being configured in [1-10] and [0-11] directions of silicon, respectively.

8. The epitaxial structure of claim 6, wherein the patterned crack is a diamond patterned crack, the buried patterned layer disposed within the silicon substrate is a diamond patterned buried layer, and adjacent sides of the grid cells of the diamond patterned buried layer are configured in the [1-10] and [0-11] directions of silicon, respectively.

9. The epitaxial structure of claim 1, wherein the material of each of the plurality of sub-epitaxial layers is a group III-V material.

10. The epitaxial structure of claim 1, wherein the epitaxial layer comprises a nitride buffer layer disposed on the first surface of the silicon substrate and a HEMT device functional layer or an LED device functional layer disposed on the nitride buffer layer.