CN116796679A - A multi-voltage domain CMOS IO design - Google Patents

Abstract

The invention relates to the technical field of integrated circuit design, and specifically to a multi-voltage domain CMOS IO design. In this design, the IO can work in multiple voltage domains. The core of the circuit is the driver of the PMOS tube, including: a driver circuit with two PMOS tubes connected in series, as well as a PGATE voltage generation circuit, an FBK generation circuit, an adaptive circuit, a VGND voltage generation circuit, and a controllable PGATE voltage generation circuit and FBK voltage generation circuit. The PGATE control switch voltage generation circuit enables it to meet multiple voltage requirements. The design of this circuit greatly improves the flexibility of the circuit, and does not require a special voltage conversion circuit, saving cost, power consumption, and It reduces the size of the system and has great practical value.

Description

A multi-voltage domain CMOS IO design

Technical field

The invention relates to the technical field of integrated circuit design, and specifically to a multi-voltage domain CMOS IO design.

Background technique

If the current IO wants to interact with external circuits of different voltages, there are several solutions: 1. The MOS tube of the IO circuit can support the required voltage, but this kind of MOS tube is usually a high-voltage MOS tube. In SOC, it is usually This kind of MOS tube is not used, so it usually cannot be used in SOC; 2. The IO circuit can only tolerate external high-voltage input, because the IO circuit can only tolerate external high-voltage input, but it cannot output high-voltage ;3. Make a voltage conversion circuit inside the PCB or SOC, but this will increase the cost and increase the area and power consumption of the entire circuit. Faced with the above solutions and the shortcomings of various solutions, a chip that can support multiple voltages is needed.

Contents of the invention

In view of the shortcomings of the existing technology, the present invention provides a technical solution, which can use lower voltage MOS tubes to design multi-voltage IOs, which are truly low-cost, low-power consumption and can be integrated in SOC, solving the current problem. Defects.

The technical solution adopted by the present invention is as follows: a multi-voltage domain CMOS IO design, including two series-connected PMOS tubes as drive circuits. The gate of one of them is marked as PGATE, the gate of the other is marked as FBK, and the gate is marked as FBK. The source of the PMOS tube for PGATE is connected to VDDPST, which is characterized in that: the PGATE is connected to multiple PGATE voltage generating circuits, and FBK is connected to multiple FBK generating circuits; each PGATE voltage generating circuit and each FBK voltage generating circuit The circuit is connected to PGATE and FBK through switches. The circuit also includes an adaptive circuit and a VGND voltage generating circuit. The VGND voltage generating circuit is used to generate a variable VGND voltage signal; the multiple PGATE voltage generating circuits and the multiple PGATE control switch voltage generating circuits are combined with the adaptive circuit and VGND Voltage generating circuit connections.

Further, the output of the adaptive circuit includes the inter_power voltage signal and the inter_gnd voltage signal.

Further, the PGATE voltage generation circuit includes 1.8V, 2.5V and 3.3V voltage generation circuits.

Further, the PGATE control switch voltage generation circuit includes control switch voltage generation circuits of 1.8V, 2.5V and 3.3V voltage generation circuits.

Further, the adaptive circuit includes three PMOS and one NMOS tubes connected in series, where the first three PMOS tubes are all in diode mode; the gate of the NMOS tube is connected to 1.8V. The first PMOS tube is used to generate the inter_power voltage signal, and the second PMOS tube is used to generate the inter_gnd voltage signal.

Further, the VGND voltage comes from VDD or VGND. There are two switches for selection, and the control voltages of the switches are recorded as: PEFBK_P, PEFBK_N, PEFBK_N and PEFBK_P.

Further, the FBK voltage comes from VDD, VDD18_POST and VSSPST_POST. Selection is made through three switches. The MOS control voltages of the switches are: PS_P, PS_N, PEFBK_P, PEFBK_N, HEFBK_P and HEFBK_N.

Beneficial effects: In a chip design, IO can work in a variety of voltage domains. The core of the circuit is the driver of the PMOS tube, including: a driver circuit of two PMOS tubes connected in series, as well as a PGATE voltage generation circuit, FBK generation circuit, and adaptive circuit, VGND voltage generation circuit, and PGATE control switch voltage generation circuit that can control the PGATE voltage generation circuit and FBK voltage generation circuit, so that it can meet multiple voltage requirements. The design of this circuit greatly improves the flexibility of the circuit. Moreover, there is no need for a special voltage conversion circuit, which saves cost, power consumption, and reduces the size of the system, which has great practical value.

Description of the drawings

Figure 1 is a schematic diagram of a PMOS drive circuit according to an embodiment of the present invention;

Figure 2 is a schematic diagram of an adaptive circuit according to an embodiment of the present invention;

Figure 3 is a schematic diagram of a 1.8V IO voltage PGATE voltage generation circuit according to an embodiment of the present invention;

Figure 4 is a schematic diagram of a 2.5V IO voltage PGATE voltage generation circuit according to an embodiment of the present invention;

Figure 5 is a schematic diagram of a 3.3V IO voltage PGATE voltage generation circuit according to an embodiment of the present invention;

Figure 6 is a schematic diagram of a VGND voltage generating circuit according to an embodiment of the present invention;

Figure 7 is a schematic diagram of the FBK voltage generation circuit according to the embodiment of the present invention;

Figure 8 is a schematic diagram of the FBK and PGATE control switch voltage generation circuit at 1.8V IO according to the embodiment of the present invention;

Figure 9 is a schematic diagram of the FBK and PGATE control switches and the vgnd control switch voltage generation circuit at 2.5V IO according to the embodiment of the present invention;

Figure 10 is a schematic diagram of the FBK and PGATE control switch voltage generation circuit at 3.3V IO according to the embodiment of the present invention;

Figure 11 is a simulation diagram of core and PAD signals at 1.8V voltage according to the embodiment of the present invention;

Figure 12 is a simulation diagram of core and PAD signals at 2.5V voltage according to the embodiment of the present invention;

Figure 13 is a simulation diagram of core and PAD signals at 3.5V voltage according to the embodiment of the present invention.

It is worth mentioning that the pins of each PMOS tube in Figure 1-10 have the same number, which means they are connected; the leftmost PS, PE and HE pins in Figure 8-10 extremely control the design. Control pin for output voltage.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art fall within the protection scope of the present invention.

As shown in Figure 1-10, a multi-voltage domain CMOS IO design includes two PMOS tubes connected in series as a drive circuit. The gate of one of them is marked as PGATE, and the gate of the other is marked as FBK. The gate is marked as The source of the PMOS tube for PGATE is marked as PAD, as the output, and the other ports are connected to the VDDPST signal; the PGATE is connected in parallel with multiple PGATE voltage generating circuits, and the FBK is connected with an FBK generating circuit; each PGATE voltage generating circuit It is also connected to a PGATE control switch voltage generation circuit that can control the PGATE voltage generation circuit and the FBK voltage generation circuit; it also includes an adaptive circuit and a VGND voltage generation circuit, and the VGND voltage generation circuit is used to generate a variable VGND voltage signal; the multiple A PGATE voltage generating circuit and a plurality of PGATE control switch voltage generating circuits are connected to the adaptive circuit and the VGND voltage generating circuit.

In this embodiment, the output of the adaptive circuit includes an inter_power voltage signal and an inter_gnd voltage signal.

In this embodiment, the PGATE voltage generating circuit includes voltage generating circuits of 1.8V, 2.5V and 3.3V.

In this embodiment, the PGATE control switch voltage generation circuit includes control switch voltage generation circuits of voltage generation circuits of 1.8V, 2.5V and 3.3V.

In this embodiment, the adaptive circuit includes four PMOS tubes connected in series. The first three PMOS tubes are connected in such a way that the source of the previous one is connected to the drain of the next one; the drain of the fourth PMOS tube is connected to the drain of the next PMOS tube. The sources of the three MPOS tubes, the source of the fourth PMOS tube is connected to VSS, the gate of the fourth PMOS tube is recorded as the VDD18 interface; the gate and source of the first PMOS tube are connected as the inter_power voltage signal interface , the gate and source of the second PMOS tube are connected as the inter_gnd voltage signal interface, and the gate and source of the third PMOS tube are connected.

In this embodiment, the VGND voltage generating circuit is a PMOS tube with four drains connected in parallel as the VGND output, the first two sources connected in parallel and connected to VDD, and the last two sources connected in parallel connected to the inter_gnd voltage signal interface; And the gates of the first to fourth PMOS tubes are respectively recorded as: PEFBK_P, PEFBK_N, PEFBK_N and PEFBK_P.

In this embodiment, the FBK voltage generation circuit has six drains connected in parallel as the FBK voltage signal output, the first two sources connected in parallel together as the VSSPST_POST interface, and the middle two sources connected in parallel as the VDD interface. , the last two sources are connected in parallel as PMOS tubes of the VDD 18_POST interface, and the gates of the first to sixth PMOS tubes are respectively recorded as: PS_P, PS_N, PEFBK_P, PEFBK_N, HEFBK_P and HEFBK_N.

It is worth noting that in the above description, such as "the gate of one of them is marked as PGATE", "the gate of the fourth PMOS tube is marked as VDD18 interface", "the gate and source of the second PMOS tube are Connection, "inter_gnd voltage signal interface", etc. are not used as a limitation, just to facilitate distinction and recording; the pins of each PMOS tube in Figure 1-10 have the same number, which means they are connected.

When using this IO design, as shown in Figure 8-10, there are three selection pins PS, PE and HE at the far left of each figure, corresponding to 1.8V, 2.5V and 3.3V respectively. Only one logic state can be 1 at the same time.

When the voltages of PAD are 1.8, 2.5 and 3.3, the corresponding voltages of FBK are 0, 0.9 and 3.3. At this time, you only need to make a selection between the switch control voltages generated by PS, PE, and HE, as shown in Figure 7.

The adaptive circuit shown in Figure 2 is used to generate inter_power and inter_gnd. This is an adaptive circuit, and the voltage value changes as VDDPST changes.

When VDDPST=2.5V, vgnd=0.9v, otherwise vgnd=inter_gnd.

Here are 3 PGATE voltage generating circuits:

At 1.8V, the control voltage of PGATE is 1.8 or 0V respectively. This is a normal 1.8VIO circuit. However, since the usage scenario is multi-voltage, a switch circuit is required. The voltages PS_N_GATE and PS_P_GATE that control the switches must change with the use voltage, otherwise you will face problems with reliability and incorrect functionality. Figure 8 is the circuit that generates this voltage. The change trajectory of the signal is [0.9 0]-->[1.8 0]-->[1.8 0.9]-->[inter_power,0.9]-->[inter_power,vgnd]-- >[VDDPST, vgnd].

At 2.5V, the control voltage of PGATE is 2.5 or vgnd respectively. Figure 4 is used to generate the voltage of PGATE. The change trajectory of the signal is [0.9 0]-->[1.8 0]-->[1.8 0.9]-->[VDDPST, vgnd]. By the same token, a switch is necessary to control whether this voltage is connected to PGATE. Figure 9 is the circuit that generates this voltage. The change trajectory of the signal is [0.9 0]-->[1.8 0]-->[1.8 0.9]- ->[inter_power,0.9]-->

[inter_power,vgnd]-->[VDDPST,vgnd].

At 3.3V, the control voltage of PGATE is 3.3 or 1.8 respectively. Figure 5 is used to generate the voltage of PGATE. The change trajectory of the signal is [0.9 0]-->[1.8 0]-->[1.8 0.9]-->[inter_power,0.9]-->[inter_power,1.8]-->[VDDPST, 1.8]. By the same token, a switch is necessary to control whether this voltage is connected to PGATE. Figure 10 is the circuit that generates this voltage. The change trajectory of the signal is [0.9 0]-->[1.8 0]-->[1.8 0.9]- ->[inter_power,0.9]-->[inter_power,1.8]-->[VDDPST, 1.8].

The circuit designed in this way allows the circuit to work under different voltages without reliability problems, and the performance under different voltages can be guaranteed.

As shown in Figure 11-13, the output waveforms of the PAD terminal in the driving circuit are at 1.8, 2.5, and 3.3V respectively. It can be seen that the function and performance are very good. The design of this circuit greatly improves the flexibility of the circuit, and does not require a special voltage conversion circuit, saving cost, power consumption, and reducing the size of the system, which has great practical value.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. All modifications, equivalent substitutions, improvements, etc. within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (7)

1. The utility model provides a many voltage domain CMOS IO designs, includes two PMOS pipes that establish ties as drive circuit, marks PGATE with the grid of one, and the grid of another marks FBK, and the source of the PMOS pipe that the grid marks PGATE is connected to VDDPST, its characterized in that: the PGATE is connected to a plurality of PGATE voltage generating circuits, and the FBK is also connected to a plurality of FBK generating circuits; each PGATE voltage generating circuit and each FBK voltage generating circuit is connected to the PGATE and the FBK through a switch; the circuit also comprises an adaptive circuit and a VGND voltage generation circuit, wherein the VGND voltage generation circuit is used for generating a variable VGND voltage signal; the PGATE voltage generating circuits and the PGATE control switch voltage generating circuits are connected with the adaptive circuit and the VGND voltage generating circuit.

2. The multi-voltage domain CMOS IO design of claim 1 wherein: the output of the adaptive circuit includes an inter_power voltage signal and an inter_gnd voltage signal.

3. The multi-voltage domain CMOS IO design of claim 1 wherein: the PGATE voltage generating circuit includes voltage generating circuits of 1.8V,2.5V, and 3.3V.

4. A multi-voltage domain CMOS IO design according to claim 3 wherein: the PGATE control switching voltage generation circuit includes control switching voltage generation circuits of 1.8V,2.5V, and 3.3V.

5. The multi-voltage domain CMOS IO design of claim 1 wherein: the self-adaptive circuit comprises 3 PMOS (P-channel metal oxide semiconductor) and 1 NMOS (N-channel metal oxide semiconductor) tubes which are connected in series, wherein the first three PMOS tubes are in a diode mode; the grid electrode of the NMOS tube is connected to 1.8V; the first PMOS tube is used for generating an inter_power voltage signal, and the second PMOS tube is used for generating an inter_gnd voltage signal.

6. The multi-voltage domain CMOS IO design of claim 2 wherein: the VGND voltage is from VDD or VGND; there are two switches for selection, the control voltages of which are respectively noted: pefbk_ P, PEFBK _ N, PEFBK _n and pefbk_p.

7. The multi-voltage domain CMOS IO design of claim 1 wherein: FBK voltages are from VDD, VDD18 POST and VSSPST POST; the MOS control voltages of the switches are respectively: ps_ P, PS _ N, PEFBK _ P, PEFBK _ N, HEFBK _p and hefbk_n.