CN116782654A - How to make a storage device - Google Patents

Abstract

Disclosed is a method for manufacturing a memory device, which includes: forming a floating gate and a control gate of a cellular device in a first region, forming a first LDD region in the substrate of the first region; forming a first gate in the second region and a second gate. The first gate is the gate of the first type of logic device, and the second gate is the gate of the second type of logic device. A second LDD region is formed in the substrate around the first gate. ; Form the source region of the cellular device in the first region; form a third LDD region in the substrate on the peripheral side of the second gate; form a first spacer on the peripheral side of the cellular device, between the first gate and the third A second sidewall is formed around the second gate; a drain region of the cell device is formed; a third gate is formed in the third region, and the third gate is the gate of the third type of logic device; around the third gate A fourth LDD region is formed in the substrate on the third gate electrode; a third spacer is formed on the peripheral side of the third gate electrode. In this application, gates of logic devices with different voltages are etched separately to avoid the impact of redundant heat treatment.

Description

How to make a storage device

Technical field

The present application relates to the technical field of semiconductor integrated circuits, and specifically to a method of manufacturing a memory device.

Background technique

Non-volatile memory (NVM) is a widely used information memory that stores 0/1 information by storing charges on a floating gate (FG). , also has good resistance to magnetic interference.

In NVM memory, NOR gate (not or, NOR) flash memory (flash) is developed based on the tunnel oxide non-volatile memory (programmable read-only memory tunnel oxide, ETOX) structure proposed by Intel. It is a voltage-controlled device that uses hot electron injection to write data and erase data based on the tunnel effect. Its notable feature is its fast random read speed. As a kind of NVM memory, NOR flash memory has the characteristics of high device density, low power consumption and electrical rewritability. It is widely used in smartphones, tablet computers, digital cameras, universal serial bus flash disks and so on. , USB flash drive, referred to as "U disk") and other electronic products with storage functions.

The structure of NOR flash memory is similar to that of a metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as "MOS"). It achieves charge storage by adding a floating gate and a dielectric layer. Usually, The substrate used for integrated NOR flash memory includes an array of cell devices and peripheral circuits. The access of charges in the floating gate will cause the device threshold voltage to change, thereby indicating the state of the cellular device. The array of cellular devices is connected together through a horizontal gate, called a word line (WL), and the drain is connected to a vertical metal through a contact hole (via), called a bit line (BL). The sources of two adjacent cell devices are connected together to form a horizontal source line.

Usually, in order to meet the requirements of low power consumption, peripheral circuits integrate multiple (three or more) logic devices with different operating voltages, for example, logic devices operating at 1.2 volts (V) and logic devices operating at 3.3 volts and 5 volts. logic device below. In related technologies, the gates of cellular devices (floating gates and control gates) and the gates of logic devices with different operating voltages are all etched and formed in the same process step, making it difficult to take into account the needs of logic devices with different operating voltages. Therefore, This results in poor reliability of memory products.

Contents of the invention

The present application provides a method for manufacturing a memory device, which can solve the problem that the manufacturing method of a memory device provided in the related art causes memory problems caused by etching the gates of cellular devices and logic devices with different operating voltages in the same process step. For problems with poor product reliability, the methods include:

A floating gate and a control gate of the cellular device are formed in the first region. The control gate is formed on the isolation layer. The isolation layer is formed on the floating gate. The floating gate is formed on the first oxide layer. The third An oxide layer is formed on the substrate. Viewed from a top view, the substrate includes a first region, a second region and a third region. The first region is used to integrate the cellular device, and the second region The third area is used to integrate the first type of logic device and the second type of logic device. The third area is used to integrate the third type of logic device. The first type of logic device, the second type of logic device and the third type of logic device. The operating voltages of the logic devices are different, and a first LDD region is formed in the substrate of the first region;

A first gate and a second gate are formed in the second region. The first gate is the gate of the first type of logic device, and the second gate is the gate of the second type of logic device. gate;

forming a second LDD region in the substrate on the peripheral side of the first gate;

Form a source region of the cellular device in the first region;

forming a third LDD region in the substrate on the peripheral side of the second gate;

A first spacer is formed on the peripheral side of the cellular device, and a second spacer is formed on the peripheral side of the first gate and the second gate;

Form the drain region of the cellular device;

A third gate is formed in the third region, and the third gate is the gate of the third type of logic device;

forming a fourth LDD region in the substrate on the peripheral side of the third gate;

A third spacer is formed around the third gate.

In some embodiments, forming the floating gate and control gate of the cellular device in the first region includes:

The substrate is provided, the first oxide layer is formed on the substrate in the first region, the second oxide layer is formed on the substrate in the second region and the third region, and A first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, and the second polysilicon layer A mask layer is formed on the second oxide layer, a third polysilicon layer is formed on the second oxide layer, and a mask layer is formed on the second polysilicon layer;

Cover the mask layer with photoresist through a photolithography process to expose the first target area, which is other areas in the first area except the area occupied by the floating gate when viewed from a bird's eye view;

Perform etching to remove the first polysilicon layer, isolation layer, second polysilicon layer and mask layer in the first target area. The remaining first polysilicon layer constitutes the floating gate, and the remaining third polysilicon layer constitutes the floating gate. Two polysilicon layers constitute the control gate;

Remove photoresist.

In some embodiments, forming the first gate and the second gate in the second region includes:

The photoresist is covered through a photolithography process to expose a second target area. The second target area is viewed from a bird's eye view. The second area is excluding the area occupied by the first gate electrode and the second gate electrode. other areas;

Perform etching to remove the third polysilicon layer in the second target area, and the remaining third polysilicon layer in the second area constitutes the first gate and the second gate;

Remove photoresist.

In some embodiments, forming the source region of the cellular device in the first region includes:

The photoresist is covered by a photolithography process to expose the third target area. The third target area is the area in the first area between the two floating gates in the cellular device group. The cellular device group is composed of Composed of two adjacent cellular devices;

Perform etching to a predetermined depth in the substrate of the third target area;

Perform ion implantation to form the source region in the substrate of the third target region;

Remove photoresist.

In some embodiments, forming a third gate in the third region includes:

The photoresist is covered by a photolithography process to expose a fourth target area. The fourth target area is the other areas in the third area except the area occupied by the third gate when viewed from a bird's eye view;

Perform etching to remove the third polysilicon layer in the fourth target area, and the remaining third polysilicon layer in the third area constitutes the third gate;

Remove photoresist.

In some embodiments, the isolation layer includes an ONO layer, the first spacer includes an ONO layer, the second spacer includes an ONO layer, and the third spacer includes a NON layer.

In some embodiments, the mask layer includes a silicon nitride layer.

The technical solution of this application at least includes the following advantages:

In the manufacturing process of memory devices integrating logic devices with different operating voltages, the gates of logic devices with different operating voltages are etched separately to avoid the impact of unnecessary heat treatment on relatively low-voltage logic devices. The reliability and yield of the device are improved to a certain extent.

Description of drawings

In order to more clearly explain the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a flow chart of a method for manufacturing a memory device provided by an exemplary embodiment of the present application;

2 to 7 are schematic diagrams of the production of a memory device provided by an exemplary embodiment of the present application.

Detailed ways

The technical solutions in this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of this application, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary; it can also be an internal connection between two components; it can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.

In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

Referring to Figure 1, which shows a flow chart of a method for manufacturing a memory device provided by an exemplary embodiment of the present application. The memory device may be a NOR flash memory. As shown in Figure 1, the method includes:

Step S1: Form a floating gate and a control gate of the cellular device in the first region. The control gate is formed on the isolation layer. The isolation layer is formed on the floating gate. The floating gate is formed on the first oxide layer. The first oxide layer is formed on on the substrate.

Exemplarily, step S1 includes but is not limited to: providing a substrate, a first oxide layer is formed on the substrate in the first region, a second oxide layer is formed on the substrate in the second region and the third region, and the first oxide layer is formed on the substrate in the first region. A first polysilicon layer is formed on the first polysilicon layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, a mask layer is formed on the second polysilicon layer, and a second polysilicon layer is formed on the isolation layer. A third polysilicon layer is formed on the oxide layer, and a mask layer is formed on the second polysilicon layer; the mask layer is covered with photoresist through a photolithography process to expose the first target area, and the first target area is Observed from a bird's eye view, other areas in the first area except the area occupied by the floating gate; etching is performed to remove the first polysilicon layer, isolation layer, second polysilicon layer and mask layer in the first target area , the remaining first polysilicon layer forms the floating gate, and the remaining second polysilicon layer forms the control gate; remove the photoresist.

Refer to FIG. 2 , which shows a schematic cross-sectional view after covering the mask layer with photoresist through a photolithography process. Refer to FIG. 3 , which shows a schematic cross-sectional view after etching to form a floating gate and a control gate. For example, as shown in Figure 2 and Figure 3:

Viewed from a top view, the substrate 210 includes a first region 201, a second region 202 and a third region 203. The first region 201 is used to integrate cellular devices, and the second region 202 is used to integrate the first type of logic device and the second type of logic device. The third area 203 is used to integrate the third type logic device. The working voltages of the first type logic device, the second type logic device and the third type logic device are different. The substrate 210 of the first area 201 is formed with A first lightly doped drain (LDD) region 211.

Before etching, a first oxide layer 221 is formed on the substrate 210 in the first region 201, and a second oxide layer 222 is formed on the substrate 210 in the second region 202 and the third region 203 (the second oxide layer 222 The thickness is greater than the thickness of the first oxide layer 221), a first polysilicon layer 231 is formed on the first oxide layer 221, an isolation layer is formed on the first polysilicon layer 231, and a second polysilicon layer is formed on the isolation layer. A mask layer 250 is formed on the silicon layer 232 and the second polysilicon layer. A third polysilicon layer 233 is formed on the second oxide layer 222. The mask layer 250 is formed on the second polysilicon layer 233. Wherein, the isolation layer may include an oxide-nitride-oxide (ONO) layer, which from bottom to top includes a silicon dioxide (SiO ₂ ) layer 241, a silicon nitride (Si ₃ N ₄ ) layer 242 and silicon dioxide layer 243; the mask layer 250 may include a silicon nitride layer; a first shallow trench isolation (STI) structure 311 is formed in the substrate 210 in the second region 202, from a top view Observe that the area surrounded by the first STI structure 311 (only partial screenshots of the first STI structure 311 are shown in FIGS. 2 to 7 ) are the active areas (AA) of the first type of logic device or the second type of logic device. ); A second STI structure 312 is formed in the substrate 210 of the third region 203. Viewed from a top view, the area surrounded by the second STI structure 312 (only partial screenshots of the second STI structure 312 are shown in Figures 2 to 7 ) is the active area of the third type of logic device.

Among them, the working voltage of the first type of logic device and the second type of logic device is greater than the working voltage of the third type of logic device, and the working voltage of the first type of logic device is greater than the working voltage of the second type of logic device. For example, the operating voltage of a first type of logic device may be between 4 volts and 6 volts (eg, it may be 5 volts), and the operating voltage of a second type of logic device may be between 2 volts and 4 volts (eg, it may be 5 volts). , which may be 3.3 volts), and the operating voltage of the third type of logic device may be between 1 volt and 2 volts (for example, it may be 1.2 volts).

The photoresist 301 can be covered on the mask layer 250 through a photolithography process to expose the first target area 401, and etching can be performed to remove the first polysilicon layer 231, isolation layer, and second polysilicon layer in the first target area 201. The silicon layer 232 and the mask layer 250, the remaining first polysilicon layer 231 constitute a floating gate, and the remaining second polysilicon layer 232 constitute a control gate, and then the photoresist 301 is removed.

Step S2: Form a first gate and a second gate in the second region. The first gate is the gate of the first type of logic device, and the second gate is the gate of the second type of logic device.

Exemplarily, step S2 includes but is not limited to: covering the photoresist through a photolithography process to expose the second target area. The second target area is viewed from a bird's-eye view. In addition to the first gate electrode and the second gate electrode, the second target area Other areas other than the occupied area; perform etching to remove the third polysilicon layer in the second target area, and the remaining third polysilicon layer in the second area constitutes the first gate and the second gate; remove the photoresist .

Referring to FIG. 4 , a schematic cross-sectional view after etching to form the second gate and the third gate is shown. For example, as shown in FIG. 4 , the photoresist 302 can be covered by a photolithography process, the second target area 402 is exposed, etching is performed, and the second target area 402 and the third polysilicon layer 233 are removed. The second area 202 The remaining third polysilicon layer 233 forms the first gate 2331 and the second gate (not shown in FIGS. 4 to 7 ), and the photoresist 302 can be removed subsequently.

Step S3: Form a second LDD region in the substrate around the first gate.

For example, the photoresist can be covered through a photolithography process, the area corresponding to the second LDD region is exposed, ion implantation is performed, a second LDD region is formed in the substrate around the first gate, and the photoresist is removed.

Step S4: Form the source region of the cellular device in the first region.

Exemplarily, step S4 includes but is not limited to: covering the photoresist through a photolithography process to expose the third target area, which is the area between the two floating gates in the cellular device group in the first area, The unit cell device group consists of two adjacent unit cells; etching is performed to a predetermined depth in the substrate of the third target area; ion implantation is performed to form a source region in the substrate of the third target area ;Remove photoresist.

Referring to FIG. 5 , a schematic cross-sectional view after forming the source region of the cellular device is shown. For example, as shown in Figure 5, a second LDD region 213 is formed in the substrate 210 on the peripheral side of the first gate 2331; the photoresist 302 can be covered by a photolithography process to expose the third target region 403 for etching. , etching to a predetermined depth in the substrate 210 in the third target region 403, performing ion implantation, forming the source region 212 in the substrate 210 in the third target region 403, and the photoresist 302 can be removed subsequently. Two adjacent groups of cellular devices can be formed into a cellular device group, and adjacent cellular devices in the cellular device group can share a source area.

It should be noted that the width of the third target area 403 is actually larger than the area between the two adjacent floating gates 231 , so during the etching process, the top of the control gate 232 will be trimmed by the plasma.

Step S5: Form a third LDD region in the substrate around the second gate.

For example, the photoresist can be covered through a photolithography process to expose the area corresponding to the third LDD region, and ions can be implanted to form the third LDD region in the substrate around the second gate, and then the photoresist can be removed.

Step S6: Form a first spacer on the peripheral side of the cell device, and form a second spacer on the peripheral side of the first gate and the second gate.

Exemplarily, both the first sidewall and the second sidewall include an ONO layer, which can be covered with photoresist through a photolithography process to expose the first area and the second area, and a silicon dioxide layer, a silicon nitride layer, and a second area are sequentially deposited. The silicon oxide layer is etched (for example, it can be etched through a dry etching process) to simultaneously form the first spacers and the second spacers. At the same time, the etching process can cause the first oxide layer and the second spacers in the first region to be etched. The second oxide layer in the two regions is removed, and then the photoresist is removed.

Step S7: Form the drain region of the cell device.

For example, the photoresist can be covered through a photolithography process to expose the area corresponding to the drain region of the cellular device, ion implantation can be performed to form the drain region of the cellular device, and then the first sidewall can be etched through a wet etching process. The outermost silicon dioxide layer is cleaned to remove the photoresist. It should be noted that the impurity concentration doped into the source and drain regions of the cell device is greater than the impurity concentration doped into other doped regions.

Referring to FIG. 6 , a schematic cross-sectional view after forming the first spacers, the second spacers and the drain region of the cellular device is shown. Exemplarily, as shown in Figure 6, the first sidewalls include a silicon dioxide layer 2511, a silicon nitride layer 2521 and a silicon dioxide layer 2531 in order from the inside to the outside. The first sidewalls are formed between the cell device groups and On the peripheral side of the cellular device group, a common source region 212 is formed in the substrate 210 between two cellular devices in the cellular device group, and a drain region 213 is formed in the substrate 210 on the peripheral side of the cellular device group; The second spacer includes a silicon dioxide layer 2512, a silicon nitride layer 2522 and a silicon dioxide layer 2532 in order from the inside to the outside. The second spacer is formed on the first gate 2331 and the second gate (not shown in the figure) A second LDD region 214 is formed in the substrate 210 around the first gate 2331, and a third LDD region (not shown in the figure) is formed in the substrate 210 around the second gate. It should be noted that in the wet etching process in step S7, the outermost silicon dioxide layer 2531 of the first side wall can also be completely removed. In Figures 6 and 7, part of the silicon dioxide layer 2531 is retained as an example. sexual description. Subsequent steps S8 to S10 are to separately manufacture the third type of logic device (which is an advanced node device).

Step S8: Form a third gate in the third region. The third gate is the gate of the third type of logic device.

Exemplarily, step S8 includes but is not limited to: covering the photoresist through a photolithography process to expose the fourth target area. The fourth target area is viewed from a bird's-eye view, and the third area except the area occupied by the third gate electrode Other areas; perform etching to remove the third polysilicon layer in the fourth target area, and the remaining third polysilicon layer in the third area constitutes the third gate; remove the photoresist.

Step S9: Form a fourth LDD region in the substrate on the side of the third gate.

For example, the third spacer formed subsequently on the peripheral side of the third gate includes a nitride-oxide-nitride (NON) layer. Before forming the fourth LDD region, the third spacer may be formed first. An oxide layer is formed on the surface of the tri-gate to repair it, and then the innermost silicon nitride layer of the NON layer is formed, etched, and then covered with photoresist through a photolithography process to expose the fourth LDD area. In the corresponding area, ions are implanted to form a fourth LDD area in the substrate around the third gate, and then the photoresist is removed.

In step S10, a third spacer is formed on the peripheral side of the third gate.

For example, a silicon dioxide layer and a silicon nitride layer can be deposited sequentially, and a third sidewall can be formed by etching. At the same time, the etching process can remove the second oxide layer in the third target area. Since the NON layer of the third side wall is deposited in the entire area, when the third side wall is formed, outer walls are formed on the peripheral sides of the first side wall and the second side wall.

Referring to FIG. 7 , a schematic cross-sectional view after forming the third side wall is shown. Exemplarily, as shown in Figure 7, the third spacer includes a silicon nitride layer 2513, a silicon dioxide layer 2523 and a silicon nitride layer 2533 in order from the inside to the outside. The third spacer is formed around the third gate 2333. side, a first outer side wall is formed on the peripheral side of the first side wall, and the first outer side wall includes a silicon nitride layer 2611, a silicon dioxide layer 2621 and a silicon nitride layer 2631 in order from the inside to the outside. The peripheral side of the second side wall A second outer sidewall is formed. The second outer sidewall includes a silicon nitride layer 2612, a silicon dioxide layer 2622 and a silicon nitride layer 2632 in sequence from the inside to the outside. A fourth LDD is formed in the substrate 210 around the third gate electrode 2333. District 215. The impurity concentrations in the source region 212 and the drain region 213 are greater than those in other doped regions. It should be noted that, in the end, the width of the side walls (the second side wall and the second outer wall) around the first type of logic device and the second type logic device is larger than the width of the side walls (the third type) around the third type logic device. Sidewall) width, so that a higher source-drain breakdown voltage can be obtained.

After step S10, the first region can be covered through a photolithography process, and source drain (SD) ion implantation can be performed on the second region and the third region. A heavily doped region is formed in the substrate on the peripheral side as the source region and the drain region of the first type of logic device, the second type of logic device and the third type of logic device.

To sum up, in the embodiments of the present application, in the manufacturing process of a memory device integrating logic devices with different operating voltages, the gates of the logic devices with different operating voltages are etched separately to avoid unnecessary heat treatment. It affects relatively low-voltage logic devices and improves the reliability and yield of the devices to a certain extent.

Obviously, the above-mentioned embodiments are only examples for clear explanation and are not intended to limit the implementation. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is neither necessary nor possible. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims (7)

1. A method of manufacturing a memory device, characterized by comprising: A floating gate and a control gate of the cellular device are formed in the first region. The control gate is formed on the isolation layer. The isolation layer is formed on the floating gate. The floating gate is formed on the first oxide layer. The third An oxide layer is formed on the substrate. Viewed from a top view, the substrate includes a first region, a second region and a third region. The first region is used to integrate the cellular device, and the second region The third area is used to integrate the first type of logic device and the second type of logic device. The third area is used to integrate the third type of logic device. The first type of logic device, the second type of logic device and the third type of logic device. The operating voltages of the logic devices are different, and a first LDD region is formed in the substrate of the first region; A first gate and a second gate are formed in the second region. The first gate is the gate of the first type of logic device, and the second gate is the gate of the second type of logic device. gate; forming a second LDD region in the substrate on the peripheral side of the first gate; Form a source region of the cellular device in the first region; forming a third LDD region in the substrate on the peripheral side of the second gate; A first spacer is formed on the peripheral side of the cellular device, and a second spacer is formed on the peripheral side of the first gate and the second gate; Form the drain region of the cellular device; A third gate is formed in the third region, and the third gate is the gate of the third type of logic device; forming a fourth LDD region in the substrate on the peripheral side of the third gate; A third spacer is formed around the third gate. 2. The method according to claim 1, wherein forming the floating gate and the control gate of the cellular device in the first region includes: The substrate is provided, the first oxide layer is formed on the substrate in the first region, the second oxide layer is formed on the substrate in the second region and the third region, and A first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, and the second polysilicon layer A mask layer is formed on the second oxide layer, a third polysilicon layer is formed on the second oxide layer, and a mask layer is formed on the second polysilicon layer; Cover the mask layer with photoresist through a photolithography process to expose the first target area, which is other areas in the first area except the area occupied by the floating gate when viewed from a bird's eye view; Perform etching to remove the first polysilicon layer, isolation layer, second polysilicon layer and mask layer in the first target area. The remaining first polysilicon layer constitutes the floating gate, and the remaining third polysilicon layer constitutes the floating gate. Two polysilicon layers constitute the control gate; Remove photoresist. 3. The method of claim 2, wherein forming the first gate and the second gate in the second region includes: The photoresist is covered through a photolithography process to expose a second target area. The second target area is viewed from a bird's eye view. The second area is excluding the area occupied by the first gate electrode and the second gate electrode. other areas; Perform etching to remove the third polysilicon layer in the second target area, and the remaining third polysilicon layer in the second area constitutes the first gate and the second gate; Remove photoresist. 4. The method of claim 2, wherein forming the source region of the cellular device in the first region includes: The photoresist is covered by a photolithography process to expose the third target area. The third target area is the area in the first area between the two floating gates in the cellular device group. The cellular device group is composed of Composed of two adjacent cellular devices; Perform etching to a predetermined depth in the substrate of the third target area; Perform ion implantation to form the source region in the substrate of the third target region; Remove photoresist. 5. The method of claim 2, wherein forming a third gate in the third region includes: The photoresist is covered by a photolithography process to expose a fourth target area. The fourth target area is the other areas in the third area except the area occupied by the third gate when viewed from a bird's eye view; Perform etching to remove the third polysilicon layer in the fourth target area, and the remaining third polysilicon layer in the third area constitutes the third gate; Remove photoresist. 6. The method according to any one of claims 1 to 5, wherein the isolation layer includes an ONO layer, the first sidewall includes an ONO layer, the second sidewall includes an ONO layer, and the third sidewall includes an ONO layer. Three side walls include NON layer. 7. The method of claim 6, wherein the mask layer includes a silicon nitride layer.