CN116779446A - Shielded gate MOS device and manufacturing method thereof - Google Patents

Abstract

The invention provides a shielded gate MOS device and a manufacturing method thereof, which includes: providing a substrate with a number of trenches formed in the substrate; performing oblique implantation of first type ions into the substrate on both sides of the trench, and adjacent trenches A first type implantation region is formed in the substrate between the trenches; a second type ion oblique implantation is performed in the substrate on both sides of the trench, and a region close to the trenches on both sides is formed in the substrate between adjacent trenches The second type of implantation region; a bottom-up spaced shield gate and a polysilicon gate are formed in the trench. The present invention performs two oblique implantations of ions into the substrate on both sides of the trench to form a superjunction structure of N pillar-P pillar-N pillar or P pillar-N pillar-P pillar in the substrate. The PN pillar structure can To further reduce the resistivity of the drift layer, the superjunction structure introduces a new depletion region, which can expand the epitaxial layer area of the shielded gate MOS device participating in the conduction substrate, and can use higher concentration epitaxy, thereby reducing the on-resistance.

Description

Shielded gate MOS device and manufacturing method thereof

Technical field

The invention belongs to the technical field of integrated circuit manufacturing, and specifically relates to a shielded gate MOS device and a manufacturing method thereof.

Background technique

Shielded Gate Trench (SGT, also known as shielded gate) field effect transistor (MOSFET) device, due to its lower gate leakage capacitance, lower on-resistance and higher withstand voltage performance, compared with traditional MOS is more conducive to the flexible application of semiconductor integrated circuits. Specifically, in a split-gate field effect transistor, by setting a shield gate below the polysilicon gate, the gate leakage capacitance can be greatly reduced and the device electric field can be optimized to increase the breakdown voltage, and the drift region of the split-gate field effect transistor also has A higher impurity carrier concentration can correspondingly reduce the on-resistance.

SGT-MOSFET devices have the advantages of small parasitic capacitance, fast switching speed, and low power loss. They are currently the mainstream power devices in medium and low voltage applications. Compared with ordinary VD (Vertical Diffused, vertical diffusion)-MOSFET, a shield gate is introduced to assist in the depletion of carriers in the drift region, thereby increasing the withstand voltage. Currently limited by process conditions and silicon material performance limits, it has become very difficult to reduce the on-resistance by reducing the resistivity of the drift layer.

Contents of the invention

The object of the present invention is to provide a shielded gate MOS device and a manufacturing method thereof. The present invention forms a second type of implanted region and a first type of implanted region in the substrate by performing two oblique implantations of ions into the substrate on both sides of the trench. The superjunction structure of the type injection region and the second type injection region; the PN pillar structure can further reduce the resistivity of the drift layer. The superjunction structure introduces a new depletion region to expand the area of the epitaxial layer on the conductive substrate where the SGT device participates. , and can use higher concentration epitaxy, thereby reducing on-resistance.

The invention provides a method for manufacturing a shielded gate MOS device, which includes:

Provide a substrate with a plurality of trenches formed in the substrate;

Perform oblique implantation of first-type ions into the substrate on both sides of the trench, and form a first-type implantation region in the substrate between adjacent trenches;

Perform oblique implantation of second-type ions into the substrate on both sides of the trench, and a region of the substrate located between adjacent trenches close to the trenches on both sides forms a second-type implantation area; Thus, a superjunction structure of the second type implanted region, the first type implanted region and the second type implanted region is formed in the substrate on both sides of the trench;

A shield gate and a polysilicon gate spaced from bottom to top are formed in the trench.

Further, the first type ion implantation dose is greater than the second type ion implantation dose.

Further, the oblique implantation dose range of the first type ions is: 2×10 ¹⁹ atoms/cm ² to 9×10 ²¹ atoms/cm ² .

Further, the oblique implantation dose range of the second type ions is: 2×10 ¹³ atoms/cm ² to 8×10 ¹⁵ atoms/cm ² .

Further, the oblique injection angle range of the first type ions is: 20°-75°; the oblique injection angle range of the second type ions is: 20°-75°.

Further, an isolation layer is formed on the surface of the substrate on both sides of the trench, and the first type ion oblique implantation and the third ion implantation are performed on the substrates on both sides of the trench using the isolation layer as a mask. Type II ion oblique implantation.

Further, forming shield gates and polysilicon gates spaced from bottom to top in the trench, specifically including:

A shielding oxide layer is formed, the shielding oxide layer covers the bottom and sidewall surface of the lower part of the trench, the shielding oxide layer has a first cavity area, and the shielding grid is formed in the first cavity area ;

A gate oxide layer is formed, the gate oxide layer covers the shield gate and the surface of the shield oxide layer and the sidewalls of the upper part of the trench, the gate oxide layer has a second cavity area, in the third Two cavity regions form the polysilicon gate.

Further, after forming the shield gate and the polysilicon gate, it also includes:

The first type ions are implanted into the substrate on both sides of the trench to form a body region; and the second type ions are heavily doped on both sides of the body region to form a source region.

The invention also provides a shielded gate MOS device, including:

A substrate with a plurality of trenches formed in the substrate;

A shield gate and a polysilicon gate spaced from bottom to top are formed in the trench;

A superjunction structure of a second type implanted region, a first type implanted region and a second type implanted region is formed in the substrate on both sides of the trench;

Further, the shielded gate MOS device also includes:

A shielding oxide layer located in the gap between the shielding gate and the trench;

A gate oxide layer is located between the shield gate and the polysilicon gate and between the sidewalls of the polysilicon gate and the sidewalls of the trench.

Compared with the prior art, the present invention has the following beneficial effects:

The invention provides a shielded gate MOS device and a manufacturing method thereof, which includes: providing a substrate with several trenches formed in the substrate; performing oblique implantation of first type ions into the substrate on both sides of the trench, and adjacent trenches A first-type implantation region is formed in the substrate between the trenches; a second-type ion oblique implantation is performed in the substrate on both sides of the trench, and a region close to the trenches on both sides is formed in the substrate between adjacent trenches. The second type of implanted region; thus, a superjunction structure of the second type of implanted region, the first type of implanted region and the second type of implanted region is formed in the substrate on both sides of the trench; a bottom-up spaced Shielded gates and polysilicon gates. The present invention performs two oblique implantations of ions into the substrate on both sides of the trench to form a superjunction structure of the second type implantation region, the first type implantation region and the second type implantation region in the substrate; that is, N pillar- The super-junction structure of P-pillar-N pillar or P-pillar-N pillar-P pillar. The PN pillar structure can further reduce the resistivity of the drift layer. The superjunction structure introduces a new depletion region to expand the shielded gate MOS device to participate in conduction. epitaxial layer area on the substrate and can use higher concentration epitaxy, thereby reducing on-resistance.

Description of drawings

FIG. 1 is a schematic flow chart of a manufacturing method of a shielded gate MOS device according to an embodiment of the present invention.

2 to 5 are schematic diagrams of each step of a manufacturing method of a shielded gate MOS device according to an embodiment of the present invention.

Among them, the reference signs are as follows:

10-Substrate; 11-Isolation layer; 12-First type implantation area; 13-Second type injection area; 14-Shielding gate; 15-Polysilicon gate; 16-Shielding oxide layer; 17-Gate oxide layer; 18- Body region; 19-source region; 20-interlayer dielectric layer; V-trench; A-oblique injection angle of first type ions; B-oblique injection angle of second type ions.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

For ease of description, some embodiments of the present application may use spatially relative terms such as “above,” “below,” “top,” “below,” etc., to describe an element as shown in the figures of the embodiments. or the relationship between a component and another element or components. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "above" the other elements or components. The terms "first," "second," etc., below are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronology. It is understood that these terms so used are interchangeable where appropriate.

An embodiment of the present invention provides a method for manufacturing a shielded gate MOS device, as shown in Figure 1, including:

Step S1. Provide a substrate with several trenches formed in the substrate;

Step S2: Perform oblique implantation of first-type ions into the substrate on both sides of the trench, and form a first-type implantation region in the substrate between adjacent trenches;

Step S3: Perform oblique implantation of second-type ions into the substrate on both sides of the trench, and form a second-type ion in a region of the substrate between adjacent trenches close to the trenches on both sides. Implantation region; thus forming a superjunction structure of the second type implantation region, the first type implantation region and the second type implantation region in the substrate on both sides of the trench;

Step S4: Form shield gates and polysilicon gates spaced from bottom to top in the trench.

Each step of the manufacturing method of the shielded gate MOS device according to the embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 5 .

Step S1, as shown in FIG. 2, a substrate 10 is provided, and a plurality of trenches V are formed in the substrate 10. Specifically, an isolation layer 11 is formed on the surface of the substrate, and the isolation layer and the substrate are etched to form several (greater than or equal to 2) trenches V. The substrate 10 can be any suitable substrate material well known to those skilled in the art. It can be a bare wafer or a wafer processed through a series of processes. For example, a shallow trench isolation can be formed inside it. Structure (STI), etc. For example, the substrate 10 includes a substrate and an epitaxial layer on the surface of the substrate, and the trenches V are distributed in the epitaxial layer.

Step S2, as shown in FIG. 3, perform oblique implantation of first-type ions into the substrate 10 on both sides of the trench V, and form a first-type implantation region 12 in the substrate 10 between adjacent trenches V.

It can also be understood that oblique implantation of first-type ions is performed into the substrate 10 between adjacent trenches V to form the first-type implantation region 12 . Dopants are introduced through oblique implantation, and the isolation layer 11 is used as a mask during the oblique implantation. For example, the first type is P type. The first type of ion tilt implant may include boron dopants and may employ implants with ion doses ranging from 2×10 ¹⁹ atoms/cm ² to 9×10 ²¹ atoms/cm ² . In one embodiment, tilt implantation is performed using an ion implantation device operating at energies ranging from 5 keV to 60 keV. Tilt implantation can be performed at temperatures ranging from 50°C to 800°C. In another embodiment, tilt implantation is performed using temperatures ranging from 100°C to 400°C. The first type ion oblique implantation angle A is an acute angle formed when a plane P ₁ parallel to the traveling direction of the dopant and a plane P ₂ perpendicular to the surface of the substrate 10 intersect. The first type ion oblique implantation angle A ranges from 20° to 75°, for example.

Step S3, as shown in FIG. 4, perform oblique implantation of second type ions into the substrate on both sides of the trench V, and the area of the substrate 10 between adjacent trenches V close to the trenches V on both sides forms a third Type II injection zone 13. A superjunction structure of the second type injection region 13, the first type injection region 12 and the second type injection region 13 is formed in the substrate on both sides of the trench V; that is, N pillar-P pillar-N pillar or P pillar-N The pillar-P pillar superjunction structure and PN pillar structure can further reduce the resistivity of the drift layer. The superjunction structure introduces a new depletion region, which can expand the area of the epitaxial layer on the conductive substrate of the shielded gate MOS device, and can Use higher concentration epitaxy, thus lowering on-resistance. Illustratively, the second type is N type, and the dopant is composed of arsenic, phosphorus, germanium, xenon, argon, krypton or a combination thereof. The second type of ion tilt implantation can use ion dose ranging from 2×10 ¹³ atoms/cm ² to 8×10 ¹⁵ atoms/cm ² . The second type ion oblique implantation angle B ranges from 20° to 75°, for example.

The first type ion implantation dose is greater than the second type ion implantation dose. Specifically, the first type implantation region 12 is formed in the substrate 10 between adjacent trenches V, and the second type implantation region 13 is located between the adjacent trenches by controlling the oblique implantation angle and dose of the second type ions. The area of the substrate 10 close to the trenches V on both sides, while the middle area of the substrate 10 between adjacent trenches is not implanted with second type ions, and the middle area of the substrate 10 between adjacent trenches is only the second type of ion. A type of injection region 12 constitutes a first type of column, such as a P column; both sides of the first type of column 12 constitute a second type of column 13, such as an N column. After oblique implantation of second type ions, the isolation layer 11 is removed. Both the first type ion implantation and the second type ion implantation are implanted obliquely using the isolation layer 11 as a mask, so the upper portions of the substrate on both sides of the trench form a triangular non-implanted area.

Step S4, as shown in FIG. 5, a shield gate 14 and a polysilicon gate 15 spaced from bottom to top are formed in the trench V. Specifically, a shielding oxide layer 16 is formed to cover the bottom and sidewall surfaces of the trench V. The shielding oxide layer 16 has a first cavity area, and the first cavity area is filled with a shielding gate film layer. The shielding oxide layer 16 can be formed through a thermal oxidation process or a chemical vapor deposition (CVD) process, or a thermal oxidation process first and then a chemical vapor deposition process, or other suitable film formation processes. A shielding oxide layer is formed on the sidewalls and bottom of the trench and on the surface of the substrate 10 around the trench V. The shielding oxide layer 16 can be a single layer film or a multi-layer film stack structure, depending on the method used. Formed by a single film-forming process or multiple film-forming processes. The material of the shielding oxide layer 16 may be a stack material of oxide and nitride, oxide, nitride, or other appropriate dielectric materials.

The material of the shielding gate film layer may be a conductive material, such as polysilicon material or other appropriate conductive materials. The shield gate film layer can be filled with N-type ion doped or P-type ion doped polysilicon into the trench V through polysilicon deposition and in-situ doping processes. At this time, the polysilicon fills the trench V and the shield around the trench V The surface of the oxide layer is also covered with polysilicon, in which the N-type ions are, for example, at least one of phosphorus, arsenic, antimony, germanium, etc., and the P-type ions are, for example, boron or indium. A part of the thickness of the shielding grid film is removed, and the shielding oxide layer surrounding the removed part of the shielding grid film is removed; the remaining thickness of the shielding grid film forms the shielding grid 14 . In a specific implementation, the shield gate film layer and the shield oxide layer 16 of the same thickness can be removed, for example, the same etching process can be used to remove them. Specifically, dry etching can be used to remove part of the thickness of the shielding gate film layer and the shielding oxide layer from top to bottom.

A gate oxide layer 17 is formed. The gate oxide layer 17 covers the surface of the shield gate 14 and the remaining shield oxide layer 16 as well as the sidewalls of the trench V above the shield gate 14. The gate oxide layer 17 has a second cavity area. The cavity area forms a polysilicon gate 15 . The polysilicon gate 15 can be deposited with polysilicon (polysilicon that can be doped with N-type ions or P-type ions) in the second cavity area of the gate oxide layer 17 through a suitable deposition process such as a chemical vapor deposition process. The deposited polysilicon is then top planarized through a chemical mechanical polishing process. Specifically, the material of the gate oxide layer 17 can be consistent with the material of the shield oxide layer 16 to improve the insulation effect. The material of the gate oxide layer 17 may also be inconsistent with the material of the shield oxide layer 16 . The material of the shielding oxide layer 16 is an oxide, such as silicon oxide. By using an oxidation process to oxidize the material of the substrate 10 to form the shielding oxide layer 16, the thickness of the shielding oxide layer 16 can be effectively controlled and better insulation quality can be obtained. In the same way, the gate oxide layer 17 can be obtained.

The manufacturing method of the shielded gate MOS device may also include: injecting first-type ions into the substrate on both sides of the trench to form the body region 18. The body region 18 is, for example, implanted with P-type ions; and redoping the body region 18 on both sides of the body region 18. The source region 19 is formed by doping second type ions, for example, N-type ions are implanted to form an N-type heavily doped (N+) source region 19 . Source area 19 covers part of body area 18 .

Next, an interlayer dielectric layer 20 is formed over the substrate 10 , and the interlayer dielectric layer 20 can be deposited through a process such as chemical vapor deposition. Through the contact hole process, the interlayer dielectric layer 20 and the like are etched to form a plurality of contact holes penetrating the interlayer dielectric layer 20 . After that, each contact hole is filled with conductive material to form a corresponding contact plug to lead out electricity. For example, a contact hole may be formed above the source region 19 to lead out the source region 19 .

Exemplarily, the source of the shielded gate MOS device is led out through the plug in the contact hole above the source region 19, and the drain is led out from the side surface (ie, the back) of the substrate 10 away from the polysilicon gate 15. The polysilicon gate 15 serves as the gate. pole. The shielded gate MOS device includes a cell area and a terminal area. In Figure 5, the bottom-up spaced shield gate 14 and polysilicon gate 15 in the trench V, as well as the N-pillar-P-pillar-N-pillar superjunction structures in the substrates on both sides of the trench V are all located in the shield gate MOS The cell area of the device; the lead-out structure of the polysilicon gate 15 is not shown in Figure 5. The polysilicon gate 15 serves as a gate electrode and can be led out through the contact hole in the terminal area (not shown).

This embodiment also provides a shielded gate MOS device, as shown in Figure 5, including:

Substrate 10, a plurality of trenches V are formed in the substrate 10;

A shield gate 14 and a polysilicon gate 15 spaced from bottom to top are formed in the trench V;

A superjunction structure of the second type implantation region 13 , the first type implantation region 12 and the second type implantation region 13 is formed in the substrate on both sides of the trench V.

The shielded gate MOS device also includes: a shielding oxide layer 16 , which is located in the gap between the shielding gate 14 and the trench V. The gate oxide layer 17 is located between the shield gate 14 and the polysilicon gate 15 and between the sidewalls of the polysilicon gate 15 and the sidewalls of the trench V. The first type of column is P type and the second type of column is N type; or the first type of column is N type and the second type of column is P type.

To sum up, the present invention provides a shielded gate MOS device and a manufacturing method thereof, which include: providing a substrate with a number of trenches formed in the substrate; performing first type ion tilting in the substrate on both sides of the trench Implantation, forming a first-type implantation region in the substrate between adjacent trenches; performing oblique implantation of second-type ions into the substrate on both sides of the trench, located near both sides of the substrate between adjacent trenches The area of the trench forms a second type implantation area; thus, a superjunction structure of the second type injection area, the first type injection area and the second type injection area is formed in the substrate on both sides of the trench; Shielded gates and polysilicon gates spaced from bottom to top. The present invention performs two oblique implantations of ions into the substrate on both sides of the trench to form a superjunction structure of the second type implantation region, the first type implantation region and the second type implantation region in the substrate; that is, N pillar- The superjunction structure of P pillar-N pillar or P pillar-N pillar-P pillar. The PN pillar structure can further reduce the resistivity of the drift layer. The superjunction structure introduces a new depletion region and can expand the SGT device to participate in the conduction of the epitaxial layer. area and can use higher concentration epitaxy, thus reducing on-resistance.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. As for the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple. For relevant details, please refer to the description in the method section.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made to the technical solution. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (10)

1. A method of manufacturing a shielded gate MOS device, comprising:

providing a substrate, wherein a plurality of grooves are formed in the substrate;

performing first type ion inclined implantation in the substrates at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves;

performing second-type ion inclined implantation on the substrates at two sides of the grooves, and forming second-type implantation areas in the areas, close to the grooves at two sides, of the substrates between the adjacent grooves; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove;

and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove.

2. The method of manufacturing a shielded gate MOS device of claim 1, wherein the first type ion implantation dose is greater than the second type ion implantation dose.

3. The method of manufacturing a shielded gate MOS device of claim 2, wherein the first type of ion tilt implant dose range: 2X 10 ¹⁹ Atoms/cm ² ～9×10 ²¹ Atoms/cm ² 。

4. The method of manufacturing a shielded gate MOS device of claim 2, wherein the second type of ion tilt implant dose ranges: 2X 10 ¹³ Atoms/cm ² ～8×10 ¹⁵ Atoms/cm ² 。

5. The method of manufacturing a shielded gate MOS device of claim 1, wherein the first type of ions are implanted obliquely through a range of angles: 20-75 degrees; the second type of ion inclined implantation angle range: 20-75 deg.

6. The method of manufacturing a shielded gate MOS device according to any one of claims 1 to 5, wherein an isolation layer is formed on the substrate surfaces on both sides of the trench, and the first type ion tilt implantation and the second type ion tilt implantation are performed on the substrate on both sides of the trench with the isolation layer as a mask, respectively.

7. The method for manufacturing the shielded gate MOS device according to any one of claims 1 to 5, wherein the forming of the shielded gate and the polysilicon gate in the trench at intervals from bottom to top, comprises:

forming a shielding oxide layer, wherein the shielding oxide layer covers the bottom and the side wall surface of the lower part of the groove, the shielding oxide layer is provided with a first cavity area, and the shielding grid is formed in the first cavity area;

and forming a gate oxide layer, wherein the gate oxide layer covers the surfaces of the shielding gate and the shielding oxide layer and the side wall of the upper part of the groove, the gate oxide layer is provided with a second cavity area, and the polysilicon gate is formed in the second cavity area.

8. The method of manufacturing a shielded gate MOS device of claim 7, further comprising, after forming the polysilicon gate:

implanting first type ions into the substrate at two sides of the groove to form a body region; and forming source regions on both sides of the body region by heavily doping the second type ions.

9. A shielded gate MOS device, comprising:

a substrate in which a plurality of grooves are formed;

a shielding gate and a polysilicon gate which are spaced from bottom to top are formed in the groove;

and the substrate at two sides of the groove is provided with a super junction structure of a second type injection region, a first type injection region and a second type injection region.

10. The shielded gate MOS device of claim 9, further comprising:

a shielding oxide layer, wherein the shielding oxide layer is positioned in a gap between the shielding grid and the groove;

and the gate oxide layer is positioned between the shielding gate and the polysilicon gate and between the side wall of the polysilicon gate and the side wall of the groove.