CN116778991A - Apparatus and methods for performing contiguous array operations in memory - Google Patents

Abstract

The present application relates to an apparatus and method for performing sequential array operations in memory. The memory may include a controller configured to cause the memory to: preparing a first plurality of memory cells of a block of memory cells to be programmed from an initialized state of the block of memory cells; programming the first data to the first plurality of memory cells; and in response to receiving a write command associated with a second address corresponding to the block of memory cells and associated with second data prior to successfully verifying programming of the first data to the first plurality of memory cells, preparing a second plurality of memory cells in the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialized state after programming the first data to the first plurality of memory cells.

Description

Apparatus and method for performing contiguous array operations in memory

Related applications

This application claims the benefit of U.S. Provisional Application No. 63/320,367, filed on March 16, 2022, which is hereby incorporated by reference in its entirety.

Technical field

The present disclosure relates generally to memories and, in particular, in one or more embodiments, to apparatus and methods for performing sequential array operations in a memory.

Background technique

Memory (eg, memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. There are many different types of memory, including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory has evolved into a popular source of non-volatile memory for a wide variety of electronic applications. Flash memory typically uses single-transistor memory cells that support high memory density, high reliability, and low power consumption. By programming charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase changes or polarization), changes in the threshold voltage (Vt) of a memory cell determine the data state of each memory cell (e.g., data value). Common uses of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones and portable devices. Removable memory modules, and the use of non-volatile memory continues to expand.

NAND flash memory is a common type of flash memory device, so called because of the logical form in which the basic memory cell configuration is laid out. Typically, memory cell arrays for NAND flash memories are arranged such that the control gates of each memory cell in a row in the array are connected together to form an access line, such as a word line. A column in an array contains a string of memory cells (often called a NAND string) connected in series between a pair of select gates, such as a source select transistor and a drain select transistor. Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variants using more than one selection gate between the memory cell string and the source and/or between the memory cell string and the data line are known.

When programming a memory, the memory cells may be programmed into memory cells commonly referred to as single-level cells (SLC). SLC can use a single memory cell to represent one digit (eg, one bit) of data. For example, in an SLC, a Vt of 2.5V or higher may indicate a programmed memory cell (e.g., represent a logic 0), while a Vt of -0.5V or less may indicate an erased memory cell (e.g., represent a logic 0). 1). Such memories can achieve higher levels of storage capacity by including multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., or combinations thereof, where the memory cells have features that enable more bits to be The data is stored in multiple levels in each memory cell. For example, an MLC may be configured to store two digits of data per memory cell represented by four Vt ranges, and a TLC may be configured to store three digits of data per memory cell represented by eight Vt ranges, The QLC can be configured to store four digits of data per memory cell represented by the sixteen Vt ranges, and so on.

Contents of the invention

One aspect of the present disclosure provides a memory that includes: a memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: respond to receiving a write command associated with a first address and associated with first data, causing a first plurality of memory cells in a memory cell block corresponding to the first address to prepare to proceed from an initialization state of the memory cell block programming; programming the first data to the first plurality of memory cells; and in response to receiving a message corresponding to the first data prior to successfully verifying programming of the first data to the first plurality of memory cells. The write command associated with the second address of the memory cell block and associated with the second data prepares a second plurality of memory cells corresponding to the second address in the memory cell block for programming without requiring Returning the block of memory cells to the initialization state after programming the first data into the first plurality of memory cells.

Another aspect of the present disclosure provides a memory that includes: a memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: respond Upon receipt of a first command associated with a first address of the memory cell array and associated with first data and corresponding to a programming operation, initiating an initial programming sequence to program the first data to the memory cell array A first plurality of memory cells corresponding to the first address in the memory cell block, wherein the initial programming sequence includes a preamble phase, a programming phase, a verification phase and a recovery phase; determine whether the memory is initiating the initial The recovery phase of the programming sequence is preceded by receiving a second command associated with a second address corresponding to the block of memory cells and associated with second data, wherein the second address corresponds to the block of memory cells. a second plurality of memory cells, and wherein the second command corresponds to the programming operation; in response to receiving the second command before initiating the recovery phase of the initial programming sequence, initiating a latter programming sequence to The second data is programmed into a second plurality of memory cells in the block of memory cells corresponding to the second address without performing the recovery phase of the initial programming sequence.

Another aspect of the present disclosure provides a memory that includes: a memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to: respond Upon receiving a first command associated with a first address of the memory cell array and associated with first data, a preamble stage of a programming sequence is performed to cause a memory cell block of the memory cell array corresponding to the A first plurality of memory cells at a first address are prepared for programming, wherein the first command corresponds to a programming operation; and the programming phase of the programming sequence is performed to program the first data to the first plurality of memory cells. ;Performing a verification phase of the programming sequence to verify the programming of the first data to the first plurality of memory cells; Determining whether the memory receives a second address associated with the block of memory cells concatenating a second command associated with second data, wherein the second address corresponds to a second plurality of memory cells of the block of memory cells, and wherein the second command corresponds to the programming operation; in response to receiving the second command, performing an abbreviated preamble phase of a subsequent programming sequence to prepare the second plurality of memory cells of the block of memory cells for programming; and in response to not receiving the second command to perform the recovery phase of the initial programming sequence.

Description of drawings

1A is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment.

Figure IB is a simplified block diagram of a device in the form of a memory module in communication with a host as part of an electronic system, according to another embodiment.

2A-2C are schematic illustrations of portions of a memory cell array that may be used in a memory of the type described with reference to FIG. 1A.

3 is a schematic diagram of a portion of a memory cell array and block selection circuitry that may be used in a memory of the type described with reference to FIG. 1A.

Figure 4 is a schematic diagram of a voltage generation system that may be used in a memory of the type described with reference to Figure 1A.

Figure 5 is a timing diagram of array operation according to an embodiment.

Figure 6 is a block diagram of a command queue that may be used in a memory of the type described with reference to Figure 1A.

Figure 7 is a depiction of an example of interaction of cache registers and data registers, according to an embodiment.

Figure 8A is a simplified depiction of two consecutive array operations of the related art.

Figure 8B is a simplified depiction of two consecutive array operations according to an embodiment.

Figure 9 is a timing diagram of sequential commands to perform array operations, according to an embodiment.

Figure 10A is a flowchart of a method of operating a memory according to an embodiment.

10B is a flowchart of a method of operating a memory according to another embodiment.

11A-11B are flowcharts of a method of operating a memory according to yet another embodiment.

Figure 12A is a flowchart of a method of operating a memory according to yet another embodiment.

Figure 12B is a flowchart of a method of operating a memory according to yet another embodiment.

Detailed ways

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific embodiments are shown by way of illustration. In the drawings, like reference numerals describe generally similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description is not to be taken in a limiting sense.

For example, the term "semiconductor" as used herein may refer to a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" shall be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by base semiconductor structures, and related Other semiconductor structures are well known to those skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, prior processing steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor may include underlying layers containing such regions/junctions.

Unless otherwise apparent from context, the term "conductive" as used herein and its various related forms (eg, conductive, conductively, conducting, conduction, conductivity, etc.) refers to electrical conductivity. Similarly, unless otherwise apparent from context, the term "connecting" as used herein and its various related forms (eg, connect, connected, connection, etc.) means electrically connected by a conductive path.

It is recognized herein that even where values may be expected to be equal, the variability and precision of industrial processes and operations may cause differences from their expected values. These variability and accuracy will generally depend on the technology used in the fabrication and operation of the integrated circuit device. Therefore, if values are expected to be equal, then those values are considered equal regardless of their resulting value.

Programming speed and power efficiency are often important considerations in the design and use of integrated circuit devices, such as semiconductor memories. Various embodiments may facilitate increased programming speed in such memories, and may further facilitate power savings in conjunction with the increased programming speed. In particular, various embodiments may abbreviate and/or omit certain stages of a programming operation in response to receiving a subsequent command, for example, for another programming operation on the same block of memory cells. By abbreviating and/or omitting one or more stages of the programming operation, increased programming speed and power savings may be achieved.

1A is a simplified illustration of a first device in the form of a memory (eg, memory device) 100 communicating with a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to an embodiment block diagram. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. Processor 130 (eg, a controller external to memory device 100) may be a memory controller or other external host device.

Memory device 100 includes an array of memory cells 104 logically arranged in rows and columns. The memory cells of logical rows are typically connected to the same access line (collectively referred to as word lines), while the memory cells of logical columns are typically selectively connected to the same data line (collectively referred to as bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. The memory cells of at least a portion of memory cell array 104 (not shown in FIG. 1A ) can be programmed to one of at least two target data states.

Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104 . Memory device 100 also includes input/output (I/O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 100 and the output of data and status information from memory device 100 . Address register 114 communicates with I/O control circuitry 112 and with row decoding circuitry 108 and column decoding circuitry 110 to latch the address signal prior to decoding. Command register 124 communicates with I/O control circuitry 112 and control logic 116 to latch incoming commands.

A controller (eg, control logic 116 internal to memory device 100 ) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130 , i.e., control logic 116 is Configured to perform array operations (eg, sensing operations [which may include read operations and verify operations], program operations, and/or erase operations) on the memory cell array 104 . Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to the address. Control logic 116 may include instruction register 128, which may represent computer-usable memory for storing computer-readable instructions. For some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

Control logic 116 may also communicate with cache register 118 . Cache register 118 latches incoming or outgoing data as directed by control logic 116 to temporarily store the data while memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from cache register 118 to data register 120 for transfer to memory cell array 104 , and then new data may be latched on the cache register 112 from I/O control circuitry 112 in cache register 118. During a read operation, data may be passed from cache register 118 to I/O control circuitry 112 for output to external processor 130 , and then new data may be passed from data register 120 to cache register 118 . Cache register 118 and/or data register 120 may form (eg, may form part of) the page buffer of memory device 100 . Data register 120 may additionally include sensing circuitry (not shown in FIG. 1A ) that senses the data status of a memory cell of memory cell array 104 , such as by sensing the status of a data line connected to that memory cell. Status register 122 may communicate with I/O control circuitry 112 and control logic 116 to latch status information for output to processor 130 .

Control logic 116 may additionally communicate with temperature sensor 126 . Temperature sensor 126 may sense the temperature of memory device 100 and provide an indication of the temperature (eg, some voltage, resistance level, digital representation, etc.) to control logic 116 . Some examples of temperature sensor 126 may include a thermocouple, resistive device, thermistor, or infrared sensor. Alternatively, temperature sensor 126 may be external to memory device 100 and in communication with external processor 130 . In this configuration, temperature sensor 126 may provide an indication of ambient temperature rather than device temperature. Processor 130 may communicate an indication representing the temperature, such as as a digital representation, across input/output (I/O) bus 134 to control logic 116 .

Trim register 127 may be in communication with control logic 116 . Trimming register 127 may represent volatile memory, a latch, or other storage location, such as a volatile or non-volatile storage location. For some embodiments, trim register 127 may represent a portion of memory cell array 104 . The memory may use trimming to set values for use in array operation, such as voltage levels, timing characteristics, etc., or trimming may be used to selectively activate or deactivate features of the memory.

Memory device 100 receives control signals from processor 130 at control logic 116 through control link 132 . Control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, and write protect WP#. Depending on the nature of memory device 100, additional or alternative control signals (not shown) may additionally be received through control link 132. Memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from processor 130 via multiplexed input/output (I/O) bus 134 and via the I/O Bus 134 outputs data to processor 130 .

For example, a command may be received at I/O control circuitry 112 via input/output (I/O) pins [7:0] of I/O bus 134 and may then be written to the command in register 124. The address may be received at I/O control circuitry 112 via input/output (I/O) pins [7:0] of I/O bus 134 and may then be written to address register 114 . This may be done at I/O control circuitry 112 via input/output (I/O) pins [7:0] for 8-bit devices or input/output (I/O) pins [7:0] for 16-bit devices. 15:0] receives the data and may then write the data into cache register 118. Data may then be written into data register 120 for programming memory cell array 104 . Data can also be output via input/output (I/O) pins [7:0] for 8-bit devices or input/output (I/O) pins [15:0] for 16-bit devices. Although reference may be made to an I/O pin, it may include any conductive node, such as commonly used conductive pads or conductive bumps, that enables electrical connection to memory device 100 through an external device (eg, processor 130).

Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified to the memory device 100 of Figure 1A. It should be appreciated that the functionality of the various block components described with reference to FIG. 1A may not necessarily be separate from distinct components or component portions of the integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform the functionality of more than one block component of FIG. 1A. Alternatively, one or more components or component portions of an integrated circuit device may be combined to perform the functionality of a single block component of FIG. 1A.

Furthermore, although particular I/O pins are described in terms of popular conventions for the reception and output of various signals, it should be noted that the I/O pins (or other I/O node structures) may be used in various embodiments. Other combinations or other numbers of I/O pins (or other I/O node structures).

A given processor 130 may communicate with one or more memory devices 100 (eg, dies). Figure IB is a simplified block diagram of a device in the form of memory module 101 in communication with a host 150 as part of an electronic system, according to another embodiment. Memory device 100 (eg, memory 100 ₀ - 100 ₃ ), processor 130 , control link 132 , and I/O bus 134 may be as described with reference to FIG. 1A . Although the memory module (eg, memory package) 101 of FIG. 1B is depicted with four memory devices 100 (eg, die), the memory module 101 may have some other number of one or more memory devices 100.

Because processor 130 (eg, a memory controller) is between host 150 and memory device 100 , communications between host 150 and processor 130 may involve communication links similar to those used between processor 130 and memory device 100 different communication links. For example, the memory module 101 may be an embedded multimedia card (eMMC) of a solid state drive (SSD). According to existing standards, communication with the eMMC may include a data link 152 (eg, an 8-bit link) for data transfer, a command link 154 for command transfer and device initialization, and a provision for enabling the data link 152 and a clock link 156 on the command link 154 that carries a synchronized clock signal. The processor 130 may autonomously handle many activities, such as power loss detection, error correction, management of defective blocks, wear leveling, and address translation.

FIG. 2A is a schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, that may be used, for example, as part of memory cell array 104 in a memory of the type described with reference to FIG. 1A . Memory array 200A includes access lines (eg, word lines) 202 ₀ - 202 _N , and data lines (eg, bit lines) 204 ₀ - 204 _M , for example. Word line 202 may be connected in a many-to-one relationship to global access lines (eg, global word lines) not shown in FIG. 2A. For some embodiments, memory array 200A may be formed over a semiconductor that may be conductively doped, for example, to have a conductivity type, such as p-type conductivity, for example, to form a p-well, or to have n-type conductivity, for example, to form an n-well. .

Memory array 200A may be arranged into rows (each corresponding to access lines 202) and columns (each corresponding to data lines 204). Each column may contain a series-connected string of memory cells ₍ eg, non-volatile memory cells), such as one of the NAND strings _2060-206M . Each NAND string 206 may be connected (eg, selectively connected) to a common source (SRC) 216 and may contain memory cells 208 ₀ through 208 _N . Memory unit 208 may represent a non-volatile memory unit for storing data. Memory cells 208 ₀ through 208 _N may include memory cells intended for storing data, and may additionally include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to users of the memory, and instead are often incorporated into series-connected strings of memory cells for well-known operational advantages.

Memory cells 208 in each NAND string 206 may be connected in series to a select gate 210 (e.g., a field effect transistor) (e.g., one of select gates 210 ₀ through 210 _M (e.g., which may be a source select transistor, commonly referred to as is the select gate source)) and the select gate 212 (eg, a field effect transistor) (eg, one of the select gates 212 ₀ to 212 _M (eg, which may be a drain select transistor, often referred to as a select gate drain ))between. Select transistors 210 ₀ - 210 _M may be commonly connected to select line 214 , such as source select line (SGS), and select transistors 212 ₀ - 212 _M may be commonly connected to select line 215 , such as drain select line (SGD). . Although depicted as conventional field effect transistors, select gates 210 and 212 may utilize a similar (eg, identical) structure to that of memory cell 208 . Select gates 210 and 212 may represent a plurality of select gates connected in series, with each select gate configured in series to receive the same or independent control signal.

The source of each select gate 210 may be connected to common source 216 . The drain of each select gate 210 may be connected to the memory cell 208 ₀ of the corresponding NAND string 206 . For example, the drain of select gate 210 ₀ may be connected to memory cell 208 ₀ corresponding to NAND string 206 ₀ . Accordingly, each select gate 210 may be configured to selectively connect the corresponding NAND string 206 to common source 216 . The control gate of each select gate 210 may be connected to select line 214 .

The drain of each select gate 212 may be connected to the data line 204 for the corresponding NAND string 206 . For example, the drain of select gate 212 ₀ may be connected to data line 204 ₀ for corresponding NAND string 206 ₀ . The source of each select gate 212 may be connected to the memory cell 208 _N of the corresponding NAND string 206 . For example, the source of select gate 212 ₀ may be connected to the corresponding memory cell 208 _N of NAND string 206 ₀ . Accordingly, each select gate 212 may be configured to selectively connect a corresponding NAND string 206 to a corresponding data line 204 . The control gate of each select gate 212 may be connected to select line 215 .

The memory array in Figure 2A may be a quasi-two-dimensional memory array, and may have a generally planar structure, for example, in which common source 216, NAND string 206, and data line 204 extend in generally parallel planes. Alternatively, the memory array in Figure 2A may be a three-dimensional memory array, for example, in which the NAND strings 206 may extend substantially perpendicular to a plane containing common source 216 and substantially perpendicular to a plane containing data lines 204, containing data lines 204. The plane of may be substantially parallel to the plane containing common source 216 .

As shown in Figure 2A, a typical construction of memory cell 208 includes a data storage structure 234 (eg, floating gate, charge well, or other configured to store charge) that can determine the data state of the memory cell (eg, through a threshold voltage change). structure), and the control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed from one or more conductive materials. In some cases, memory cell 208 may further have a defined source/drain (eg, source) 230 and a defined source/drain (eg, drain) 232 . Control gate 236 of memory cell 208 is connected to (and in some cases forms) access line 202 .

A column of memory cells 208 may be a NAND string 206 or a plurality of NAND strings 206 selectively connected to a given data line 204 . A row of memory cells 208 may be memory cells 208 that are commonly connected to a given access line 202 . A row of memory cells 208 may, but does not necessarily, contain all memory cells 208 that are commonly connected to a given access line 202 . The rows of memory cells 208 may generally be divided into one or more groups of physical pages of memory cells 208 , and the physical pages of memory cells 208 generally include every other memory cell 208 that is commonly connected to a given access line 202 . For example, memory cells 208 commonly connected to access line _202N and selectively connected to even bit lines 204 (eg, bit lines 204 ₀ , 204 ₂ , 204 ₄ , etc.) may be a physical unit of memory cell 208 pages (eg, even memory cells), while memory cells 208 commonly connected to word line _202N and selectively connected to odd bit lines 204 (eg, bit lines 204 ₁ , 204 ₃ , 204 ₅ , etc.) may be memory Another physical page of cell 208 (eg, odd memory cell). Although data lines 204 ₃ to 204 ₅ are not explicitly depicted in FIG. 2A , it is apparent from the drawing that data lines 204 of memory cell array 200A may be numbered consecutively from data line 204 ₀ to data line 204 _M. Other groupings of memory cells 208 that are commonly connected to a given access line 202 may also define physical pages of memory cells 208 . For some memory devices, all memory cells commonly connected to a given access line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which in some embodiments may still be an entire row) that is read during a single read operation or programmed during a single program operation (eg, an upper or lower page of memory cells) may be Treated as a logical page of memory cells. A block of memory cells may include those memory cells configured to be erased together, such as all memory cells connected to access lines 202 ₀ - 202 _N (eg, all NAND strings 206 sharing a common access line 202 ). Unless explicitly distinguished, references herein to a page of memory cells refer to the memory cells of a logical page of memory cells.

Although the example of FIG. 2A is discussed in connection with NAND flash memory, the embodiments and concepts described herein are not limited to specific array architectures or structures and may include other structures (e.g., SONOS or other data storage structures configured to store charge ) and other architectures (e.g., AND arrays, NOR arrays, etc.).

FIG. 2B is another schematic diagram of a portion of a memory cell array 200B that may be used, for example, as part of a memory cell array 104 in a memory of the type described with reference to FIG. 1A . Like-numbered elements in Figure 2B correspond to the description as provided with respect to Figure 2A. Figure 2B provides additional details of an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate vertical structures that may contain semiconductor pillars, which may be solid or hollow, wherein portions of the pillars may serve as channel regions for the memory cells of the NAND string 206, such as when the memory is activated. The region through which current can flow in a cell (such as a field-effect transistor). NAND strings 206 may each be selectively connected to bit lines 204 ₀ - 204 _M via select transistor 212 (eg, which may be a drain select transistor, often referred to as select gate drain), and via select transistor 210 (eg, may be A source select transistor, often referred to as a select gate source, is selectively connected to common source 216 . Multiple NAND strings 206 may be selectively connected to the same bit line 204. A subset of the NAND strings 206 may be connected to their respective data lines 204 by biasing the select lines 215 ₀ to 215 _K to selectively activate specific select transistors 212 , respectively, between the NAND string 206 and the data line 204 . Select transistor 210 may be activated by biasing select line 214 . Each access line 202 may be connected to multiple rows of memory cells of memory array 200B. Rows of memory cells commonly connected to each other by specific access lines 202 may be collectively referred to as a hierarchy.

Three-dimensional NAND memory array 200B may be formed on peripheral circuitry 226 . Peripheral circuitry 226 may represent various circuitry used to access memory array 200B. Peripheral circuitry 226 may include complementary circuit elements. For example, peripheral circuitry 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate in a process commonly referred to as CMOS or complementary metal oxide semiconductor. Although CMOS generally no longer utilizes strictly metal-oxide-semiconductor construction due to advances in integrated circuit manufacturing and design, the CMOS nomenclature is retained for convenience.

FIG. 2C is yet another schematic diagram of a portion of a memory cell array 200C that may be used, for example, as part of the memory cell array 104 in a memory of the type described with reference to FIG. 1A . Like-numbered elements in Figure 2C correspond to the description as provided with respect to Figure 2A. Memory cell array 200C may include series-connected memory cell strings (eg, NAND strings) 206, access (eg, word) lines 202, data (eg, bit) lines 204, select lines 214 ( For example, source select line), select line 215 (eg, drain select line), and source 216. For example, a portion of memory cell array 200A may be part of memory cell array 200C. Figure 2C depicts grouping NAND strings ₂₀₆ into blocks of memory cells 250, such as blocks of memory cells _2500-250L . A block of memory cells 250 may be a grouping of memory cells 208 that may be erased together in a single erase operation, sometimes referred to as an erase block. Each block of memory cells 250 may represent those NAND strings 206 commonly associated with a single select line 215, such as select line ₂₁₅₀ . Source 216 of memory cell block ₂₅₀₀ may be the same source as source 216 of memory cell block _250L . For example, each block of memory cells 250 ₀ - 250 _L may be selectively commonly connected to source 216 . The access lines 202 and select lines 214 and 215 of one memory cell block 250 may not have direct connections with the access lines 202 and select lines 214 and 215 of any other memory cell block 250 of the memory cell blocks 250 ₀ - 250 _L , respectively.

Data lines 204 ₀ - 204 _M may be connected (eg, selectively connected) to buffer portion 240 , which may be part of a page buffer of a memory. Buffer portion 240 may _correspond to a memory plane (eg, a set of memory cell blocks _2500-250L ). Buffer portion 240 may include sensing circuitry (not shown in Figure 2C) for sensing data values indicated on corresponding data lines 204. Buffer portion 240 may include a portion of data register 120 and _a portion of cache register 118 corresponding to blocks of memory cells _2500-250L .

3 is a schematic diagram of a portion of a memory cell array and block selection circuitry that may be used in a memory of the type described with reference to FIG. 1A , depicting local access lines (eg, local word lines) 202 and global access lines ( For example, a many-to-one relationship between global word lines) 302.

As depicted in FIG. 3 , a plurality of memory cell blocks 250 may have their local access lines (eg, local word lines) 202 collectively selectively connected to a plurality of global access lines (eg, global word lines) 302 . For simplicity, drain and source select lines and their corresponding transistors are not depicted. Although FIG. 3 only depicts memory cell blocks 250 ₀ and 250 _L (block 0 and block L), additional memory cell blocks 250 may have their local access lines 202 commonly connected to the global access line 302 in a similar manner. Similarly, although FIG. 3 depicts only four local access lines 202 for each memory cell block, memory cell blocks 250 may include fewer or more local access lines 202 (and may be used in a similar manner with fewer or more local access lines 202 ). More global access lines 302 are associated). Memory cell blocks 250 ₀ - 250 _L may belong to a single memory cell plane, such as a grouping of memory cell blocks 250 that are commonly associated with a single buffer portion 240 .

To facilitate memory array operations for a particular block of memory cells 250 that are commonly coupled to a given set of global access lines 302 , each block of memory cells 250 may have a corresponding set of block select transistors that have a one-to-one relationship with its local access lines 202 346. The control gates of the set of block select transistors 346 of a given memory cell block 250 may be commonly connected to a corresponding block select line 348 . For example, for a block of memory cells 250 ₀ , local access line 202 ₀₀ may be selectively connected to global access line 302 ₀ through block select transistor 346 ₀₀ and local access line 202 ₁₀ may be selected through block select transistor 346 ₁₀ is selectively connected to global access line 302 ₁ , local access line 202 ₂₀ is selectively connected to global access line 302 ₂ via block select transistor 346 ₂₀ , and local access line 202 ₃₀ is selectively connectable to global access line 302 2 via block select transistor 346 ₃₀ Block select transistors 346 ₀₀ - 346 ₃₀ are selectively connected to global access line 302 ₃ in response to control signals received on block select line 348 ₀ . The block select transistors 346 of the memory cell block 250 may be collectively referred to as block select circuitry, and such block select circuitry for the memory cell block 250 is often referred to as a string driver. For example, such block selection circuitry may be formed in peripheral circuitry 226 . Each block of select transistors 346 may represent a selective connection of local access line 202 to its corresponding global access line 302 . A voltage generation system 344 may be connected (eg, selectively connected) to each global access line 302 to apply a corresponding voltage level to each global access line 302 to perform array operations.

Figure 4 is a schematic diagram of a voltage generation system 344 that may be used in a memory of the type described with reference to Figure 1A. As depicted, voltage _generation system 344 may include several voltage generation devices 460, such as voltage generation devices _4600-460X . For example, each voltage generating device 460 may represent a charge pump.

Each voltage generating device 460 may be selectively connected to a corresponding one or more of global access lines 302 (eg, global access lines 302 ₀ - 302 _N ). Each voltage generation device 460 may be configured to generate one or more voltage levels to be applied to its corresponding one or more global access lines 302 and local access lines 202 connected thereto during array operation. For example, during a programming operation, voltage generation device 460 ₀ may be configured to generate a programming voltage to apply to a local access line 202 connected to a memory cell 208 selected for programming, while voltage generation device 460 ₁ may be Configured to generate a pass voltage for application to local access lines 202 connected to other memory cells 208 in the same NAND string 206 as the selected memory cell 208 . The applied voltage level may change during array operation. For example, a selected access line receiving the programming voltage may first reach the pass voltage and then rise to the programming voltage. Programming operations using more than one pass voltage level and/or another isolation voltage level or levels are known, and additional voltage generation means 460 can be used to generate such additional voltage levels to apply to their respective global accesses. Line 302.

Figure 5 is a timing diagram of array operation according to an embodiment. In the example of Figure 5, array operations may represent programming operations, such as cache programming operations. At time t0, a controller of the memory (eg, control logic 116) may receive a first cycle of commands (eg, a write command). The first cycle of commands can be received from the command queue. In the example of Figure 5, the first loop description of the command is 80h. However, specific command codes are provided by way of example and, therefore, have no limiting significance. At times t1 and t2, the controller of the memory may receive column addresses, such as receiving a first packet C1 of column addresses at time t1 and receiving a second packet C2 of column addresses at time t2. The column address identifies the target column of the memory cell array for a programming operation. At times t3-t5, the controller of the memory may receive row addresses, such as receiving a first packet R1 of row addresses at time t3, receiving a second packet R2 of row addresses at time t4, and receiving a row address at time t5. The third packet of address is R3. The row address identifies the target row of the memory cell array for the programming operation, and in combination with the column address, identifies the target block of memory cells for the programming operation. It should be appreciated that although two packets of column addresses and three packets of row addresses are depicted in Figure 5, the size of the column addresses and row addresses will depend on the addressable space of the memory such that less or less may be utilized as needed. More address packages. From time t6 to time t7, the memory may receive one or more data packets. Data packets may be delayed by the address cycle to data load time (t _ADL ) 564 after the last address packet is received. At time t8, the memory's controller may receive a second cycle of commands. In the example of Figure 5, the second loop of the command is illustrated as 15h. However, specific command codes are provided by way of example and, therefore, have no limiting significance. Data packets may be loaded into cache register 118 for subsequent transfer to data register 120 .

The period after the command is completed, such as in this example, after the first and second cycles in which the memory's controller receives the command, and before the memory transitions the RDY status indicator (e.g., Status Register 6 or SR) This may correspond to a period of time for loading cache registers 118 or other preparatory activities before programming data into the memory cell array. For example commands, this may be called t _WB . Time t _WB 566 may correspond to the time period from time t8 to time t9.

At time t9, the memory may indicate that cache register 118 is busy, eg, contains valid data and cannot load new data, and may complete its transfer of data to data register 120 at time t10. The period of time from time t9 to time t10 corresponding to the example command may be referred to as cache busy time (t _CBSY ) 568. At time tlO, after the expiration of time t _CBSY 568, the memory may transition its RDY status indicator to its initial value, thus indicating that the controller is available to accept commands for the next array operation. The memory's controller may then receive the first cycle of the next command.

Commands received by the memory may be queued before commands being received by the memory's controller. Figure 6 is a block diagram of a command queue 670 that may be used in a memory of the type described with reference to Figure 1A. Command queue 670 may be part of command register 124 and/or address register 114 . Command queue 670 may receive commands, and optionally their associated addresses and/or data, from I/O control circuitry 112 and may forward the commands, and optionally other received data, when control circuitry 116 is ready for processing. The associated address and/or data is provided to control circuitry 116 . Command queue 670 may represent a first-in-first-out queue corresponding to a portion (eg, only a portion) of memory cell array 104 . For example, command queue 670 may queue commands for accessing a specific block set of memory cells 250 (eg, a memory plane). The memory may additionally include one or more additional command queues 670 for queuing commands for accessing different portions of the memory cell array 104 (eg, different memory planes). Control circuitry 116 may communicate with command queue 670 and may know the next command for accessing its corresponding portion of memory cell array 104 .

Figure 7 is a depiction of an example of interaction of cache register 118 and data register 120, according to an embodiment. In FIG. 7, cache register 118 is depicted as containing eight storage registers 772 for storing data for memory programming operations, and data register 120 is depicted as containing eight storage registers 774 for storing data transferred from cache register 118. Data used for programming operations. Although it should be appreciated that a typical memory may contain significantly more storage registers 772 and 774, a simplified set of storage registers will be used to describe the interaction of cache registers 118 and data registers 120 during programming operations.

At time 776 ₀ , storage register 772 of cache register 118 may be loaded with data received in association with the write command. In the example of Figure 7, this data byte is represented as 11001000. Although data register 120 may contain data at this time, its value is irrelevant.

At time 776 ₁ , the data in storage register 772 of cache register 118 (eg, 11001000) may be transferred to storage register 774 of data register 120 such that cache register 118 and data register 120 contain the data associated with the write command. Same data. The memory may then be able to program the data associated with the write command to the memory cell array.

At time 776 ₂ , while the memory is programming the data of data register 120 to the memory cell array, storage register 772 of cache register 118 may be loaded with data received in association with a later write command. In the example of Figure 7, this data byte is represented as 00111001.

At time ₇₇₆₃ , the data in storage register 772 of cache register 118 (eg, 00111001) may be transferred to storage register 774 of data register 120 such that cache register 118 and data register 120 contain information related to the subsequent write command. The same data linked. The memory may then be able to program the data associated with the later write command to the memory cell array.

At time 776 ₄ , while the memory is programming the data of data register 120 to the memory cell array, storage register 772 of cache register 118 may be loaded with data received in association with a subsequent write command. In the example of Figure 7, this data byte is represented as 01010010. This process can continue for additional write commands received. Since the subsequent write command cannot be processed until the data from the previous write command in cache register 118 is transferred to data register 120, it may be desirable to reduce the cache busy time t _CBSY .

Figure 8A is a simplified depiction of two consecutive array operations of the related art. Figure 8A may depict two consecutive programming operations. Figure 8A may depict a simplified representation of access line voltage levels for both selected access lines and unselected access lines during a programming operation.

Programming operations can contain multiple stages. At time t0 of Figure 8A, a preamble phase 880 of the first programming operation may begin. The preamble stage 880 may represent the time when the memory is ready to program data into the memory cell array, starting from an initialization state, for example. For example, the address data may be examined to determine which memory cell block and which memory cell rows of that memory cell block contain the memory cells selected for programming. The memory may perform further checks to determine whether one or more of the memory cells selected for programming have been designated for replacement as redundant memory cells, and if so, mask those addresses from the act of selecting redundant memory cells. The memory may check the temperature sensor to determine if any adjustments to the trim value should be made, or if any notifications should be issued. The memory may further activate a voltage generating system associated with the selected block of memory cells, and its associated voltage generating device, and may activate other peripheral circuitry associated with accessing the selected block of memory cells.

At time tl of Figure 8A, the programming phase 882 of the first programming operation may begin. Programming phase 882 may represent the time used to effect programming of data to the memory cell array. For example, a programming pulse may be applied to an access line connected to a memory cell selected for programming, while a pass voltage may be applied to the remaining access line of a series-connected string of memory cells containing the memory cell selected for programming. Wire.

At time t2 of Figure 8A, the verify phase 884 of the first programming operation may begin. Verification phase 884 may represent the time used to determine whether data has been successfully programmed to the selected memory cell. For example, a read voltage may be applied to an access line connected to a memory cell selected for programming, while a pass voltage may be applied to the remaining access lines of a series-connected string of memory cells containing the selected memory cell. The access and select lines of the selected memory cell block may then be discharged to, for example, a reference potential, which may be OV, ground, or Vss.

At time t3 of Figure 8A, the recovery phase 886 of the first programming operation may begin. Recovery phase 886 may represent the time for returning the block of memory cells to an initialized state. This may include deactivating the voltage generating system for the selected block of memory cells, including deactivating its voltage generating means, which may further include discharging its voltage generating means to, for example, a reference potential. Recovery stage 886 may additionally include biasing a subset of access lines (e.g., drain-side access lines from selected memory cell locations) to a positive voltage level to shift from the channel of the series-connected string of memory cells. The trapped charge carriers are removed and the access lines are then discharged again to, for example, a reference potential. Other peripheral circuitry involved in accessing the selected block of memory cells may also be deactivated. For example, the block select transistor may be deactivated, as well as the remaining circuitry of column decoding circuitry 110 and row decoding circuitry 108 .

At time t4 of Figure 8A, a preamble phase 880 of the second programming operation may begin. The preamble phase 880 of the second programming operation may include all types of activity of the preamble phase 880 , even if pointing to a different set of selected memory cells corresponding to the address associated with the subsequent write command and to programming versus the subsequent write command. associated data. Specifically, the memory may initiate the second programming operation from an initialized state. At time t5 of Figure 8A, the programming phase 882 of the second programming operation may begin. At time t6 of Figure 8A, the verify phase 884 of the second programming operation may begin. At time t7 of Figure 8A, the recovery phase 886 of the second programming operation may begin. The program phase 882, verify phase 884, and restore phase 886 of the second programming operation may include all activity types of the program phase 882, verify phase 884, and restore phase 886 of the first programming operation, respectively, even if the pointer corresponds to the subsequent write command. The addresses associated with the different sets of selected memory cells point to the programming data associated with the subsequent write command.

Figure 8B is a simplified depiction of two consecutive array operations in accordance with an embodiment. Figure 8B may depict two consecutive programming operations. Figure 8B may depict a simplified representation of access line voltage levels for both selected access lines and unselected access lines during a programming operation.

Programming operations can contain multiple stages. At time t0 of Figure 8B, a preamble phase 880 of the first programming operation may begin. The preamble stage 880 may represent the time when the memory is ready to program data into the memory cell array, starting from an initialization state, for example. For example, the address data may be examined to determine which memory cell block and which memory cell rows of that memory cell block contain the memory cells selected for programming. The memory may perform further checks to determine whether one or more of the memory cells selected for programming have been designated for replacement as redundant memory cells, and if so, mask those addresses from the operation of selecting redundant memory cells. The memory may check the temperature sensor to determine if any adjustments to the trim value should be made, or if any notifications should be issued. The memory may further activate a voltage generating system associated with the selected block of memory cells, and its associated voltage generating device, and may activate other peripheral circuitry associated with accessing the selected block of memory cells.

At time tl of Figure 8B, the programming phase 882 of the first programming operation may begin. Programming phase 882 may represent the time used to effect programming of data to the memory cell array. For example, a programming pulse may be applied to an access line connected to a memory cell selected for programming, while a pass voltage may be applied to the remaining access line of a series-connected string of memory cells containing the memory cell selected for programming. Wire.

At time t2 of Figure 8B, the verify phase 884 of the first programming operation may begin. Verification phase 884 may represent the time used to determine whether data has been successfully programmed to the selected memory cell. For example, a read voltage may be applied to an access line connected to a memory cell selected for programming, while a pass voltage may be applied to the remaining access lines of a series-connected string of memory cells containing the selected memory cell. For some embodiments, the access and select lines of the selected memory cell block may then be discharged to, for example, a reference potential, which may be OV, ground, or Vss. For other embodiments, the access lines and select lines of the selected memory cell block may have their voltage levels intercepted from the sensing portion of the verify stage 884, such as depicted by the dashed lines for the access lines of the selected memory cell block.

In contrast to related art (eg, further contrast), the recovery phase 886 may not be performed after the verification phase 884. These activities may be omitted or reduced where the latter programming operation targets the same block of memory cells. Thus, at time t3, the memory cell block may not return to the initialized state. The voltage generation system for the selected memory cell block and its voltage generation means may remain active. Before initiating the next programming stage 882, the subset of access lines of the selected memory cell block may not be biased from the reference potential to a positive voltage level. Peripheral circuitry involved in accessing the selected block of memory cells may also remain active. For example, the block select transistor may remain active, and the remaining circuitry of row decoding circuitry 108 may also remain active.

At time t4 of Figure 8B, a reduced preamble phase 888 of the second programming operation may begin. Because the block of memory cells does not return to an initialized state, certain activities of the preamble phase 880 may be omitted or reduced. For example, knowing that the second programming operation is for the same block of memory cells, the address data may not be checked (eg, may not be checked again) to determine which block of memory cells contains the memory cells selected for programming. In the case where redundancy utilizes replacement columns of memory cells, the memory may not perform a check to determine whether one or more of the memory cells selected for programming have been designated for replacement as redundant memory cells, as this may have been The act of selecting redundant memory cells obscures those addresses. The memory may assume that it experiences the same temperature (eg, ambient or device temperature) and therefore may not check the temperature sensor. The voltage generation system associated with the selected memory cell block and its associated voltage generation device may remain active, and other peripheral circuitry associated with accessing the selected memory cell block may also remain active. Regarding the voltage generation system, the memory may only change the multiplexing of voltage generation devices, taking into account different selected access lines to receive the programming voltage, and different unselected access lines to receive the pass voltage.

At time t4 of Figure 8B, the programming phase 882 of the second programming operation may begin. At time t5 of Figure 8B, the verify phase 884 of the second programming operation may begin. The program phase 882 and verify phase 884 of the second programming operation may include all activity types of the program phase 882 and verify phase 884 of the first programming operation, respectively, even if a different pointer corresponding to the address associated with the subsequent write command is selected. A set of memory cells and a pointer to program the data associated with the subsequent write command.

In the case where the next subsequent command is for a different block of memory cells, or for a different array operation, such as a read operation, at time t6, the recovery phase 886 of the second programming operation may begin. This recovery phase 886 of the second programming operation may include all types of activity of the recovery phase 886 described with reference to the first programming operation of Figure 8A, even for a different set of selected memory cells. Alternatively, where the next subsequent command is for the same array operation of the same block of memory cells, the memory may continue to the next programming stage 882 at time t6 without performing the recovery stage 886.

Figure 9 is a timing diagram of sequential commands to perform array operations, according to an embodiment. The command may represent a cache programming command that performs a series of cache programming operations on the same block of memory cells. Elements of the command may correspond to the description of FIG. 5 . Thus, at time A, a first cycle of a first command is received (eg, by a controller of a memory), followed by its associated address and data, and a second cycle of the first command. Cache busy time (tCBSY ₁ ) 968 ₁ may represent the time for the preamble phase 880 , programming phase 882 , and verification phase 884 as discussed with reference to FIG. 8B . Recovery phase 886 may be omitted because the controller (eg, control logic 116 ) knows that the latter (eg, second) command was queued for processing at time B and was for the same type of array operation pointing to the same block of memory cells. . Due to the omission of the recovery phase 886, the cache busy time (tCBSY ₁ ) 968 ₁ can be expected to be shorter in duration than related art cache busy times for the same array operation.

At time B, a first cycle of the second command is received (eg, by the controller), followed by its associated address and data, and a second cycle of the second command. Cache busy time (tCBSY ₂ ) 968 ₂ may represent the time used for the abbreviated preamble phase 888 , programming phase 882 , and verification phase 884 as discussed with reference to FIG. 8B . Because the controller (eg, control logic 116) knows that the latter (eg, third) command is queued for processing at time C and knows that it is for the same type of array operation directed to the same block of memory cells, it can again Recovery phase 886 is omitted. Due to the abbreviated preamble phase 888 that may be made by not returning the block of memory cells and associated access circuitry to an initialized state after programming the data associated with the first command, and the typical omission of the recovery phase 886, high speed The cache busy time (tCBSY ₂ ) 968 ₂ can be expected to last shorter than the cache busy time (tCBSY ₁ ) 968 ₁ .

At time C, a first cycle of the third command is received (eg, by the controller), followed by its associated address and data, and a second cycle of the third command. The third programming operation may be performed, for example, in response to the controller (eg, control logic 116) knowing that a later (eg, fourth) command is queued for processing at time D and is known to be for the same type pointing to the same block of memory cells. array operation and enters the cache busy time (tCBSY ₂ )968 ₂ again. Alternatively, in response to the controller (e.g., control logic 116) knowing that no later command was received (e.g., via memory) and queued, or that the later command is for a different type of array operation and/or is directed to a different memory unit block, the controller may cause the memory to perform a reduced preamble phase 888, programming phase 882, verify phase 884, and recovery phase 886 to bring the memory cell block and associated access circuitry into an initialization state, thereby causing a longer cache busy time .

Knowing that the latter command is for the same array operation and points to the same block of memory cells may include determining whether the command loop indicates the same array operation, such as a programming operation, and whether the address associated with the latter command points to the same block of memory cells.

Figure 10A is a flowchart of a method of operating a memory according to an embodiment. The method may represent actions associated with successive array operations (eg, programming operations) performed by a memory. The method may be in the form of computer-readable instructions stored, for example, in instruction register 128 . Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause associated components of memory to perform the method.

At 1001, in response to receiving a first command associated with a first address of a memory cell array and associated with first data, the memory may initiate an initial programming sequence to program the first data to the memory A first plurality of memory cells corresponding to the first address in the memory cell block of the cell array. The initial programming sequence may include a preamble phase, a programming phase, a verification phase, and a recovery phase. The first command may be a write command for a programming operation. For example, the first command may be a cache programming command. The first plurality of memory cells may correspond to a particular row (eg, a logical row) of a block of memory cells of the array of memory cells.

At 1003, it may be determined whether a second command associated with a second address of the memory cell array and associated with second data has been received prior to performing the recovery phase of the initial programming sequence. The second command may be a write command for a programming operation. The second command may be for the same array operation as the first command (eg, the same programming operation), and the second address may correspond to the same block of memory cells of the memory cell array as the first address. The second command may be received by the memory and placed in the command queue before being processed by the controller.

At 1005, in response to receiving the second command prior to initiating the recovery phase of the initial programming sequence, the memory may initiate a subsequent programming sequence to program the second data into a second plurality of memories in the block of memory cells corresponding to the second address. unit without the need to perform the recovery phase of the initial programming sequence. The second plurality of memory cells may correspond to different rows (eg, logical rows) of memory cells. Alternatively, at 1007, in response to a second command not being received prior to initiating the recovery phase of the initial programming sequence, or the next command being directed to a different array operation and/or to a different block of memory cells, the memory may perform the initial programming sequence recovery stage.

10B is a flowchart of a method of operating a memory according to another embodiment. The method may represent actions associated with successive array operations (eg, programming operations) performed by the memory continuation of the method of FIG. 10A. The method may be in the form of computer-readable instructions stored, for example, in instruction register 128 . Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause associated components of memory to perform the method.

At 1005', which may represent a continuation of 1005 of Figure 10A, the memory may initiate a subsequent programming sequence to program second data into a second plurality of memory cells corresponding to a second address in the block of memory cells. The latter programming sequence may include abbreviated preamble, programming, verification and recovery phases. The activity types of the abbreviated predecessor phase of the latter programming sequence may be an appropriate subset of the activity types of the preceding phase of the initial programming sequence. That is, the abbreviated predecessor phase of a subsequent programming sequence may contain only the types of activities performed by the preceding phase of the initial programming sequence, and the preceding phase of the initial programming sequence may contain the abbreviated predecessor phase of the subsequent programming sequence. Types of additional activities not performed during the sequence phase. The programming phase, verification phase and recovery phase (e.g., optional recovery phase) of the latter programming sequence may include all activity types of the programming phase, verification phase, and recovery phase (e.g., optional recovery phase) of the initial programming sequence (e.g., optional recovery phase) For example, even if the same activity is directed to different selected memory cells).

At 1009, it may be determined whether a third command associated with a third address of the memory cell array and associated with third data has been received prior to initiating the recovery phase of the subsequent programming sequence. The third command may be a write command for programming operations. The third command may be used for the same array operation as the first command and the second command, and the third address may correspond to the same memory cell block of the memory cell array as the first address and the second address. The third command may be received by the memory and placed in the command queue before being processed by the controller.

At 1011, in response to receiving the third command before initiating the recovery phase of the latter programming sequence, the memory may initiate the latter programming sequence to program third data into a third plurality of memory cells corresponding to the third address. memory cells and there is no need to perform a recovery phase of the latter programming sequence, such as after programming the second data to the second plurality of memory cells. The third plurality of memory cells may correspond to different rows (eg, logical rows) of memory cells. Alternatively, at 1013, in response to a third command not being received before initiating the recovery phase of the latter programming sequence, or the next command being directed to a different array operation and/or to a different block of memory cells, the memory may perform the latter. The recovery phase of the programming sequence. The process of 1005' through 1013 may be repeated for one or more additional commands for the same array operation and the same block of memory cells.

11A-11B are flowcharts of a method of operating a memory according to yet another embodiment. The method may represent actions associated with successive array operations (eg, programming operations) performed by a memory. The method may be in the form of computer-readable instructions stored, for example, in instruction register 128 . Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause associated components of memory to perform the method.

At 1121, in response to receiving a first command associated with the first address and associated with the first data, a preamble stage of the programming sequence may be performed to cause the block of memory cells in the array of memory cells to correspond to the first address. A first plurality of memory cells are ready for programming. The first plurality of memory cells may be a page (eg, a logical page) of memory cells of a block of memory cells. The first command may be a write command to perform a programming operation. For example, the first command may be a cache programming command.

At 1123, the programming phase of the programming sequence may be performed to program the first data to the first plurality of memory cells. At 1125, a verification phase of the programming sequence may be performed to verify whether the first data was successfully programmed to the first plurality of memory cells. The process may then continue to 1127 without additional verification. Optionally, at 1129, it may be determined whether the verification phase is passed, such as whether first data was successfully programmed to the first plurality of memory cells. In response to determining that the verification phase is passed, the process may continue to 1127 . In response to determining that the verification phase has not passed, eg, first data was not successfully programmed to the first plurality of memory cells, the process may return to 1123 to continue programming first data to the first plurality of memory cells. This programming/verification process may be repeated until the verification phase is determined to be passed, at which time the process may continue to 1127 .

At 1127, it may be determined whether a second command associated with the second address and associated with the second data has been received. The second command may be a write command that performs programming operations on different plurality of memory cells (eg, the same programming operation). The second command may be the same command as the first command. For example, the first command may be a page cache programming command that complies with the Open NAND Flash Interface (ONFI 5.0) standard specification and has a structure of a first cycle of 80h and a second cycle of 15h. Therefore, the second command is also May have an 80h/15h structure. Alternatively, ONFI 5.0 additionally provides a close page cache programming command with a structure of 80h first loop and 10h second loop, indicating the end of cache programming. Therefore, the second command may be the same as the first Commands are different, but can still direct the same array operation and point to the same block of memory cells.

The second command may be received by the memory and placed in the command queue before being processed by the controller. The second address may correspond to a block of memory cells. In response to determining that the second command has been received at 1127, the process may continue to 1131. Alternatively, at 1133, in response to the second command not being received, or the next command being directed to a different array operation and/or to a different block of memory cells, the memory may perform a recovery phase of the programming sequence to place the block of memory cells in In initialization state.

At 1131, a reduced preamble stage of the latter programming sequence may be performed to prepare a second plurality of memory cells in the block of memory cells corresponding to the second address for programming. The second plurality of memory cells may be pages (eg, logical pages) of memory cells of a block of memory cells.

At 1135, the programming phase of the latter programming sequence may be performed to program second data to the second plurality of memory cells. At 1137, a verification phase of the latter programming sequence may be performed to verify whether the second data was successfully programmed to the second plurality of memory cells. The process may then continue to 1139 without additional verification. Optionally, at 1141, it may be determined whether the verification phase is passed, such as whether second data was successfully programmed to the second plurality of memory cells. In response to determining that the verification phase is passed, the process may continue to 1139 . In response to a determination that the verification phase was not passed, eg, second data was not successfully programmed to the second plurality of memory cells, the process may return to 1135 to continue programming second data to the second plurality of memory cells. This programming/verification process may be repeated until the verification phase is determined to be passed, at which time the process may continue to 1139 .

At 1139, it may be determined whether a third command associated with a third address and associated with third data has been received. The third command may be a write command that performs programming operations on different plurality of memory cells (eg, the same programming operation). The third command may be the same command as the first command and the second command. The third command may be received by the memory and placed in the command queue before being processed by the controller. The third address may correspond to a block of memory cells. In response to determining that the third command has been received at 1139, the process of 1131 to 1139 may be repeated, but for the third command and its associated third address and third data. Alternatively, at 1143, in response to the third command not being received, or the next command being directed to a different array operation and/or to a different block of memory cells, the memory may perform a recovery phase of the latter programming sequence to convert the block of memory cells. Put in initialization state.

The activity types of the abbreviated preceding phase of the latter programming sequence may be an appropriate subset of the activity types of the preceding phases of the programming sequence (eg, the initial programming sequence). The programming phase, verification phase and recovery phase (eg, optional recovery phase) of the latter programming sequence may include all activity types of the programming phase, verification phase, and recovery phase (eg, optional recovery phase) of the initial programming sequence.

Figure 12A is a flowchart of a method of operating a memory according to yet another embodiment. The method may represent actions associated with successive array operations (eg, programming operations) performed by a memory. The method may be in the form of computer-readable instructions stored, for example, in instruction register 128 . Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause associated components of memory to perform the method.

at 1241, in response to receiving a write command associated with the first address and associated with the first data, preparing a first plurality of memory cells of the block of memory cells for programming from an initialization state of the block of memory cells, As described previously. The first plurality of memory cells may correspond to a first address. The initialization state of the memory cell block may include discharging access lines and select lines of the memory cell block to a reference potential and deactivating block select circuitry corresponding to the memory cell block. The initialization state of the memory cell block may additionally include deactivating the voltage generating device corresponding to the memory cell block. At 1243, the memory may program the first data to the first plurality of memory cells.

At 1245, in response to receiving a write command associated with the second address corresponding to the block of memory cells and associated with the second data prior to successfully verifying programming of the first data to the first plurality of memory cells, for example, The memory may prepare the second plurality of memory cells of the block of memory cells for programming without returning the block of memory cells to an initialized state after programming the first data to the first plurality of memory cells. The second plurality of memory cells may correspond to the second address.

By not returning the block of memory cells to an initialized state after programming the first data into the first plurality of memory cells, the access and select lines can trap the desired voltage closer to the reference potential than the reference potential for programming the second data. level of voltage level. Similarly, by maintaining activation of the voltage generating means corresponding to the memory cell block, less time is required for it to reach its desired voltage level. Additionally, a block of memory cells can remain selected by maintaining activation of the block selection circuitry. Each of these efficiencies, individually or in combination, may reduce the time required to program the second data to the second plurality of memory cells. Additionally, by not spending time returning the block of memory cells to an initialized state, the time required to program the first data to the first plurality of memory cells may also be reduced, thereby permitting the programming of the second data to the second plurality of memory cells. Start earlier than when returning the block of memory cells to an initialized state.

Optionally, at 1247, in response to not receiving a command for access to the block of memory cells before successfully verifying programming of the first data to the first plurality of memory cells, the memory may program the first data to The first plurality of memory cells then returns to the initialized state.

Optionally, at 1249, in response to receiving a next command for a different array operation or for access to a different block of memory cells prior to successfully verifying programming of the first data to the first plurality of memory cells, the memory The block of memory cells may be returned to an initialized state after programming the first data to the first plurality of memory cells.

Figure 12B is a flowchart of a method of operating a memory according to yet another embodiment. The method may represent actions associated with successive array operations (eg, programming operations) performed by the memory continuation of the method of Figure 12A. The method may be in the form of computer-readable instructions stored, for example, in instruction register 128 . Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause associated components of memory to perform the method.

At 1251, continuing from 1245, the memory may program the second data to the second plurality of memory cells. At 1253, in response to receiving a write command associated with a different address corresponding to the block of memory cells and associated with different data, the memory may prepare a different plurality of memory cells of the block of memory cells for programming and set the different Data is programmed into different multiple memory cells without returning the block of memory cells to an initialized state. Different plurality of memory cells may correspond to different addresses.

At 1255, it may be determined whether an additional write command associated with the address corresponding to the block of memory cells has been received. If so, then the process may return to 1253 to again prepare for and program the data associated with the additional write command. This process may be repeated for one or more additional write commands received for access to the block of memory cells, i.e., determining whether an additional write command associated with the address corresponding to the block of memory cells has been received and then Providing for programming of data associated with additional write commands and programming the data associated with the additional write commands. If such a write command is not received at 1255 before successfully verifying the programming of the data associated with the previous write command, the process may continue to 1257 and return the block of memory cells to an initialized state.

in conclusion

Although specific embodiments have been illustrated and described herein, it will be understood by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those skilled in the art. This application is therefore intended to cover any adaptations or variations of the embodiments.

Claims (22)

1. A memory, comprising:

a memory cell array; and

a controller for access to the array of memory cells, wherein the controller is configured to cause the memory to:

in response to receiving a write command associated with a first address and with first data, preparing a first plurality of memory cells in a block of memory cells corresponding to the first address for programming from an initialized state of the block of memory cells;

programming the first data to the first plurality of memory cells; and

in response to receiving the write command associated with a second address corresponding to the block of memory cells and associated with second data prior to successfully verifying programming of the first data to the first plurality of memory cells, a second plurality of memory cells in the block of memory cells corresponding to the second address are prepared for programming without returning the block of memory cells to the initialized state after programming the first data to the first plurality of memory cells.

2. The memory of claim 1, wherein the controller is further configured to cause the memory to:

In response to not receiving a command for access of the block of memory cells prior to successfully verifying programming of the first data to the first plurality of memory cells, returning the block of memory cells to the initialized state after programming the first data to the first plurality of memory cells.

3. The memory of claim 1, wherein the controller is further configured to cause the memory to:

in response to receiving a command for access of a different block of memory cells prior to successfully verifying programming of the first data to the first plurality of memory cells, the block of memory cells is returned to the initialized state after programming the first data to the first plurality of memory cells.

4. The memory of claim 1, wherein the controller being configured to cause the memory to return the block of memory cells to the initialized state comprises the controller being configured to deactivate block selection circuitry corresponding to the block of memory cells.

5. The memory of claim 1, wherein the controller being configured to cause the memory to return the memory cell block to the initialized state comprises the controller being configured to deactivate a voltage generating device corresponding to the memory cell block.

6. The memory of claim 1, wherein the controller being configured to cause the memory to return the block of memory cells to the initialized state comprises the controller being configured to discharge an access line and a select line corresponding to the block of memory cells to a reference potential.

7. The memory of claim 1, wherein the controller is further configured to cause the memory to:

programming the second data to the second plurality of memory cells; and

for each additional write command of the one or more additional write commands, each associated with a respective address corresponding to the block of memory cells and with respective data, and each received before successfully verifying programming of any previous data to the respective plurality of memory cells:

in response to receiving an additional write command, preparing respective pluralities of memory cells in the block of memory cells corresponding to their respective addresses for programming without returning the block of memory cells to the initialized state after programming the previous data to their respective pluralities of memory cells; and

programming the respective data of that additional write command to its respective plurality of memory cells; and

The block of memory cells is returned to the initialized state in response to not receiving an additional write command for access of the block of memory cells before successfully verifying the programming of the previous data to their respective plurality of memory cells.

8. A memory, comprising:

a memory cell array; and

a controller for access to the array of memory cells, wherein the controller is configured to cause the memory to:

in response to receiving a first command associated with a first address of the memory cell array and with first data and corresponding to a programming operation, initiating an initial programming sequence to program the first data to a first plurality of memory cells of a memory cell block of the memory cell array that corresponds to the first address, wherein the initial programming sequence includes a preamble phase, a programming phase, a verification phase, and a recovery phase;

determining whether the memory receives a second command associated with a second address corresponding to the block of memory cells and with second data prior to initiating the recovery phase of the initial programming sequence, wherein the second address corresponds to a second plurality of memory cells of the block of memory cells, and wherein the second command corresponds to the programming operation;

In response to receiving the second command prior to initiating the recovery phase of the initial programming sequence, a subsequent programming sequence is initiated to program the second data to a second plurality of memory cells of the block of memory cells corresponding to the second address without performing the recovery phase of the initial programming sequence.

9. The memory of claim 8, wherein the first command and the second command are the same command.

10. The memory of claim 8, wherein the controller is further configured to cause the memory to:

the recovery phase of the initial programming sequence is performed in response to not receiving the second command prior to initiating the recovery phase of the initial programming sequence.

11. The memory of claim 8, wherein the controller is further configured to cause the memory to:

the recovery phase of the initial programming sequence is performed in response to receiving a next command directed to a different array operation or to a different block of memory cells prior to initiating the recovery phase of the initial programming sequence.

12. The memory of claim 8, wherein the subsequent programming sequence comprises abbreviated preamble phases, wherein the preamble phases of the initial programming sequence comprise activating voltage generating devices corresponding to the block of memory cells, and wherein the abbreviated preamble phases of the subsequent programming sequence do not comprise activating those voltage generating devices corresponding to the block of memory cells.

13. The memory of claim 12, wherein the preamble phase of the initial programming sequence includes checking a temperature sensor, and wherein the abbreviated preamble phase of the subsequent programming sequence does not include checking the temperature sensor.

14. The memory of claim 12, wherein the preamble phase of the initial programming sequence includes examining the first address to determine the block of memory cells, and wherein the abbreviated preamble phase of the subsequent programming sequence does not include examining the first address to determine the block of memory cells.

15. The memory of claim 12, wherein the preamble phase of the initial programming sequence comprises determining whether a memory cell selected for programming has been designated for replacement with a redundant memory cell, and wherein the reduced preamble phase of the subsequent programming sequence does not comprise determining whether a memory cell selected for programming has been designated for replacement with a redundant memory cell.

16. The memory of claim 8, wherein the subsequent programming sequence comprises a programming phase, a verification phase, and a recovery phase, and wherein the programming phase, the verification phase, and the recovery phase of the subsequent programming sequence each comprise the same set of activity types as the programming phase, the verification phase, and the recovery phase, respectively, of the initial programming sequence.

17. A memory, comprising:

a memory cell array; and

a controller for access to the array of memory cells, wherein the controller is configured to cause the memory to:

in response to receiving a first command associated with a first address of the memory cell array and with first data, performing a preamble phase of a programming sequence to prepare a first plurality of memory cells in a memory cell block of the memory cell array corresponding to the first address for programming, wherein the first command corresponds to a programming operation;

performing a programming phase of the programming sequence to program the first data to the first plurality of memory cells;

performing a verification phase of the programming sequence to verify the programming of the first data to the first plurality of memory cells;

Determining whether the memory receives a second command associated with a second address corresponding to the block of memory cells and associated with second data, wherein the second address corresponds to a second plurality of memory cells of the block of memory cells, and wherein the second command corresponds to the programming operation;

in response to receiving the second command, performing a abbreviated preamble phase of a subsequent programming sequence to prepare the second plurality of memory cells of the block of memory cells for programming; and

the recovery phase of the initial programming sequence is performed in response to not receiving the second command.

18. The memory of claim 17, wherein the second command is the same command as the first command.

19. The memory of claim 17, wherein the controller is further configured to cause the memory to repeat the programming phase and verification phase of the programming sequence in response to determining that the first data was not successfully programmed to the first plurality of memory cells.

20. The memory of claim 17, wherein in response to receiving the second command, the controller is further configured to cause the memory to:

Performing a programming phase of the subsequent programming sequence to program the second data to the second plurality of memory cells;

performing a verify phase of the subsequent programming sequence to verify the programming of the second data to the second plurality of memory cells;

determining whether the memory receives a third command associated with a third address corresponding to the block of memory cells and associated with third data, wherein the third address corresponds to a third plurality of memory cells of the block of memory cells, and wherein the third command corresponds to the programming operation;

in response to receiving the third command, performing the reduced preamble phase of the subsequent programming sequence to prepare the third plurality of memory cells for programming; and

in response to not receiving the third command, the recovery phase of the subsequent programming sequence is performed.

21. The memory of claim 20, wherein the second command is the same command as the first command, and wherein the third command is a different command than the second command.

22. The memory of claim 17, wherein the reduced set of active types of the preamble phase of the subsequent programming sequence is an appropriate subset of the set of active types of the preamble phase of the programming sequence.