CN116759335A - Bonding device, forming method of bonding device and bonding method - Google Patents
Bonding device, forming method of bonding device and bonding method Download PDFInfo
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- CN116759335A CN116759335A CN202310693688.5A CN202310693688A CN116759335A CN 116759335 A CN116759335 A CN 116759335A CN 202310693688 A CN202310693688 A CN 202310693688A CN 116759335 A CN116759335 A CN 116759335A
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- 238000000034 method Methods 0.000 title claims description 72
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 239000000463 material Substances 0.000 claims description 60
- 238000004891 communication Methods 0.000 claims description 38
- 239000003989 dielectric material Substances 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 239000000084 colloidal system Substances 0.000 claims description 25
- 239000007788 liquid Substances 0.000 claims description 20
- 239000000126 substance Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000003825 pressing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000013007 heat curing Methods 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 171
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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Abstract
The bonding device is used for bonding a chip and a first wafer, the first wafer comprises a plurality of chip areas, each chip area is provided with a region to be bonded, and the bonding device comprises: the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area; the auxiliary layers are arranged on the surfaces of the substrate wafers, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surfaces of the substrate wafers, the grooves are used for accommodating the chips, the positions of the cell areas where the grooves are located relative to the grooves are consistent with the positions of the chip areas relative to the areas to be bonded, the alignment difficulty between a plurality of chips and the first wafer is reduced, alignment accuracy is improved, and structural performance obtained by bonding is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a bonding device, a method for forming the bonding device, and a bonding method.
Background
In the state where very large scale integrated circuits are developed increasingly close to physical limits, three-dimensional integrated circuits, which are advantageous in terms of both physical size and cost, are an effective way to extend moore's law and solve advanced packaging problems.
The logic circuit is cut into chips and attached to a monolithic wafer with the memory circuit by means of a patch to form a completed memory, a form of packaging that is common in the art. The packaging form has high alignment requirement on the logic circuit chip and the memory wafer, and the prior art can only achieve alignment accuracy of tens of micrometers and can not meet the packaging requirement.
In summary, the existing packaging technology needs to be further improved.
Disclosure of Invention
The invention solves the technical problem of providing a bonding device, a forming method of the bonding device and a bonding method so as to improve the performance of a formed chip.
In order to solve the above technical problems, the present invention provides a bonding apparatus for bonding a chip and a first wafer, where the first wafer includes a plurality of chip areas, and each chip area has a to-be-bonded area, and the bonding apparatus includes: the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area; the auxiliary layers are positioned on the surface of the substrate wafer, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating chips, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas.
Optionally, the auxiliary layer further has a plurality of communication openings located between adjacent grooves, the bottoms of the communication openings expose the surface of the substrate wafer, and each communication opening is communicated with the adjacent groove.
Optionally, the substrate wafer is further provided with a through hole at the bottom of each groove.
Optionally, the auxiliary layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, where a material of the first dielectric layer is different from a material of the second dielectric layer; the ratio of the thicknesses of the first dielectric layer and the second dielectric layer ranges from 1:10 to 1:20.
Optionally, the material of the auxiliary layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Correspondingly, the technical scheme of the invention also provides a forming method of the bonding device, which comprises the following steps: providing a plurality of chips to be bonded and a first wafer, wherein the first wafer comprises a plurality of chip areas, and each chip area is internally provided with a region to be bonded; providing a substrate wafer, wherein the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area; and forming an auxiliary layer on the surface of the substrate wafer, wherein grooves are formed in the auxiliary layer on each cell area, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating chips to be bonded, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas.
Optionally, the auxiliary layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, where a material of the first dielectric layer is different from a material of the second dielectric layer; the ratio of the thicknesses of the first dielectric layer and the second dielectric layer ranges from 1:10 to 1:20.
Optionally, the forming method of the auxiliary layer includes: forming a first dielectric material layer and a second dielectric material layer positioned on the first dielectric material layer on the surface of the substrate wafer; etching the second dielectric material layer until the first dielectric material layer is exposed, and forming the second dielectric layer; and continuing to etch the first dielectric material layer exposed by the second dielectric layer until the surface of the substrate wafer is exposed.
Optionally, the material of the auxiliary layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Optionally, the auxiliary layer further has a plurality of communication openings located between adjacent grooves, the bottoms of the communication openings expose the surface of the substrate wafer, and each communication opening is communicated with the adjacent groove.
Optionally, the substrate wafer is further provided with a through hole at the bottom of each groove.
Correspondingly, the technical scheme of the invention also provides a bonding method, which comprises the following steps: providing a plurality of chips; providing a first wafer, wherein the first wafer comprises a plurality of chip areas, and each chip area is internally provided with an area to be bonded; providing a bonding device, wherein the bonding device comprises a substrate wafer, the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area; the auxiliary layers are positioned on the surface of the substrate wafer, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating the chips, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas; fixing a plurality of chips to the bottoms of the grooves respectively; the first wafer is oriented to the surface of the auxiliary layer, a plurality of chips are bonded with the first wafer, and one chip is correspondingly bonded to one area to be bonded; and after the bonding process, separating a plurality of chips from the bottom of the groove.
Optionally, the method for fixing the chips to the bottoms of the grooves respectively includes: filling colloid materials at the bottoms of the grooves; and respectively placing a plurality of chips on the surface of the colloid material in each groove.
Optionally, the method for fixing the chips to the bottoms of the grooves respectively further includes: after the chips are placed on the surface of the colloid material, pressing each chip to enable the surfaces of the chips to be located on the same horizontal plane.
Optionally, the method for fixing the chips to the bottoms of the grooves respectively further includes: after the pressing process, the colloid material is also subjected to a heat curing treatment.
Optionally, the auxiliary layer is further provided with a plurality of communication openings between adjacent grooves, the bottoms of the communication openings expose the surface of the substrate wafer, and each communication opening is communicated with the adjacent groove; the method for fixing the chips to the bottoms of the grooves respectively further comprises the following steps: the gel material is also filled into the communication openings.
Optionally, the method for disengaging the chips from the bottom of the groove includes: and immersing the chip and the substrate wafer into chemical liquid, wherein the chemical liquid enters the bottom of the groove from the communication opening, and the chemical liquid reacts with the colloid material so as to separate the chip from the colloid material.
Optionally, the substrate wafer is further provided with a through hole at the bottom of each groove.
Optionally, the method for disengaging the chips from the bottom of the groove includes: and soaking the chip and the substrate wafer into chemical liquid, wherein the chemical liquid enters the bottom of the groove from the through hole, and the chemical liquid reacts with the colloid material to separate the chip from the colloid material.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the bonding device provided by the technical scheme of the invention, the bonding device is used for bonding chips and wafers, the wafers comprise a plurality of chip areas, each chip area is internally provided with an auxiliary layer positioned on the surface of the substrate wafer, each auxiliary layer on each cell area is internally provided with a groove, the bottoms of the grooves expose the surface of the substrate wafer, the grooves are used for accommodating the chips, the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the chips relative to the chip areas, which are to be bonded, because the grooves limit the bonding positions of the chips relative to the first wafer, when the bonding device is adopted to bond the chips and the first wafer, only the substrate wafer and the first wafer need to be aligned, so that the alignment difficulty between the chips and the first wafer is reduced, the alignment precision is facilitated, and the structural performance obtained by bonding is improved.
In the method for forming the bonding device provided by the technical scheme of the invention, the bonding device is used for bonding chips and wafers, the wafers comprise a plurality of chip areas, each chip area is internally provided with a region to be bonded, an auxiliary layer is formed on the surface of the substrate wafer, grooves are formed in the auxiliary layer on each cell area, the bottoms of the grooves expose the surface of the substrate wafer, the grooves are used for accommodating the chips, the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the regions to be bonded relative to the chip areas, and because the grooves limit the bonding positions of the chips relative to the first wafer, when the bonding device is adopted for bonding the chips and the first wafer, only the substrate wafer and the first wafer need to be aligned, so that the alignment difficulty between the chips and the first wafer is reduced, the alignment accuracy is facilitated, and the structural performance obtained by bonding is improved.
In the bonding method provided by the technical scheme of the invention, the bonding device is used for bonding chips and wafers, the wafers comprise a plurality of chip areas, each chip area is internally provided with an auxiliary layer positioned on the surface of the substrate wafer, each auxiliary layer on each cell area is internally provided with a groove, the bottoms of the grooves expose the surface of the substrate wafer, the grooves are used for accommodating the chips, the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the chips relative to the chip areas, which are to be bonded, because the grooves limit the bonding positions of the chips relative to the first wafer, when the bonding device is adopted to bond the chips and the first wafer, only the substrate wafer and the first wafer need to be aligned, so that the alignment difficulty between the chips and the first wafer is reduced, the alignment precision is facilitated, and the structural performance obtained by bonding is improved.
Further, after the chips are placed on the surface of the colloid material, the chips are pressed, so that the surfaces of the second chips are positioned on the same horizontal plane, the flatness of the bottom surface of each groove of the bonding device in the bonding process is reduced, the requirement on the thickness uniformity of each chip is met, and the process window is improved.
Drawings
FIGS. 1-4 are schematic structural views of steps of a method of bonding a chip to a wafer;
FIG. 5 is a flow chart of a bonding method according to an embodiment of the present invention;
FIGS. 6 to 19 are schematic structural views illustrating steps of a bonding method according to an embodiment of the present invention;
fig. 20 to 22 are schematic structural views of a bonding device according to another embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As background art, the performance needs to be improved by adopting the structure formed by the conventional chip and wafer package. Analysis will now be described in connection with a method of bonding chips and wafers.
Fig. 1 to 4 are schematic structural views of steps of a method for bonding chips and wafers.
Referring to fig. 1, a logic wafer 10 is provided, and the logic wafer 10 includes a plurality of logic chips 101.
Referring to fig. 2, a memory wafer 20 is provided, the memory wafer 20 includes a plurality of memory chips 201.
Referring to fig. 3 and 4, fig. 3 is a schematic top view, and fig. 4 is a schematic partially enlarged cross-sectional view along XX1 in fig. 3, in which the logic chips 101 on the logic wafer 10 are selected and attached to the memory chips 201 of the memory wafer 20.
In the above method of bonding chips and wafers, it is necessary to attach the logic chips 101 to the memory chips 201 of the memory wafer 20 one by one, which is slow and has low alignment accuracy. Since the logic chip 101 can only be attached to the fixed position of the memory chip 201, that is, the first electrical interconnection layer a of the logic chip 101 and the second electrical interconnection layer B of the memory chip 201 need to be bonded, normal circuit connection of the two chips can be achieved, and even when an alignment abnormality occurs (as shown by a dotted line in the figure), the situation that the circuits of the two chips cannot be connected occurs.
In order to solve the above problems, the bonding device, the forming method of the bonding device and the bonding method provided by the invention are characterized in that the bonding device is used for bonding chips and wafers, each wafer comprises a plurality of chip areas, each chip area is internally provided with an auxiliary layer positioned on the surface of the substrate wafer, each auxiliary layer on each cell area is internally provided with a groove, the bottom of each groove exposes the surface of the substrate wafer, the grooves are used for accommodating the chips, the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the chips relative to the chip areas where the grooves are to be bonded, and because the bonding positions of the chips relative to the first wafer are limited by the grooves, when the bonding device is adopted to bond a plurality of chips and the first wafer, the chips and the first wafer are only required to be aligned, so that the alignment precision between a plurality of chips and the first wafer is reduced, and the structure performance of bonding acquisition is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 is a flowchart of a bonding method according to an embodiment of the invention.
Referring to fig. 5, the bonding method includes the following steps:
step 601, providing a plurality of chips;
step 602, providing a first wafer, wherein the first wafer comprises a plurality of chip areas, and each chip area is provided with a to-be-bonded area;
step 603, providing a bonding device, wherein the bonding device comprises a substrate wafer, the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area; the auxiliary layers are positioned on the surface of the substrate wafer, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating the chips, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas;
step 604, fixing a plurality of chips to the bottoms of the grooves respectively;
step 605, the first wafer is directed to the surface of the auxiliary layer, so that a plurality of chips are bonded with the first wafer, and one chip is correspondingly bonded to one area to be bonded;
step 606, after the bonding process, removing the chips from the bottom of the groove.
The following detailed description will be given with reference to the accompanying drawings.
Fig. 6 to 19 are schematic structural diagrams of steps of a bonding method according to an embodiment of the invention.
Referring to fig. 6 and 7, and with continued reference to fig. 5, a plurality of chips 301 are provided.
It should be noted that fig. 6 shows a schematic top view of several chips 301 before dicing and separating on the same wafer, and fig. 7 is a schematic enlarged cross-sectional view of a single chip 301 along the NN1 direction in fig. 6.
In this embodiment, the chip 301 is obtained by dicing the second wafer 30, and the chip 301 has a logic circuit therein.
Referring to fig. 8 and 9, with continued reference to fig. 5, fig. 8 is a schematic top view, and fig. 9 is a schematic partially enlarged cross-sectional view along the MM1 direction in fig. 8, a first wafer 40 is provided, where the first wafer 40 includes a plurality of chip regions 401, and each chip region 401 has a region C to be bonded therein.
The region to be bonded C is used to define a position for bonding the chip 301 (as shown in fig. 6) on the first wafer 40.
In this embodiment, each of the chip regions 401 of the first wafer 40 has a memory circuit therein, and the first wafer 40 and the plurality of chips 301 are bonded to form a memory.
It should be noted that the technical solution of the present invention is applicable to bonding a chip and a first wafer, wherein the size of the chip is smaller than that of the chip area of the first wafer, and is not limited to forming a memory.
Referring to fig. 10 to 13, with continued reference to fig. 5, fig. 10 is a schematic top view, fig. 11 is a partially enlarged view of fig. 10, fig. 12 is a schematic cross-sectional view along the direction EE1 in fig. 11, and fig. 13 is a schematic cross-sectional view along the direction FF1 in fig. 11, a bonding device is provided, the bonding device includes: a substrate wafer 500, wherein the substrate wafer 500 includes a plurality of cell areas I, and each cell area I overlaps each chip area 401 (shown in fig. 8) when the first wafer 40 (shown in fig. 8) is attached to the surface of the substrate wafer 500; the auxiliary layer 501 located on the surface of the substrate wafer 500 has a groove 502 in the auxiliary layer 501 on each cell area I, the bottom of the groove 502 exposes the surface of the substrate wafer 500, the groove 502 is used for accommodating the chip 301 (as shown in fig. 6), and the position of the groove 502 relative to the cell area I where it is located is consistent with the position of the to-be-bonded area C (as shown in fig. 8) relative to the chip area 401.
Specifically, the position of the bottom of the groove 502 corresponding to the cell area I where the bottom is located is consistent with the position of the to-be-bonded area C corresponding to the chip area 401.
In this embodiment, the auxiliary layer 501 further has a plurality of communication openings 503 between adjacent grooves 502, the bottom of each communication opening 503 exposes the surface of the substrate wafer 500, and each communication opening 503 is communicated with the adjacent groove 502. The communication opening 503 is used to allow chemical liquid to flow into the groove 502 through the communication opening 503 when the chips 301 are separated from the bottom of the groove 502, so as to facilitate removal of the colloid material between the groove 502 and the chips 301.
In another embodiment, the substrate wafer is further provided with a through hole at the bottom of each groove. The through holes are used for allowing chemical liquid to flow into the grooves through the through holes when a plurality of chips are separated from the bottoms of the grooves, so that the colloid materials between the grooves and the chips can be removed easily.
In this embodiment, the auxiliary layer 501 includes a first dielectric layer 501a and a second dielectric layer 501b located on the first dielectric layer 501a, where a material of the first dielectric layer 501 is different from a material of the second dielectric layer 502; the ratio of the thicknesses of the first dielectric layer 501a and the second dielectric layer 501b ranges from 1:10 to 1:20.
In this embodiment, the material of the auxiliary layer 501 includes a dielectric material, where the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Specifically, the material of the first dielectric layer 501a is silicon nitride, and the material of the second dielectric layer 501b is silicon oxide.
Referring to fig. 14 to 17, with continued reference to fig. 5, fig. 14 is a schematic top view, fig. 15 is a partially enlarged view of fig. 14, fig. 16 is a schematic cross-sectional view along EE1 in fig. 15, and fig. 17 is a schematic cross-sectional view along FF1 in fig. 15, in which a plurality of chips 301 are respectively fixed to the bottoms of the grooves 502.
In this embodiment, the method for fixing the chips 301 to the bottoms of the grooves 502 includes: filling a colloid material 504 into the bottoms of the grooves 502; a plurality of chips 301 are respectively placed on the surface of the colloid material 504 in each groove 502.
In this embodiment, the gel material 504 is also filled into the communication opening 503.
In this embodiment, the method for fixing the plurality of chips 301 to the bottoms of the grooves 502 respectively further includes: after the chips 301 are placed on the surface of the gel material 504, each of the chips 301 is pressed so that the surfaces of the chips 301 are positioned on the same horizontal plane. The surfaces of the chips 301 are located on the same horizontal plane, so that the flatness of the bottom surface of each groove 502 of the bonding device in the bonding process is reduced, the requirement on the thickness uniformity of each chip 301 is reduced, and the process window is improved.
In this embodiment, the method for fixing the plurality of chips 301 to the bottoms of the grooves 502 respectively further includes: after the pressing process, the gel material 504 is also subjected to a heat curing process.
Please refer to fig. 18 on the basis of fig. 16, and with continued reference to fig. 5, the first wafer 40 is oriented to the surface of the auxiliary layer 501, so that a plurality of chips 301 are bonded to the first wafer 40, and one chip 301 is correspondingly bonded to one to-be-bonded area C.
Please refer to fig. 19 on the basis of fig. 18, and with continued reference to fig. 5, after the bonding process, the chips 301 are detached from the bottoms of the grooves 502.
So far, since the grooves 502 limit the bonding position of each chip 301 relative to the first wafer 40, when the bonding device is adopted to bond a plurality of chips 301 and the first wafer 40, only the substrate wafer 500 and the first wafer 40 need to be aligned, so that the alignment difficulty between a plurality of chips 301 and the first wafer 40 is reduced, the alignment precision is improved, and the structural performance obtained by bonding is improved.
In this embodiment, the method for disengaging the chips 301 from the bottom of the recess 502 includes: the chip 301 and the substrate wafer 500 are immersed in a chemical liquid, which enters the bottom of the recess 502 from the communication opening 503 (as shown in fig. 11), and reacts with the colloidal material 504 to detach the chip 301 from the colloidal material 504.
In another embodiment, the method for disengaging the plurality of chips from the bottom of the recess comprises: and soaking the chip and the substrate wafer into chemical liquid, wherein the chemical liquid enters the bottom of the groove from the through hole, and the chemical liquid reacts with the colloid material to separate the chip from the colloid material.
Accordingly, the embodiment of the present invention further provides a bonding apparatus for the above bonding method, please continue to refer to fig. 10 to 13, wherein the bonding apparatus is used for bonding a chip 301 (as shown in fig. 6 and 7) and a first wafer 40 (as shown in fig. 8 and 9), the first wafer 40 includes a plurality of chip regions 401, and each chip region 401 has a region C to be bonded therein; the bonding device includes: a substrate wafer 500, wherein the substrate wafer 500 includes a plurality of cell areas I, and each cell area I overlaps each chip area 401 (as shown in fig. 8) when the first wafer 40 is attached to the surface of the substrate wafer 500; the auxiliary layer 501 located on the surface of the substrate wafer 500 has a groove 502 in the auxiliary layer 501 on each cell area I, the bottom of the groove 502 exposes the surface of the substrate wafer 500, the groove 502 is used for accommodating the chip 301 (as shown in fig. 6), and the position of the groove 502 relative to the cell area I where it is located is consistent with the position of the to-be-bonded area C (as shown in fig. 8) relative to the chip area 401.
So far, since the grooves 502 limit the bonding position of each chip 301 relative to the first wafer 40, when the bonding device is adopted to bond a plurality of chips 301 and the first wafer 40, only the substrate wafer 500 and the first wafer 40 need to be aligned, so that the alignment difficulty between a plurality of chips 301 and the first wafer 40 is reduced, the alignment precision is improved, and the structural performance obtained by bonding is improved.
Specifically, the position of the bottom of the groove 502 corresponding to the cell area I where the bottom is located is consistent with the position of the to-be-bonded area C corresponding to the chip area 401.
In this embodiment, the auxiliary layer 501 further has a plurality of communication openings 503 between adjacent grooves 502, the bottom of each communication opening 503 exposes the surface of the substrate wafer 500, and each communication opening 503 is communicated with the adjacent groove 502. The communication opening 503 is used to allow chemical liquid to flow into the groove 502 through the communication opening 503 when the chips 301 are separated from the bottom of the groove 502, so as to facilitate removal of the colloid material between the groove 502 and the chips 301.
In another embodiment, the substrate wafer is further provided with a through hole at the bottom of each groove. The through holes are used for allowing chemical liquid to flow into the grooves through the through holes when a plurality of chips are separated from the bottoms of the grooves, so that the colloid materials between the grooves and the chips can be removed easily.
In this embodiment, the auxiliary layer 501 includes a first dielectric layer 501a and a second dielectric layer 501b located on the first dielectric layer 501a, where a material of the first dielectric layer 501a is different from a material of the second dielectric layer 501b; the ratio of the thicknesses of the first dielectric layer 501a and the second dielectric layer 501b ranges from 1:10 to 1:20.
In this embodiment, the material of the auxiliary layer 501 includes a dielectric material, where the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Specifically, the material of the first dielectric layer 501a is silicon nitride, and the material of the second dielectric layer 501b is silicon oxide.
Correspondingly, an embodiment of the present invention further provides a method for forming the bonding device, please continue to refer to fig. 10 to 13, where the method for forming the bonding device includes: providing a plurality of chips 301 to be bonded (as shown in fig. 6 and 7) and a first wafer 40 (as shown in fig. 8 and 9), wherein the first wafer 40 comprises a plurality of chip areas 401, and each chip area 401 is provided with a region C to be bonded; providing a substrate wafer 500, wherein the substrate wafer 500 comprises a plurality of cell areas I, and each cell area I is overlapped with each chip area 401 (as shown in fig. 8) when the first wafer 40 is adhered to the surface of the substrate wafer 500; an auxiliary layer 501 is formed on the surface of the substrate wafer 500, and a groove 502 is formed in the auxiliary layer 501 on each cell area I, the bottom of the groove 502 exposes the surface of the substrate wafer 500, the groove 502 is used for accommodating the chip 301 (as shown in fig. 6), and the position of the groove 502 relative to the cell area I where the groove 502 is located is consistent with the position of the to-be-bonded area C (as shown in fig. 8) relative to the chip area 401.
So far, since the grooves 502 limit the bonding position of each chip 301 relative to the first wafer 40, when the bonding device is adopted to bond a plurality of chips 301 and the first wafer 40, only the substrate wafer 500 and the first wafer 40 need to be aligned, so that the alignment difficulty between a plurality of chips 301 and the first wafer 40 is reduced, the alignment precision is improved, and the structural performance obtained by bonding is improved.
Specifically, the position of the bottom of the groove 502 corresponding to the cell area I where the bottom is located is consistent with the position of the to-be-bonded area C corresponding to the chip area 401.
In this embodiment, the auxiliary layer 501 includes a first dielectric layer 501a and a second dielectric layer 501b located on the first dielectric layer 501a, where a material of the first dielectric layer 501a is different from a material of the second dielectric layer 501b; the ratio of the thicknesses of the first dielectric layer 501a and the second dielectric layer 501b ranges from 1:10 to 1:20.
In this embodiment, the method for forming the auxiliary layer 501 includes: forming a first dielectric material layer (not shown) and a second dielectric material layer (not shown) on the first dielectric material layer on the surface of the substrate wafer 500; etching the second dielectric material layer until the first dielectric material layer is exposed, and forming the second dielectric layer 501b; and continuing to etch the first dielectric material layer exposed by the second dielectric layer 501b until the surface of the substrate wafer 500 is exposed.
In this embodiment, the material of the auxiliary layer 501 includes a dielectric material, where the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Specifically, the material of the first dielectric layer 501a is silicon nitride, and the material of the second dielectric layer 501b is silicon oxide.
In this embodiment, the auxiliary layer 501 further has a plurality of communication openings 503 between adjacent grooves 502, the bottom of each communication opening 503 exposes the surface of the substrate wafer 500, and each communication opening 503 is communicated with the adjacent groove 502.
In another embodiment, the substrate wafer is further provided with a through hole at the bottom of each groove.
It should be noted that the bonding device can be reused for a plurality of times, and the bonding device can be cleaned before the next use so as to reduce contamination of wafers and chips to be bonded.
Fig. 20 to 22 are schematic structural views of a bonding device according to another embodiment of the present invention.
The main difference between this embodiment and the previous embodiment is that: the above embodiment uses the communication openings to remove the gel material between the grooves and the chips, and in this embodiment, the gel material between the grooves and the chips is removed through the through holes at the bottom of each groove in the substrate wafer.
With continued reference to fig. 6 to 9, the bonding apparatus is used for bonding a chip 301 and a first wafer 40, where the first wafer 40 includes a plurality of chip regions 401, and each chip region 401 has a region C to be bonded therein.
In this embodiment, referring to fig. 20 to 22, fig. 20 is a schematic top view, fig. 21 is a partially enlarged view of fig. 20, and fig. 22 is a schematic cross-sectional view along HH1 in fig. 21, including: a substrate wafer 700, wherein the substrate wafer 700 includes a plurality of cell areas II, and each cell area II overlaps each chip area 401 (as shown in fig. 8) when the first wafer 40 is attached to the surface of the substrate wafer 700; the auxiliary layer 701 is located on the surface of the substrate wafer 700, a groove 702 is formed in the auxiliary layer 701 on each cell area II, the bottom of the groove 702 exposes the surface of the substrate wafer 700, the groove 702 is used for accommodating the chip 301 (as shown in fig. 6), and the position of the groove 702 relative to the cell area II where the groove 702 is located is consistent with the position of the to-be-bonded area C (as shown in fig. 8) relative to the chip area 401.
In this embodiment, the substrate wafer 700 further has a through hole 703 at the bottom of each of the grooves 702.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A bonding apparatus for bonding a chip and a first wafer, the first wafer comprising a plurality of chip regions, and each chip region having a region to be bonded therein, the bonding apparatus comprising:
the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area;
the auxiliary layers are positioned on the surface of the substrate wafer, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating chips, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas.
2. The bonding apparatus of claim 1, wherein the auxiliary layer further has a plurality of communication openings between adjacent grooves, wherein bottoms of the communication openings expose the surface of the substrate wafer, and wherein each communication opening communicates with an adjacent groove.
3. The bonding apparatus of claim 1, wherein the substrate wafer further has a through hole therein at a bottom of each of the grooves.
4. The bonding apparatus of claim 1, wherein the auxiliary layer comprises a first dielectric layer and a second dielectric layer on the first dielectric layer, the first dielectric layer being of a different material than the second dielectric layer; the ratio of the thicknesses of the first dielectric layer and the second dielectric layer ranges from 1:10 to 1:20.
5. The bonding apparatus of claim 4, wherein the material of the auxiliary layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
6. A method of forming a bonding apparatus, comprising:
providing a plurality of chips to be bonded and a first wafer, wherein the first wafer comprises a plurality of chip areas, and each chip area is internally provided with a region to be bonded;
providing a substrate wafer, wherein the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area;
and forming an auxiliary layer on the surface of the substrate wafer, wherein grooves are formed in the auxiliary layer on each cell area, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating chips to be bonded, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas.
7. The method of forming a bonding device according to claim 6, wherein the auxiliary layer comprises a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein a material of the first dielectric layer is different from a material of the second dielectric layer; the ratio of the thicknesses of the first dielectric layer and the second dielectric layer ranges from 1:10 to 1:20.
8. The method of forming a bonding device according to claim 7, wherein the method of forming the auxiliary layer comprises: forming a first dielectric material layer and a second dielectric material layer positioned on the first dielectric material layer on the surface of the substrate wafer; etching the second dielectric material layer until the first dielectric material layer is exposed, and forming the second dielectric layer; and continuing to etch the first dielectric material layer exposed by the second dielectric layer until the surface of the substrate wafer is exposed.
9. The method of claim 7, wherein the material of the auxiliary layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
10. The method of claim 7, wherein the auxiliary layer further has a plurality of communication openings between adjacent grooves, wherein bottoms of the communication openings expose the surface of the substrate wafer, and each communication opening communicates with an adjacent groove.
11. The method of claim 7, wherein the substrate wafer further has a through hole at a bottom of each of the grooves.
12. A bonding method, comprising:
providing a plurality of chips;
providing a first wafer, wherein the first wafer comprises a plurality of chip areas, and each chip area is internally provided with an area to be bonded;
providing a bonding device, the bonding device comprising,
the substrate wafer comprises a plurality of cell areas, and when the first wafer is attached to the surface of the substrate wafer, each cell area is overlapped with each chip area;
the auxiliary layers are positioned on the surface of the substrate wafer, grooves are formed in the auxiliary layers on the cell areas, the bottoms of the grooves are exposed out of the surface of the substrate wafer, the grooves are used for accommodating the chips, and the positions of the grooves relative to the cell areas where the grooves are positioned are consistent with the positions of the areas to be bonded relative to the chip areas;
fixing a plurality of chips to the bottoms of the grooves respectively;
the first wafer is oriented to the surface of the auxiliary layer, a plurality of chips are bonded with the first wafer, and one chip is correspondingly bonded to one area to be bonded;
and after the bonding process, separating a plurality of chips from the bottom of the groove.
13. The bonding method according to claim 12, wherein the method of fixing the plurality of chips to the bottoms of the grooves, respectively, comprises: filling colloid materials at the bottoms of the grooves; and respectively placing a plurality of chips on the surface of the colloid material in each groove.
14. The bonding method according to claim 13, wherein the method of fixing the plurality of chips to the bottoms of the grooves, respectively, further comprises: after the chips are placed on the surface of the colloid material, pressing each chip to enable the surfaces of the chips to be located on the same horizontal plane.
15. The bonding method of claim 14, wherein the method of fixing the plurality of chips to the bottoms of the grooves, respectively, further comprises: after the pressing process, the colloid material is also subjected to a heat curing treatment.
16. The bonding method according to claim 13, wherein the auxiliary layer further has a plurality of communication openings between adjacent grooves, the bottoms of the communication openings expose the surface of the substrate wafer, and each communication opening communicates with an adjacent groove; the method for fixing the chips to the bottoms of the grooves respectively further comprises the following steps: the gel material is also filled into the communication openings.
17. The bonding method of claim 16, wherein the method of disengaging the plurality of chips from the bottom of the recess comprises: and immersing the chip and the substrate wafer into chemical liquid, wherein the chemical liquid enters the bottom of the groove from the communication opening, and the chemical liquid reacts with the colloid material so as to separate the chip from the colloid material.
18. The bonding method of claim 13, wherein the substrate wafer further has a through hole therein at the bottom of each of the grooves.
19. The bonding method of claim 18, wherein the method of disengaging the plurality of chips from the bottom of the recess comprises: and soaking the chip and the substrate wafer into chemical liquid, wherein the chemical liquid enters the bottom of the groove from the through hole, and the chemical liquid reacts with the colloid material to separate the chip from the colloid material.
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| CN202310693688.5A CN116759335A (en) | 2023-06-12 | 2023-06-12 | Bonding device, forming method of bonding device and bonding method |
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| CN202310693688.5A CN116759335A (en) | 2023-06-12 | 2023-06-12 | Bonding device, forming method of bonding device and bonding method |
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