CN116758855B - Input signal phase relation self-adapting circuit in micro display panel - Google Patents
Input signal phase relation self-adapting circuit in micro display panel Download PDFInfo
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Abstract
The invention discloses an input signal phase relation self-adapting circuit in a micro display panel, which comprises: a row period valid data strobe signal HDE adaptive unit and a field period valid data strobe signal VDE adaptive unit; the self-adaptive unit of the effective data strobe signal HDE of the line period obtains the effective data strobe signal HDE of the self-adaptive line period after correction by timing and calculating the original line synchronous signal HS; the field period effective data strobe signal VDE self-adaptive unit obtains a modified self-adaptive field period effective data strobe signal VDE by timing and calculating an original field synchronous signal VS; and finally, the centering display of the input video picture on the micro display panel is realized.
Description
Technical Field
The invention relates to the technical field of image display, in particular to an input signal phase relation self-adaptive circuit in a micro display panel.
Background
Micro-display technology based on Micro-LEDs or Micro-OLEDs refers to display technology in which self-luminous Micro-scale LEDs or OLEDs are used as luminous pixel units, and the luminous pixel units are assembled on a driving panel to form a high-density LED array. The micro display chip has the advantages of small size, high integration level, self-luminescence and the like, and has the advantages of display brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like. Based on the above advantages, the micro display chip-based display device can be manufactured as a miniature and portable product, which allows the micro display chip-based display device to be applied to an AV or VR display device.
When a micro display panel is used to display a video picture, a situation that the resolution of an input video signal is not matched with that of the micro display panel is often encountered, for example, when the input video signal has 640 x 480 resolution, that is, 640 pixels are arranged in each row of the display picture, and 480 rows are taken, if the actual physical pixels of the micro display panel are 800 x 600, the display picture of the video signal cannot be centrally displayed, but only is displayed in the corner alignment of the micro display panel.
Therefore, in the prior art, a method and a circuit for adaptively adjusting a micro display chip according to an input video signal are needed, so that video data can be centrally displayed in the micro display panel.
Disclosure of Invention
The technical purpose to be achieved by the present invention is to provide an input signal phase relation adaptive circuit in a micro display panel, the input signal phase relation adaptive circuit comprising: a row period valid data strobe signal HDE adaptive unit and a field period valid data strobe signal VDE adaptive unit;
wherein the row period valid data strobe signal HDE adaptation unit comprises:
the HS signal timing unit is used for timing the original line synchronizing signal HS and resetting a timing result according to the input triggering edge of the original line synchronizing signal HS;
a first time length detection unit for detecting the period length T of the original line synchronous signal HS according to the timing result of the HS signal timing unit 0 ；
A second time length detection unit for detecting a first time length T from the HS trigger edge of the original line synchronous signal to the HDE trigger edge of the effective data strobe signal according to the timing result of the HS signal timing unit and the HDE trigger edge of the effective data strobe signal of the original line period 1 ；
A column black insertion calculation unit, which calculates a column black insertion correction duration deltat of a row period effective data strobe signal HDE corresponding to a single-side increase black insertion column in an original video picture according to the number of pixels in each row in physical pixels of the micro display panel;
an HDE start point operation unit, where the HDE start point operation unit corrects the duration Δt and the first duration T according to the column black insertion 1 Calculating the starting time point T of the modified line period effective data strobe signal HDE m ；
An HDE end point operation unit, the HDE junctionThe beam point operation unit is used for correcting the starting time point T of the effective data strobe signal HDE according to the line period m And calculating the end time point T of the modified row period effective data strobe signal HDE by the micro display panel physical resolution n ；
An HDE validity checking unit, which outputs the timing value X outputted by the HS signal timing unit and the start time point T of the corrected row period valid data strobe signal HDE m And an end time point T of the modified line period valid data strobe signal HDE n Checking, namely outputting an adaptive line period effective data strobe signal HDE after checking is passed;
the field period valid data strobe signal VDE adaptation unit comprises:
the VS signal timing unit is used for timing the original field synchronizing signal VS and resetting a timing result according to the trigger edge of the input original field synchronizing signal VS;
a third duration detection unit for detecting the period duration t of the original field synchronizing signal VS according to the timing result of the VS signal timing unit 0 ；
A fourth time length detection unit for detecting a second time length T from the trigger edge of the original field synchronizing signal VS to the trigger edge of the original field period effective data strobe signal VDE according to the timing result of the VS signal timing unit and the trigger edge of the original field period effective data strobe signal VDE 2 ；
A row black insertion calculation unit, which calculates a row black insertion correction duration deltat of a field period effective data strobe signal VDE corresponding to a single-side increase black insertion row in an original video picture according to the number of rows in a physical pixel of a micro display panel;
a VDE start point operation unit, wherein the VDE start point operation unit is used for correcting the duration delta T of the line black insertion and the second duration T 2 Calculating the start time point t of the corrected field period effective data strobe signal VDE m ；
VDE end point operation unit, said VDE end point operationThe unit valid data strobe signal VDE start time t according to the corrected field period m And calculating an end time point t of the corrected field period effective data strobe signal VDE by the micro display panel physical resolution n ；
A VDE validity checking unit for outputting a timing value x and a start time t of the corrected field period valid data strobe signal VDE to the VS signal timing unit m And an end time point t of the modified field period valid data strobe signal VDE n And checking, and outputting the effective data strobe signal VDE of the adaptive field period after the checking is passed.
In one embodiment, the trigger edge of the original line synchronization signal HS is a level jump edge occurring when the valid state of the original line synchronization signal HS arrives; when the original line synchronizing signal HS is effective at high level, the triggering edge of the original line synchronizing signal HS is a rising edge, and when the original line synchronizing signal HS is effective at low level, the triggering edge of the original line synchronizing signal HS is a falling edge.
In one embodiment, the triggering edge of the original field synchronization signal VS is a level jump edge occurring when the active state of the original field synchronization signal VS arrives, when the original field synchronization signal VS is active at a high level, the triggering edge of the original field synchronization signal VS is a rising edge, and when the original field synchronization signal VS is active at a low level, the triggering edge of the original field synchronization signal VS is a falling edge.
In one embodiment, the HS signal timing unit performs timing according to a pixel clock, and the timing result is a sum of durations of a plurality of pixel clock periods.
In one embodiment, the VS signal timing unit performs timing according to the pixel clock and the trigger edge of the original line synchronization signal HS, and the timing result is a plurality of period durations T 0 Is a sum of the durations of (a).
In one embodiment, the first time period T 1 The sum of the original line synchronizing signal HS time length and the effective data strobe signal HDE back porch time length of the original line period is obtained.
In one embodiment, the secondDuration T 2 I.e. the sum of the original field sync signal VS duration plus the back porch duration of the original field period valid data strobe signal VDE.
In one embodiment, the timing value X output by the HS signal timing unit and the start time point T of the modified line period effective data strobe signal HDE m And an end time point T of the modified line period valid data strobe signal HDE n The verification means that: when T is m ﹤X﹤T n When the time passes, the verification is passed, and the starting time point T is taken as m And end time point T n An adaptive row period active data strobe signal HDE is generated.
In one embodiment, the timing value x output by the timing unit of the VS signal and the start time point t of the modified field period valid data strobe signal VDE m And an end time point t of the modified field period valid data strobe signal VDE n The verification means that: when t m ﹤x﹤t n When the time passes, the verification is passed, and the starting time point t is taken as m And end time point t n An adaptive field period valid data strobe signal VDE is generated.
One or more embodiments of the present invention may have the following advantages over the prior art:
the invention can realize the centered display of the input video on the micro display panel through the self-adaptive phase relation circuit, and the process is automatically realized through the circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of a phase relationship adaptive circuit for input signals in a micro display panel according to the present invention;
FIG. 2 is a schematic diagram of HS signals and HDE signals according to the present invention;
FIG. 3 is a schematic diagram of VS signals and VDE signals according to the present invention;
FIG. 4 is a schematic diagram of the circuit structure of the HS signal timing unit of the present invention;
FIG. 5 is a schematic diagram of a circuit structure of a first timing detection unit according to the present invention;
FIG. 6 is a schematic diagram of a circuit configuration of a second duration detection unit according to the present invention;
FIG. 7 is a schematic diagram of a column black insertion calculation unit according to the present invention;
FIG. 8 is a schematic diagram of a circuit configuration of a VS signal timing unit according to the present invention;
fig. 9 is a schematic diagram of the structure of the row black insertion calculation unit of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Examples
The input signal phase relation adaptive circuit in the micro display panel of the present invention shown in fig. 1 comprises a row period effective data strobe signal HDE adaptive unit and a field period effective data strobe signal VDE adaptive unit.
In this embodiment, the row period valid data strobe signal HDE adaptive unit includes:
the HS signal timing unit is used for timing according to an original line synchronizing signal HS trigger edge input into the HS signal timing unit; the trigger edge of the original line synchronization signal HS is a level jump edge occurring when the valid state of the original line synchronization signal HS arrives, for example, when the original line synchronization signal HS is valid at a high level, the trigger edge of the original line synchronization signal HS is a rising edge, and when the original line synchronization signal HS is valid at a low level, the trigger edge of the original line synchronization signal HS is a falling edge.
A first time length detection unit for detecting the period length T of the original line synchronous signal HS according to the timing result of the HS signal timing unit 0 I.e. the high level duration and the low level duration in the original line synchronization signal HS.
A second time length detection unit for detecting a first time length T from the HS trigger edge of the original line synchronous signal to the HDE trigger edge of the effective data strobe signal according to the timing result of the HS signal timing unit and the HDE trigger edge of the effective data strobe signal of the original line period 1 The first time length T 1 The sum of the original line synchronizing signal HS time length and the effective data strobe signal HDE back porch time length of the original line period is obtained.
And the column black insertion calculation unit calculates column black insertion correction duration delta T of the row period effective data strobe signal HDE corresponding to the single-side increased black insertion column in the original video picture according to the number of pixels in each row in the physical pixels of the micro display panel. As shown in fig. 2.
An HDE start point operation unit, where the HDE start point operation unit corrects the duration Δt and the first duration T according to the column black insertion 1 Calculating the starting time point T of the modified line period effective data strobe signal HDE m I.e. said first time period T 1 And subtracting the column black insertion correction time delta T to obtain the time interval of the triggering edge of the corrected row period effective data strobe signal HDE relative to the triggering edge of the original row synchronizing signal HS.
HDE end point operationA unit for calculating the end point of the HDE according to the start time point T of the modified line period effective data strobe signal HDE m Calculating the end time point T of the modified row period effective data strobe signal HDE according to the row period effective data strobe signal HDE time length corresponding to the physical resolution of the micro display panel n I.e. the point in time T of the ending edge of the modified row period active data strobe signal HDE n 。
An HDE validity checking unit, which outputs the timing value X outputted by the HS signal timing unit and the start time point T of the corrected row period valid data strobe signal HDE m And an end time point T of the modified line period valid data strobe signal HDE n Comparing, when T m ﹤X﹤T n At the beginning time point T m And end time point T n And an adaptive row period effective data strobe signal HDE as a signal duration of the corrected row period effective data strobe signal HDE.
In this embodiment, the field period valid data strobe signal VDE adaptive unit includes:
the VS signal timing unit is used for timing according to an original field synchronizing signal VS trigger edge and an original line synchronizing signal HS trigger edge which are input into the VS signal timing unit; the trigger edge of the original field synchronization signal VS is a level jump edge occurring when the active state of the original field synchronization signal VS arrives, for example, when the original field synchronization signal VS is active at a high level, the trigger edge of the original field synchronization signal VS is a rising edge, and when the original field synchronization signal VS is active at a low level, the trigger edge of the original field synchronization signal VS is a falling edge.
A third duration detection unit for detecting the period duration t of the original field synchronizing signal VS according to the timing result of the VS signal timing unit 0 I.e. the sum of the high-level duration and the low-level duration in the original field sync signal VS.
A fourth time length detection unit for detecting the effective data strobe signal of the original field period according to the timing result of the VS signal timing unitVDE trigger edge to detect a second duration T from the original field sync signal VS trigger edge to the original field period valid data strobe signal VDE trigger edge 2 The second time period T 2 I.e. the sum of the original field sync signal VS duration plus the back porch duration of the original field period valid data strobe signal VDE.
And the row black insertion calculation unit is used for calculating row black insertion correction duration delta t of the field period effective data strobe signal VDE corresponding to the single-side increased black insertion row in the original video picture according to the row number in the physical pixel of the micro display panel. As shown in fig. 3.
A VDE start point operation unit, wherein the VDE start point operation unit is used for correcting the duration delta T of the line black insertion and the second duration T 2 Calculating the start time point t of the corrected field period effective data strobe signal VDE m I.e. said second time period T 2 Subtracting the row black inserting correction time length delta t to obtain the time interval of the triggering edge of the corrected row black inserting correction time length delta t relative to the triggering edge of the original field synchronizing signal VS.
A VDE end point operation unit for effectively outputting the start time point t of the data strobe signal VDE according to the corrected field period m Calculating the end time point t of the corrected field period effective data strobe signal VDE according to the field period effective data strobe signal VDE duration corresponding to the physical resolution of the micro-display panel n I.e. the point in time t of the ending edge of the modified field period valid data strobe signal VDE n 。
A VDE validity checking unit for outputting a timing value x and a start time t of the corrected field period valid data strobe signal VDE to the VS signal timing unit m And an end time point t of the modified field period valid data strobe signal VDE n Checking when t m ﹤x﹤t n At the beginning time point t m And end time point t n The adaptive field period valid data strobe signal VDE as the signal duration of the modified field period valid data strobe signal VDE.
In this embodiment, the circuit structure of the HS signal timing unit is shown in fig. 4, and the HS signal timing unit includes a first data selector 101, a first multi-bit wide flip-flop 102, and a first 1-bit adder 103. As shown in fig. 4, the original row synchronization signal HS trigger edge is input to the channel selection terminal of the first data selector 101, and when the original row synchronization signal HS trigger edge arrives, a 1-channel is selected, and the input of the 1-channel is at a low level. When the original line synchronization signal HS ends, a 0 channel is selected. The output end of the first data selector 101 is connected to the D input end of the first multi-bit wide flip-flop 102, the Q output end of the first multi-bit wide flip-flop 102 is connected to the input end of the first 1-bit adder 103, and the output end of the first 1-bit adder 103 is connected to the 0-channel input end of the first data selector 101. The Q output of the first multi-bit wide flip-flop 102 also serves as the timing output of the HS signal timing unit. In this embodiment, the HS signal timing unit performs timing according to the pixel clock, and the timing result substantially outputs the number of pixel clocks.
In this embodiment, the circuit structure of the first time length detection unit is shown in fig. 5, and the first time length detection unit includes a second data selector 104 and a second multi-bit wide flip-flop 105. The 1-channel input end of the second data selector 104 is connected to the timing output of the HS signal timing unit, and the channel selection end of the second data selector 104 is connected to the original line synchronization signal HS trigger edge signal. The output terminal of the second data selector 104 is connected to the D input terminal of the second multi-bit wide flip-flop 105, and the Q output terminal of the second multi-bit wide flip-flop 105 is connected to the 0-channel input terminal of the second data selector 104. Namely, when the timing unit of the HS signal is reset due to the access of the HS trigger edge of the original line synchronizing signal, the period duration T of the HS period of the previous original line synchronizing signal before the HS trigger edge of the original line synchronizing signal 0 Is acquired by the first time length detection unit.
In this embodiment, the circuit structure of the second duration detection unit is shown in fig. 6, and the second duration detection unit includes a third data selector 106 and a third multi-bit wide flip-flop 107. By a means ofThe 1-channel input end of the third data selector 106 is connected to the timing output of the HS signal timing unit, and the channel selection end of the third data selector 106 is connected to the active data strobe signal HDE trigger edge of the original row period. An output terminal of the third data selector 106 is connected to a D input terminal of a third multi-bit wide flip-flop 107, and a Q output terminal of the third multi-bit wide flip-flop 107 is connected to a 0-channel input terminal of the third data selector 106. I.e. when the active data strobe signal HDE trigger edge of the original row period comes, the first time length T 1 Is acquired by the second duration detection unit.
In this embodiment, the column black insertion calculation unit has a structure as shown in fig. 7, and includes a first subtraction unit 108 and a first shift operation unit 109, where the first subtraction unit 108 performs a first shift operation according to an input period duration T 0 And calculating the column black inserting correction time length 2 delta T at the left side and the right side of the correction picture according to the number of pixels in each row in the physical pixels of the micro display panel. The result is that the binary value is shifted one bit to the left by the first shift operation unit 109 to achieve the effect of dividing 2, and the single-side column black insertion correction duration Δt is obtained.
In this embodiment, the circuit structure of the VS signal timing unit is shown in fig. 8, and the VS signal timing unit includes a fourth data selector 1001, a fourth multi-bit wide flip-flop 1002, a second 1-bit adder 1003, and a fifth data selector 1004. As shown in fig. 8, the original field sync signal VS triggers a channel selection terminal connected to the fourth data selector 1001, and when the original field sync signal VS arrives, a 1-channel is selected, and the input of the 1-channel is low. When the original field sync signal VS ends, a 0 channel is selected. An output terminal of the fourth data selector 1001 is connected to a D input terminal of a fourth multi-bit wide flip-flop 1002, a Q output terminal of the fourth multi-bit wide flip-flop 1002 is connected to an input terminal of a second 1-bit adder 1003, and an output terminal of the second 1-bit adder 1003 is connected to a 1-channel input terminal of a fifth data selector 1004. While the Q output of the fourth multi-bit wide flip-flop 1002 is directly connected to the 0-channel input of the fifth data selector 1004. An output terminal of the fifth data selector 1004 is connected to the fourth data selector 10010 channel input of (c). The channel selection end of the fifth data selector 1004 is connected to the original line synchronization signal HS trigger edge signal. The Q output of the fourth multi-bit wide flip-flop 1002 also serves as the timing output of the VS signal timing unit. In this embodiment, the VS signal timing unit performs timing according to the pixel clock and the trigger edge of the original line synchronization signal HS, and the timing result substantially outputs the period duration T of the original line synchronization signal HS 0 Is a number of (3).
In this embodiment, the circuit structure of the third duration detection unit is the same as that of the first duration detection unit, except that the input signal becomes the timing output of the VS signal timing unit and the trigger edge of the original field synchronization signal VS. The circuit structure of the fourth time length detection unit is the same as that of the second time length detection unit, except that the input signal is changed into the timing output of the VS signal timing unit and the trigger edge of the original field period effective data strobe signal VDE.
In this embodiment, the structure of the row black insertion calculation unit is as shown in fig. 9, and the row black insertion calculation unit includes a second subtraction unit 1005 and a second shift operation unit 1006, where the second subtraction unit 1005 is according to the input period duration t 0 And calculating row black inserting correction time length 2 x delta t on the upper side and the lower side of the correction picture by the row number in the physical pixel of the micro display panel. The result is that the binary value is shifted one bit to the left by the second shift operation unit 1006 to achieve the effect of dividing 2, so as to obtain the black inserting correction duration delta t of the single-side row.
The above description is only a specific embodiment of the present invention, and the scope of the present invention is not limited thereto, and any person skilled in the art should modify or replace the present invention within the technical specification described in the present invention.
Claims (10)
1. An input signal phase relation adaptive circuit in a micro display panel, the input signal phase relation adaptive circuit comprising: a row period valid data strobe signal HDE adaptive unit and a field period valid data strobe signal VDE adaptive unit;
wherein the row period valid data strobe signal HDE adaptation unit comprises:
the HS signal timing unit is used for timing the original line synchronizing signal HS and resetting a timing result according to the input triggering edge of the original line synchronizing signal HS;
a first time length detection unit for detecting the period length T of the original line synchronous signal HS according to the timing result of the HS signal timing unit 0 ；
A second time length detection unit for detecting a first time length T from the HS trigger edge of the original line synchronous signal to the HDE trigger edge of the effective data strobe signal according to the timing result of the HS signal timing unit and the HDE trigger edge of the effective data strobe signal of the original line period 1 ；
A column black insertion calculation unit, which calculates a column black insertion correction duration deltat of a row period effective data strobe signal HDE corresponding to a single-side increase black insertion column in an original video picture according to the number of pixels in each row in physical pixels of the micro display panel;
an HDE start point operation unit, where the HDE start point operation unit corrects the duration Δt and the first duration T according to the column black insertion 1 Calculating the starting time point T of the modified line period effective data strobe signal HDE m ；
An HDE end point operation unit for outputting the start time point T of the modified line period valid data strobe signal HDE m And calculating the end time point T of the modified row period effective data strobe signal HDE by the micro display panel physical resolution n ；
An HDE validity checking unit, which outputs the timing value X outputted by the HS signal timing unit and the start time point T of the corrected row period valid data strobe signal HDE m And an end time point T of the modified line period valid data strobe signal HDE n Checking, namely outputting an adaptive line period effective data strobe signal HDE after checking is passed;
the field period valid data strobe signal VDE adaptation unit comprises:
the VS signal timing unit is used for timing the original field synchronizing signal VS and resetting a timing result according to the trigger edge of the input original field synchronizing signal VS;
a third duration detection unit for detecting the period duration t of the original field synchronizing signal VS according to the timing result of the VS signal timing unit 0 ；
A fourth time length detection unit for detecting a second time length T from the trigger edge of the original field synchronizing signal VS to the trigger edge of the original field period effective data strobe signal VDE according to the timing result of the VS signal timing unit and the trigger edge of the original field period effective data strobe signal VDE 2 ；
A row black insertion calculation unit, which calculates a row black insertion correction duration deltat of a field period effective data strobe signal VDE corresponding to a single-side increase black insertion row in an original video picture according to the number of rows in a physical pixel of a micro display panel;
a VDE start point operation unit, wherein the VDE start point operation unit is used for correcting the duration delta T of the line black insertion and the second duration T 2 Calculating the start time point t of the corrected field period effective data strobe signal VDE m ；
A VDE end point operation unit for effectively outputting the start time point t of the data strobe signal VDE according to the corrected field period m And calculating an end time point t of the corrected field period effective data strobe signal VDE by the micro display panel physical resolution n ；
A VDE validity checking unit for outputting a timing value x and a start time t of the corrected field period valid data strobe signal VDE to the VS signal timing unit m And an end time point t of the modified field period valid data strobe signal VDE n And checking, and outputting the effective data strobe signal VDE of the adaptive field period after the checking is passed.
2. The input signal phase relation adaptive circuit according to claim 1, wherein the trigger edge of the original row synchronization signal HS is a level jump edge occurring when the active state of the original row synchronization signal HS arrives; when the original line synchronizing signal HS is effective at high level, the triggering edge of the original line synchronizing signal HS is a rising edge, and when the original line synchronizing signal HS is effective at low level, the triggering edge of the original line synchronizing signal HS is a falling edge.
3. The adaptive circuit of claim 1, wherein the trigger edge of the original field sync signal VS is a rising edge when the original field sync signal VS is active high, and the trigger edge of the original field sync signal VS is a falling edge when the original field sync signal VS is active low.
4. The input signal phase relation adaptive circuit according to claim 1, wherein the HS signal timing unit performs timing according to a pixel clock, and the timing result is a sum of durations of a plurality of pixel clock periods.
5. The adaptive circuit of claim 1, wherein the VS signal timing unit is configured to perform timing according to a pixel clock and an initial line synchronization signal HS trigger edge, and the timing result is a plurality of period durations T 0 Is a sum of the durations of (a).
6. The input signal phase relationship adaptation circuit of claim 1, wherein the first duration T 1 The sum of the original line synchronizing signal HS time length and the effective data strobe signal HDE back porch time length of the original line period is obtained.
7. The infusion of claim 1An incoming signal phase relation adaptive circuit, characterized in that the second time period T 2 I.e. the sum of the original field sync signal VS duration plus the back porch duration of the original field period valid data strobe signal VDE.
8. The adaptive circuit according to claim 1, wherein the timing value X outputted from the HS signal timing unit, the start time point T of the modified line period valid data strobe signal HDE m And an end time point T of the modified line period valid data strobe signal HDE n The verification means that: when T is m ﹤X﹤T n When the time passes, the verification is passed, and the starting time point T is taken as m And end time point T n An adaptive row period active data strobe signal HDE is generated.
9. The input signal phase relation adaptive circuit according to claim 1, wherein the timing value x outputted to the VS signal timing unit, the start time point t of the corrected field period valid data strobe signal VDE m And an end time point t of the modified field period valid data strobe signal VDE n The verification means that: when t m ﹤x﹤t n When the time passes, the verification is passed, and the starting time point t is taken as m And end time point t n An adaptive field period valid data strobe signal VDE is generated.
10. A micro-display panel, comprising an input signal phase relation adaptive circuit according to any one of claims 1-9.
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