CN116741777A - Integrated circuit including active pattern having variable width and design method thereof - Google Patents

Abstract

An integrated circuit may include: a first active pattern group extending along a first direction in a first row and including a plurality of active patterns overlapping each other in the first direction, the first row extending along the first direction; and A plurality of gate electrodes extending in a first row along a second direction perpendicular to the first direction, wherein two active patterns in the first active pattern group adjacent to each other in the first direction may be in a second row. have the same width in two directions, or have a width that differs by a first offset or a second offset in a second direction.

Description

Integrated circuit including active pattern with variable width and design method thereof

Cross-references to related applications

This application is based on and claims Korean Patent Application No. 10-2022-0030331 filed with the Korean Intellectual Property Office on March 10, 2022, and Korean Patent Application No. 10 filed with the Korean Intellectual Property Office on June 22, 2022 -2022-0076380, the entire disclosure of which is incorporated herein by reference.

Technical field

The inventive concept relates to integrated circuits, and more particularly, to integrated circuits including active patterns with variable widths and design methods thereof.

Background technique

Devices with various structures have been developed, and these devices can each have unique properties. New devices may be formed through new processes (eg, sub-processes), and accordingly, new design rules may be beneficial in designing integrated circuits including the new devices.

Contents of the invention

The inventive concept provides an integrated circuit including an active pattern with variable width and a design method thereof.

According to an aspect of the inventive concept, an integrated circuit is provided, the integrated circuit including: a first active pattern group extending along a first direction in a first row and including a plurality of active patterns overlapping each other in the first direction. source patterns, a first row extending in a first direction; and a plurality of gate electrodes in the first row extending in a second direction perpendicular to the first direction, wherein the first active pattern group in the first direction Two active patterns adjacent to each other may have the same width in the second direction, or have widths that differ by the first offset amount or the second offset amount in the second direction.

According to an aspect of the inventive concept, there is provided an integrated circuit including a plurality of functional units arranged in a first row extending along a first direction, wherein each of the plurality of functional units arranged in the first row The functional units may include an active pattern extending in a first direction and at least one gate electrode extending in a second direction perpendicular to the first direction, and be adjacent to each other in the first row and overlap each other in the first direction. The two active patterns respectively included in the two functional units may have the same width in the second direction, or have widths that differ by the first offset or the second offset in the second direction.

According to an aspect of the inventive concept, an integrated circuit is provided, including: a plurality of units; a first pattern and a second pattern extending along a first direction and adjacent to each other to power a first unit among the plurality of units; a plurality of first active patterns extending in a first direction between the first pattern and the second pattern and overlapping each other in the first direction; and a plurality of first gate electrodes between the first pattern and the second pattern extending along a second direction perpendicular to the first direction, wherein two first active patterns among the plurality of first active patterns that are adjacent to each other in the first direction may have the same width in the second direction or There is a width different from the first offset amount or the second offset amount in the second direction.

Description of drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

1A and 1B are perspective views of devices according to example embodiments;

2A and 2B are plan views illustrating the layout of an integrated circuit according to example embodiments;

3A and 3B are plan views illustrating the layout of an integrated circuit according to example embodiments;

4 is a plan view showing the layout of a unit according to an example embodiment;

5 is a plan view illustrating the layout of an integrated circuit according to an example embodiment;

6A, 6B, 6C, 6D, 6E, and 6F are plan views illustrating the layout of an integrated circuit according to example embodiments;

7 is a flowchart illustrating a method of manufacturing an integrated circuit according to example embodiments;

8 is a block diagram illustrating a system-on-chip according to an example embodiment; and

9 is a block diagram illustrating a computing system including memory for storing programs, according to an example embodiment.

Detailed ways

1A and 1B are perspective views of devices according to example embodiments. For example, Figure IA shows a fin field effect transistor (FinFET) 10a, and Figure IB shows a gate all around field effect transistor (GAAFET) 10b. For convenience of explanation, FIGS. 1A and 1B show a state in which one of the two source/drain regions has been removed.

Herein, the X-axis direction and the Y-axis direction may be referred to as a first direction (also referred to as a first horizontal direction) and a second direction (also referred to as a second horizontal direction), respectively, and the Z-axis direction may be referred to as It is called the vertical direction or the third direction. A plane having an X-axis and a Y-axis may be referred to as a horizontal plane, a component arranged in the +Z direction relative to other components may be referred to as a component above other components, and a component arranged in the -Z direction relative to other components may be Called a component that is underneath other components. Additionally, the area of a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends (eg, extends longitudinally). The surface exposed in the +Z direction may be referred to as the top surface or upper surface, the surface exposed in the −Z direction may be referred to as the bottom surface or lower surface, and the surface exposed in the ±X direction or ±Y direction may be are called lateral surfaces. In the drawings, for convenience of explanation, only some layers may be shown, and to indicate a connection between an upper pattern and a lower pattern, a via hole may be shown although the via hole is located below the upper pattern. In addition, a pattern made of a conductive material (for example, a pattern of a wiring layer) may be called a conductive pattern or may be simply called a pattern.

Integrated circuits may be manufactured through semiconductor processes and may include multiple devices. For example, an integrated circuit may include active devices such as transistors and/or passive devices such as capacitors. A semiconductor process may include a series of sub-processes for forming transistors with predefined structures. For example, FinFET 10a and GAAFET 10b may be formed through a semiconductor process. In some embodiments, the semiconductor process may include a sub-process for forming transistors having a different structure than that of FinFET 10a and GAAFET 10b. For example, a nanosheet for a P-type transistor and a nanosheet for an N-type transistor may be separated by a dielectric wall, thereby forming a ForkFET having a structure of N-type transistors and P-type transistors adjacent to each other through a semiconductor process. In addition, bipolar junction transistors and field effect transistors (FETs) (eg, complementary FETs (CFETs), negative FETs (NCFETs), carbon nanotube (CNT) FETs, etc.) can be formed through semiconductor processes.

Referring to FIG. 1A , the FinFET 10 a may be formed of first to third active patterns A1 to A3 having a shallow thickness and a gate electrode G extending in the Y-axis direction. A fin shape extending in the X-axis direction between trench isolation portions (STI). Source/drain regions SD may be formed on either side of the gate electrode G, and first channels CH1 to CH1 to third active patterns A3 respectively corresponding to the source/drain regions SD may be formed between the source/drain regions SD. The third channel CH3. The first to third channels CH1 to CH3 may overlap the gate electrode G in the Y-axis and Z-axis directions, and may overlap the gate electrode G with each of the first to third channels CH1 to CH3 An insulating layer is formed between them. In some embodiments, unlike what is shown in FIG. 1A , the source/drain region SD may be composed of three parts corresponding to the first to third active patterns A1 to A3 respectively. As used herein, "element A extends in the X direction" (or similar language) may mean that element A extends longitudinally in the X direction. Furthermore, as used herein, "element A overlaps element B in the X direction" (or similar language) means that there is at least one line that extends in the X direction and intersects both elements A and B.

The effective channel width of the FinFET 10a may depend on the number of active patterns, and therefore, the FinFET 10a may have a current driving capability corresponding to the number of active patterns. For example, a FinFET including one or two channels may have lower current drive capabilities and power consumption than FinFET 10a of Figure 1A. Additionally, FinFETs including more than three channels may have higher current drive capabilities and power consumption than FinFET 10a of FIG. 1A. Integrated circuits may include FinFETs that include various numbers of channels to optimize performance and efficiency.

Referring to FIG. 1B , the GAAFET 10b may be formed of an active pattern A1 extending in the X-axis direction and a gate electrode G extending in the Y-axis direction. The source/drain regions SD may be formed on either side of the gate electrode G, and have first to third nanosheets NS1 to NS3 spaced apart from each other in the Z-axis direction and extending in the X-axis direction while having a first width W1 A channel may be formed between the source/drain regions SD. As shown in Figure 1B, GAAFET 10b including nanosheets may be referred to as a multi-bridge channel field effect transistor (MBCFET). The first to third nanosheets may overlap the gate electrode G in the Y-axis and Z-axis directions, and an insulation may be formed between the gate electrode G and each of the first to third nanosheets. layer.

The effective channel width of GAAFET 10b may depend on the number and width of nanosheets, and therefore, GAAFET 10b may have a current driving capability corresponding to the number and width of nanosheets. For example, a GAAFET including one or two nanosheets or a nanosheet having a width smaller than the first width W1 may have lower current driving capability and power consumption than the GAAFET 10b of FIG. 1B. Furthermore, a GAAFET including more than three nanosheets or including nanosheets with a width greater than the first width W1 may have higher current driving capability and power consumption than the GAAFET 10b of FIG. 1B. Integrated circuits can include GAAFETs, which include various numbers and widths of nanosheets to optimize performance and efficiency.

A transition of active patterns may refer to a change in the number and/or width of active patterns adjacent to each other in the device. FinFET 10a can realize the transformation of the active pattern by adjusting the number of channels (or the number of fins), while GAAFET 10b can realize the transformation of the active pattern by adjusting the first width W1 of the nanosheet. Therefore, compared with FinFET 10a, GAAFET10b can support devices with more various features.

As device size decreases to achieve high integration levels, the difficulty of the semiconductor process may increase and the transformation of active patterns may be limited by the semiconductor process. For example, when large transitions in active patterns occur, such as when designing structures in which the width of the nanosheets in an integrated circuit is greatly reduced or greatly increased, the semiconductor process may not readily implement the designed structure. Therefore, when the transition of the active pattern is large, the yield of the integrated circuit may be reduced, or the area of the integrated circuit may be increased due to the space for the transition of the active pattern (eg, diffusion interruption).

As described below with reference to the accompanying drawings, integrated circuits can be designed taking into account semiconductor processes, thereby reducing the time and cost required to design integrated circuits and improving the yield rate of integrated circuits. Furthermore, the integrated circuit can have high reliability, and accordingly, the reliability of applications including the integrated circuit can be improved. In addition, integrated circuits with high reliability can be easily designed, thereby significantly shortening the time to market of integrated circuits. Hereinafter, GAAFET (ie, MBCFET) will be mainly described as an example of the device, but note that embodiments of the inventive concept are not limited thereto. Furthermore, although the transformation of the active pattern by changing the width of the nanosheets will mainly be described, note that the transformation of the active pattern can occur by changing the number of nanosheets, as described above.

2A and 2B are plan views illustrating the layout of an integrated circuit according to example embodiments. Hereinafter, redundant descriptions of FIGS. 2A and 2B will be omitted.

Referring to Figure 2A, an integrated circuit may include a plurality of standard cells. A standard cell is a layout unit included in an integrated circuit, and may be simply called a cell. The unit may include transistors and may be designed to perform predefined functions. In integrated circuits, cells can be aligned and arranged along rows. For example, in FIG. 2A , the first row R1 and the second row R2 may extend in the X-axis direction, and the cells may be arranged in the first row R1 and/or the second row R2. Units arranged in one row may be referred to as single-height units, and units arranged in two or more consecutive rows may be referred to as multi-height units. The single-height units arranged in the first row R1 may have a first height H1 in the Y-axis direction, the single-height units arranged in the second row R2 may have a second height H2 in the Y-axis direction, and the single-height units arranged continuously in The multi-height cells in the first row R1 and the second row R2 may have a height corresponding to the sum of the heights H1 and H2 in the Y-axis direction.

In some embodiments, the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same as or different from each other. For example, as shown in FIG. 2A, the second height H2 may be greater than the first height H1 (H2>H1). Rows with different heights can be arranged in various ways. For example, the rows with the first height H1 and the rows with the second height H2 may be alternately arranged in a ratio of 1:1, 2:2, 4:4, etc.

Patterns for supplying power to the cells can be arranged on the boundaries of the rows. For example, as shown in FIG. 2A , the first to third metal patterns M21 to M23 may extend in the X-axis direction on the boundary of the first row R1 and the second row R2. The negative power supply voltage VSS may be applied to the first and third metal patterns M21 and M23, and an n-channel field effect transistor (NFET) may be arranged adjacent to the first and third metal patterns M21 and M23. In addition, the positive power supply voltage VDD may be applied to the second metal pattern M22, and a p-channel field effect transistor (PFET) may be arranged adjacent to the second metal pattern M22.

The integrated circuit may include an active pattern extending in the X-axis direction, and the unit may include a transistor formed of the active pattern. For example, as shown in FIG. 2A , the integrated circuit 20a may include a plurality of first active patterns A11 to A13 overlapping each other in the X-axis direction and a plurality of first active patterns A11 to A13 overlapping each other in the X-axis direction in the first row R1. Two active patterns A21 to A23. In addition, the integrated circuit 20a may include a plurality of third active patterns A31 to A33 overlapping each other in the X-axis direction and a plurality of fourth active patterns A41 to A43 overlapping each other in the X-axis direction in the second row R2 . As shown in FIG. 2A , a plurality of first active patterns A11 to A13 and a plurality of fourth active patterns A41 to A43 adjacent to the first and third metal patterns M21 and M23 to which the negative power supply voltage VSS is applied An n-channel field effect transistor (NFET) may be formed, and the plurality of second active patterns A21 to A23 and the plurality of second active patterns A31 to A33 adjacent to the second metal pattern M22 to which the positive power supply voltage VDD is applied may A p-channel field effect transistor (PFET) is formed.

In some embodiments, the transition of active patterns may be limited to a predefined size. For example, as shown in FIG. 2A , the transition of the active patterns among the plurality of first active patterns A11 to A13 in the first row R1 may be limited to the first offset OS1. Therefore, the difference between the widths of the first active patterns A11 and A12 adjacent to each other may correspond to the first offset amount OS1, and the difference between the widths of the first active patterns A12 and A13 adjacent to each other also May correspond to the first offset OS1. In addition, the transition of the active patterns among the plurality of second active patterns A21 to A23 in the first row R1 may be limited to the second offset OS2. In some embodiments, the first offset OS1 and the second offset OS2 may be the same. Similarly, the transition of the active patterns in the plurality of third active patterns A31 to A33 in the second row R2 may be limited to the third offset OS3, and the plurality of fourth active patterns in the second row R2 The transition of the active patterns in patterns A41 to A43 may be limited to the fourth offset OS4. In some embodiments, the third offset OS3 and the fourth offset OS4 may be the same. The first to fourth offset amounts OS1 to OS4 may be defined by a semiconductor process used to manufacture the integrated circuit 20a, and therefore, errors caused by excessive transitions of active patterns in the integrated circuit 20a may be eliminated.

In some embodiments, the width of the active patterns in the first row R1 and the width of the active patterns in the second row R2 may be different. For example, the maximum width (or minimum width) of the plurality of first active patterns A11 to A13 in the first row R1 may be the same as the maximum width (or minimum width) of the plurality of fourth active patterns A41 to A43 in the second row R2. width) are different. In addition, the maximum width (or minimum width) of the plurality of second active patterns A21 to A23 in the first row R1 may be the same as the maximum width (or minimum width) of the plurality of third active patterns A31 to A33 in the second row R2. width) are different. The maximum width of the active pattern may refer to the widest width of the active pattern. Therefore, the maximum width of the first active patterns A11 to A13 may be the width of the first active pattern A13, and the maximum width of the second active patterns A21 to A23 may be the width of the second active pattern A23. Furthermore, the minimum width of the active pattern may refer to the narrowest width of the active pattern. Therefore, the minimum width of the first active patterns A11 to A13 may be the width of the first active pattern A11, and the minimum width of the second active patterns A21 to A23 may be the width of the second active pattern A21.

Referring to Figure 2B, active patterns in integrated circuit 20b may have one of two widths. For example, as shown in FIG. 2B , each of the plurality of first active patterns A11 to A13 in the first row R1 that overlap each other in the X-axis direction may have two widths that differ by a first offset OS1 One of W11 and W12. In addition, each of the plurality of second active patterns A21 to A23 in the first row R1 that overlap each other in the X-axis direction may have one of two widths W21 and W22 that differ by the second offset OS2. In some embodiments, the first offset OS1 and the second offset OS2 may be the same. In some embodiments, the widths W11 and W12 of the plurality of first active patterns A11 to A13 may be the same as the widths W21 and W22 of the plurality of second active patterns A21 to A23, respectively. Similarly, in the second row, each of the plurality of third active patterns A31 to A33 that overlap each other in the X-axis direction may have one of two widths W3 1 and W32 that differ by the third offset OS3 , and each of the plurality of fourth active patterns A41 to A43 that overlap each other in the X-axis direction may have one of two widths W41 and W42 that differ by the fourth offset amount OS4. In some embodiments, the third offset OS3 and the fourth offset OS4 may be the same. In some embodiments, the widths W31 and W32 of the plurality of third active patterns A31 to A33 may be the same as the widths W41 and W42 of the plurality of fourth active patterns A41 to A43, respectively.

3A and 3B are plan views illustrating the layout of an integrated circuit according to example embodiments. In some embodiments, cells may be terminated by a diffusion break, and transitions of active patterns may occur in the diffusion break. In some embodiments, the active patterns in the cells may have a constant width. For example, as shown in Figures 3A and 3B, the active pattern can have a constant width within a cell and different widths in different cells. Hereinafter, redundant descriptions of FIGS. 3A and 3B will be omitted.

Referring to FIG. 3A, the integrated circuit 30a may include a first unit C31a and a second unit C32a. The first unit C31a may include active patterns A11 and A21 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second unit C32a may include active patterns A12 and A22 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The gate electrode may extend in the Y-axis direction with a Contacted Poly Pitch (CPP), and in FIG. 3A , each of the first unit C31a and the second unit C32a may have three pixels in the X-axis direction. The length of CPP.

A diffusion break may be formed at a boundary parallel to the Y-axis of the first cell C31a and the second cell C32a instead of the gate electrode, and the first cell C31a and the second cell C32a arranged adjacent to each other may share one diffusion break. As shown in FIG. 3A, the diffusion break arranged at the location of the gate electrode may be called a single diffusion break (SDB) or a dummy gate. In some embodiments, unlike the illustration in FIG. 3A , cells may have boundaries extending in the X-axis direction between gate electrodes, and diffusion interruptions formed between gate electrodes of adjacent cells may be referred to as double Diffusion Break (DDB).

As shown in FIG. 3A , the active pattern A11 for the PFET in the first cell C31a may have a first width W1, and the active pattern A12 for the PFET in the second cell C32a may have a second width W2. As described above with reference to FIGS. 2A and 2B , the second width W2 may be larger than the first width W1 by a first offset OS1 . The width of the active pattern may be changed at the diffusion interruption between the first cell C31a and the second cell C32a, and the active pattern may be removed from the diffusion interruption. The active pattern A11 and the active pattern A12 may be spaced apart from each other in the X-axis direction, and no active pattern may be provided between the active pattern A11 and the active pattern A12, as shown in FIG. 3A. The active pattern A11 and the active pattern A12 may be directly adjacent to each other. The term "directly adjacent" as used herein includes a configuration in which two "elements" directly adjacent to each other (eg, active patterns A11 and A12) are positioned such that no other similar elements are located between each other. between two directly adjacent components.

Referring to FIG. 3B, the integrated circuit 30b may include first to fourth units C31b to C34b. The first unit C31b may include active patterns A11 and A21 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second unit C32b may include active patterns A12 and A22 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. As shown in FIG. 3B , the active pattern A11 of the first unit C31b and the active pattern A12 of the second unit C32b may have a first width W1, and may be formed by passing along Y between the first unit C31b and the second unit C32b. The axially extending SDBs are spaced apart from each other.

The fourth unit C34b may include active patterns A13 and A23 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second width W2 of the active pattern A13 of the fourth unit C34b may be larger than the first width W1 of the active pattern A12 of the second unit C32b by the first offset OS1. Unlike the integrated circuit 30a of FIG. 3A, the transition of the active pattern in the integrated circuit 30b of FIG. 3B may require diffusion interruptions to extend along the Y-axis direction by a width of CPP or greater. Therefore, the integrated circuit 30b may include the third cell C33b between the second cell C32b and the fourth cell C34b, and the active pattern may be removed from the third cell C33b. In some embodiments, the third cell C33b may not include any active patterns. Herein, units including transistors (or active patterns) and designed to perform functions through the transistors (for example, the first unit C31b, the second unit C32b, and the fourth unit C34b) may be referred to as functional units. Furthermore, as shown in the third cell C33b, a unit for conversion of an active pattern inserted between functional units may be called a filling unit. In some embodiments, unlike the illustration in FIG. 3B , the filling unit may correspond to one CPP (1CPP) or have a length of more than two CPPs (2CPP) in the X-axis direction.

4 is a plan view showing the layout of a unit according to an example embodiment. In some embodiments, active pattern transitions may occur within cells.

Referring to FIG. 4 , cell C40 may include active patterns A11 and A12 overlapping each other in the X-axis direction and active patterns A21 and A22 overlapping each other in the X-axis direction. The width W12 of the active pattern A12 may be larger than the width W11 of the active pattern A11 by a first offset OS1, and the width W22 of the active pattern A22 may be larger than the width W21 of the active pattern A21 by a second offset OS2. The first offset OS1 and the second offset OS2 may be defined by a semiconductor process, and the unit C40 may be designed to include a transition of the active pattern corresponding to the first offset OS1 or the second offset OS2. Therefore, unit C40 can be designed with optimized performance and efficiency, and errors caused by unit C40 can be reduced or prevented.

FIG. 5 is a plan view showing the layout of integrated circuit 50 according to an example embodiment. As described above with reference to FIGS. 2A and 2B , the integrated circuit 50 may include a plurality of cells, and the plurality of cells may be arranged in rows extending along the X-axis direction (eg, the first row R1 and/or the second row R2 ). . As described above with reference to FIGS. 2A and 2B , the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same as each other or different from each other.

In some embodiments, the width of the active pattern for the NFET and the width of the active pattern for the PFET in the cell may be different from each other. For example, as shown in FIG. 5 , the active pattern A11 for NFET and the active pattern A12 for PFET may extend in the X-axis direction in the first row R1. The width W11 of the active pattern A11 for NFET may be smaller than the width W12 of the active pattern A12 for PFET (W11<W12). In some embodiments, unlike the illustration in FIG. 5 , the width W11 of the active pattern A11 for NFET may be larger than the width W12 of the active pattern A12 for PFET (W11>W12). Furthermore, as shown in FIG. 5 , the active pattern A21 for PFET and the active pattern A22 for NFET may extend in the X-axis direction in the second row R2. The width W21 of the active pattern A21 for PFET may be larger than the width W22 of the active pattern A22 for NFET (W21>W22). In some embodiments, unlike the illustration in FIG. 5 , the width W21 of the active pattern A21 for PFET may be smaller than the width W22 of the active pattern A22 for NFET (W21<W22).

6A-6F are plan views illustrating the layout of an integrated circuit according to example embodiments. 6A to 6F are plan views showing examples in which active patterns with different widths are aligned in various ways. In FIGS. 6A to 6F , each of the integrated circuits 60 a to 60 f may include first to third metal patterns M61 to M63 extending in the X-axis direction on the boundary of the first and second rows R1 and R2 . The negative power supply voltage VSS may be applied to the first and third metal patterns M61 and M63, and the positive power supply voltage VDD may be applied to the second metal pattern M62.

Referring to FIG. 6A, the integrated circuit 60a may include active patterns extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60a may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the active pattern may have a boundary that overlaps a line extending in the X-axis direction. For example, as shown in FIG. 6A , the plurality of first active patterns A11 to A14 may have boundaries overlapping the lines X1-X1′ extending in the X-axis direction, and the plurality of second active patterns A21 to A24 may have A boundary that overlaps the line X2-X2' extending in the X-axis direction. As shown in FIG. 6A , the lines X1 - X1 ′ and the lines X2 - to A24 can be arranged between line X1-X1' and line X2-X2'. The plurality of first active patterns A11 to A14 may include corresponding side surfaces (also referred to as first outer surfaces) aligned in the X-axis direction, and the plurality of second active patterns A21 to A24 may include corresponding side surfaces aligned in the X-axis direction. The corresponding side surface (also referred to as the second outer surface) is as shown in Figure 6A. The plurality of first active patterns A11 to A14 may further include first inner surfaces facing the plurality of second active patterns A21 to A24, and the plurality of second active patterns A21 to A24 may further include first inner surfaces facing the plurality of second active patterns A21 to A24. A second inner surface of the active patterns A11 to A14.

Referring to FIG. 6B, the integrated circuit 60b may include active patterns extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60b may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the active pattern may have a boundary that overlaps a line extending in the X-axis direction. For example, as shown in FIG. 6B , the plurality of first active patterns A11 to A14 may have boundaries overlapping the lines X1-X1′ extending in the X-axis direction, and the plurality of second active patterns A21 to A24 may have A boundary that overlaps the line X2-X2' extending in the X-axis direction. As shown in FIG. 6B, the lines X1-X1' and the lines X2-X2' may be adjacent to the center of the first row R1. Therefore, the lines X1-X1' and the lines The patterns A11 to A14 and the plurality of second active patterns A21 to A24 extend along the X-axis direction. The plurality of first active patterns A11 to A14 may include first inner surfaces aligned in the X-axis direction and facing the plurality of second active patterns A21 to A24, and the plurality of second active patterns A21 to A24 may include first inner surfaces along The X-axis direction is aligned with and faces the second inner surfaces of the plurality of first active patterns A11 to A14, as shown in FIG. 6B.

Referring to FIG. 6C , the integrated circuit 60c may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, in the first row R1, the integrated circuit 60c may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the active pattern may have a boundary that overlaps a line extending in the X-axis direction. For example, as shown in FIG. 6C , the plurality of first active patterns A11 to A14 may have boundaries overlapping the lines X1-X1′ extending in the X-axis direction, and the plurality of second active patterns A21 to A24 may have A boundary that overlaps the line X2-X2' extending in the X-axis direction. As shown in Figure 6C, lines X1-X1' may be adjacent to the boundary of the first row R1, and lines X2-X2' may be adjacent to the center of the first row R1. Therefore, the plurality of first active patterns A11 to A14 may be arranged between the lines X1-X1' and the lines X2-X2', and the lines X2-X2' may be arranged between the plurality of first active patterns A11 to A14 and the plurality of The two active patterns A21 to A24 extend along the X-axis direction. The plurality of first active patterns A11 to A14 may include first outer surfaces aligned in the X-axis direction and may include first inner surfaces facing the plurality of second active patterns A21 to A24, and the plurality of second active patterns The patterns A21 to A24 may include second inner surfaces aligned in the X-axis direction and facing the plurality of first active patterns A11 to A14, as shown in FIG. 6C .

Referring to FIG. 6D , the integrated circuit 60d may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, in the first row R1, the integrated circuit 60d may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the center of each active pattern (eg, a center point in the Y-axis direction) may be aligned to overlap a line extending in the X-axis direction. For example, as shown in FIG. 6D , the center of each of the first active patterns A11 to A14 may be aligned to overlap the line X1-X1′ extending in the X-axis direction, and a plurality of second The center of each of the second active patterns A21 to A24 may be aligned to overlap the line X2-X2' extending in the X-axis direction. The first active patterns A11 to A14 may include corresponding center points in the Y-axis direction, and the center points of the first active patterns A11 to A14 are aligned in the X-axis direction. The second active patterns A21 to A24 may include corresponding center points in the Y-axis direction, and the center points of the second active patterns A21 to A24 are aligned in the X-axis direction, as shown in FIG. 6D .

Referring to FIG. 6E , the integrated circuit 60e may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, in the first row R1, the integrated circuit 60e may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. Furthermore, the integrated circuit 60e may include a plurality of third active patterns A31 to A34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the active patterns may be arranged and may have a width to have a constant distance from adjacent active patterns in the Y-axis direction. For example, as shown in FIG. 6E , in the first row R1 , the plurality of first active patterns A11 to A14 may be spaced apart from the plurality of corresponding second active patterns A21 to A24 by a first distance D1 respectively. In addition, the plurality of second active patterns A21 to A24 in the first row may be spaced apart from the plurality of corresponding third active patterns A31 to A34 by a second distance D2, respectively. The first distance D1 and the second distance D2 may be the same as each other or different from each other.

Referring to FIG. 6F, the integrated circuit 60f may include active patterns extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60f may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns A11 to A14 overlapping each other in the X-axis direction. Patterns A21 to A24. Furthermore, the integrated circuit 60f may include a plurality of third active patterns A31 to A34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, active pattern transitions may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be the same as the offset between adjacent active patterns A12 and A13, and may be the same as the offset between adjacent active patterns A13 and A14. The amount is different.

In some embodiments, the center of each active pattern (eg, a center point in the Y-axis direction) may be aligned to overlap a line extending in the X-axis direction. For example, as shown in FIG. 6F , the center of each of the first active patterns A11 to A14 may be aligned to overlap the line X1-X1′ extending in the X-axis direction, and the plurality of second active patterns The center of each second active pattern among the source patterns A21 to A24 may be aligned to overlap the line X2-X2′ extending in the X-axis direction, and each third active pattern among the plurality of third active patterns A31 to A34 The center of the active pattern may be aligned to overlap the line X3-X3' extending in the X-axis direction.

In some embodiments, each active pattern may have a width to have a constant distance from adjacent active patterns in the Y-axis direction. For example, as shown in FIG. 6F , in the first row R1 , the plurality of first active patterns A11 to A14 may be spaced apart from the plurality of corresponding second active patterns A21 to A24 by a first distance D1 respectively. In addition, the plurality of second active patterns A21 to A24 in the first row R1 may be spaced apart from the plurality of corresponding third active patterns A31 to A34 by a second distance D2 respectively. The first distance D1 and the second distance D2 may be the same as each other or different from each other.

7 is a flowchart illustrating a method of manufacturing an integrated circuit (IC) according to example embodiments. For example, the flowchart of FIG. 7 shows an example of a method of manufacturing an integrated circuit (IC) including standard cells. As shown in FIG. 7, a method of manufacturing an integrated circuit (IC) may include a plurality of operations S10, S30, S50, S70, and S90.

The unit library (or standard unit library) D12 may include information on standard units, such as information on functions, characteristics, layout, etc. In some embodiments, the cell library D12 may define standard cells, each standard cell including active patterns of different widths. In some embodiments, the cell library D12 may define standard cells including active patterns whose widths are changed. In some embodiments, cell library D12 may define fill cells inserted for transitions of active patterns. In some embodiments, the cell library D12 may define standard cells having different widths including active patterns for PFETs and active patterns for NFETs, respectively.

Design rules D14 may include requirements to be adhered to by the layout of the integrated circuit IC. For example, the design rule D14 may include requirements for the spacing between patterns on the same layer, the minimum width of patterns, the routing direction of wiring layers, etc. In some embodiments, design rule D14 may define a minimum separation distance in the same track of a routing layer.

In operation S10, a logic synthesis operation of generating the netlist D13 from the register transfer level (RTL) data D11 may be performed. For example, a semiconductor design tool (eg, a logic synthesis tool) may perform logic synthesis on the RTL data D11 with reference to the cell library D12 and generate a netlist D13 including a bitstream or a netlist, the logic synthesis being written as a hardware description language (HDL) , such as VHSIC Hardware Description Language (VHDL) and Verilog. Netlist D13 may correspond to the placement and routing inputs, which will be described below.

In operation S30, units may be arranged. For example, a semiconductor design tool (eg, a P&R tool) may refer to the cell library D12 and the design rule D14 to lay out the standard cells used in the netlist D13. In some embodiments, design rule D14 may define the transitions of active patterns allowed in a row. For example, design rule D14 may define at least one offset allowed in a row, and adjacent active patterns may have the same width, or the widths of adjacent active patterns may differ by at least one offset defined by design rule D14 . The semiconductor design tool may consider adjacent standard cells to select a standard cell including an active pattern with an appropriate width from the cell library D12, and may arrange the selected standard cell.

In operation S50, the pins of the unit may be routed. For example, the semiconductor design tool may generate interconnections electrically connecting output pins and input pins of arranged standard cells, and may generate layout data D15 defining the arranged standard cells and the generated interconnections. Each interconnect may include a via layer of vias and/or a pattern of wiring layers. The layout data D15 may have a format such as Graphic Design System-II (GDSII), and may include geometric information of cells and interconnections. Semiconductor design tools can reference design rule D14 while routing the pins of the cell. The layout data D15 may correspond to the output of placement and routing. Operation S50 alone may be referred to as a method of designing an integrated circuit, or operations S30 and S50 may collectively be referred to as a method of designing an integrated circuit.

In operation S70, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion (eg, refraction due to light characteristics in lithography) may be applied to the layout data D15. Based on the data to which OPC is applied, a pattern on the mask can be defined to form a pattern arranged on a plurality of layers, and at least one mask (or photomask) for forming a pattern for each of the plurality of layers can be manufactured. mold). In some embodiments, the layout of the integrated circuit (IC) may be limitedly changed in operation S70 , and the limited changes to the integrated circuit (IC) in operation S70 may be referred to as design supervision as a method for optimizing the integrated circuit (IC). post-processing of the structure.

In operation S90, an operation of manufacturing an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. Front-end-of-line (FEOL) may include operations such as: planarizing and cleaning the wafer; forming trenches; forming wells; forming gate electrodes; and forming source and drain electrodes. Through FEOL, various devices such as transistors, capacitors, resistors, etc. can be formed on the substrate. In addition, the back-end-of-line (BEOL) may include, for example, the following operations: silicide the gate, source, and drain regions; add dielectric; perform planarization; form holes, add metal layers; form vias; form passivation layers wait. Through BEOL, individual devices such as transistors, capacitors, resistors, etc. can be interconnected. In some embodiments, a mid-line process (MOL) may be performed between the FEOL and BEOL, and contacts may be formed on the respective devices. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in various applications.

8 is a block diagram illustrating a system on a chip (SoC) 80 according to an example embodiment. System-on-chip 80 is a semiconductor device and may include an integrated circuit according to example embodiments. The system-on-chip 80 implements complex blocks (for example, intellectual property (IP)) that perform various functions in one chip, and the system-on-chip 80 can be designed by a method of designing an integrated circuit according to example embodiments. Therefore, the system-on-chip 80 can Provide high yield and reliability with good (e.g., best or highest) performance and efficiency. Referring to FIG. 8 , the system-on-chip 80 may include a modem 82 , a display controller 83 , a memory 84 , an external memory controller 85 , a central processing unit (CPU) 86 , a transaction unit 87 , a power management IC (PMIC) 88 and a graphics processing unit ( GPU)89. The various functional blocks of the system on chip 80 can communicate with each other through the system bus 81 .

The CPU 86, which is capable of controlling the operation of the system-on-chip 80 at the highest level, can control the operation of the other functional blocks 82 to 85 and 87 to 89. The modem 82 may demodulate signals received from outside the system-on-chip 80 or modulate signals generated inside the system-on-chip 80 to transmit signals to the outside. The external memory controller 85 can control operations of transmitting and receiving data from an external memory device connected to the system-on-chip 80 . For example, programs and/or data stored in the external memory device may be provided to the CPU 86 or the GPU 89 under the control of the external memory controller 85. The GPU 89 can execute program instructions related to graphics processing. The GPU 89 may receive graphics data through the external memory controller 85 , or may transmit graphics data processed by the GPU 89 to the outside of the system-on-chip 80 through the external memory controller 85 . The transaction unit 87 can monitor the data transactions of each functional block, and the PMIC 88 can control the power supplied to each functional block under the control of the transaction unit 87 . The display controller 83 may send data generated within the system on chip 80 to the display by controlling a display (or display device) external to the system on chip 80 . Memory 84 may include non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), or may include volatile memory (e.g., dynamic random access memory (DRAM), static random access memory, etc.). Access memory (SRAM, etc.).

Figure 9 is a block diagram illustrating a computing system 90 including memory for storing programs, according to an example embodiment. A method of designing an integrated circuit according to example embodiments, such as at least some operations of the above-described flowchart, may be performed in a computing system (or computer) 90 .

Computing system 90 may be a fixed computing system (eg, desktop computer, workstation, server, etc.), or may be a portable computing system (eg, laptop computer, etc.). As shown in Figure 9, computing system 90 may include a processor 91, an input/output device 92, a network interface 93, a random access memory (RAM) 94, a read only memory (ROM) 95, and a storage device 96. The processor 91 , the input/output device 92 , the network interface 93 , the RAM 94 , the ROM 95 and the storage device 96 may be connected to the bus 97 and may communicate with each other through the bus 97 .

Processor 91 may be referred to as a processing unit and may include a processor capable of executing any instruction set (eg, Intel Architecture-32 (IA-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.), such as a microprocessor, application processor (AP), digital signal processor (DSP), and graphics processing unit. For example, processor 91 can access memory, namely RAM 94 or ROM 95, through bus 97 and can execute instructions stored in RAM 94 or ROM 95.

The RAM 94 may store the program 941 of the method of designing an integrated circuit according to example embodiments, or at least a part thereof, and the program 941 may enable the processor 91 to perform the method of designing an integrated circuit, for example, at least some operations included in the method of FIG. 7 . That is, the program 941 may include a plurality of instructions executable by the processor 91 , and the plurality of instructions included in the program 941 may enable the processor 91 to perform, for example, at least some operations included in the flowcharts described above.

Even if the power supply to computing system 90 is cut off, storage device 96 may not lose stored data. For example, storage device 96 may include a non-volatile storage device, or may include storage media such as magnetic tape, optical disks, and magnetic disks. Additionally, storage device 96 may be removable from computing system 90 . The storage device 96 may store a program 941 according to an example embodiment, and the program 941 or at least a portion thereof may be loaded from the storage device 96 into the RAM 94 before the program 941 is executed by the processor 91 . Alternatively, the storage device 96 may store a file written in a programming language, and the program 941 generated from the file by a compiler or the like or at least a part thereof may be loaded into the RAM 94 . In addition, as shown in FIG. 9 , the storage device 96 may store a database (DB) 961 , and the database 961 may include information required to design the integrated circuit, for example, regarding the designed blocks, the cell library D 1 2 of FIG. 7 and/or or information from Design Rule D14.

Storage device 96 may also store data to be processed by processor 91 or data processed by processor 91. That is, the processor 91 may generate data by processing data stored in the storage device 96 according to the program 941, and may enable the storage device 96 to store the generated data. For example, the storage device 96 may store the RTL data D11, netlist D13, and/or layout data D15 of FIG. 7 .

Input/output devices 92 may include input devices such as keyboards and pointing devices, and may include output devices such as display devices and printers. For example, the user can trigger the processor 91 to execute the program 941 through the input/output device 92, can input the RTL data D11 and/or the netlist D13 of Figure 7, and can check the layout data D15 of Figure 7.

Network interface 93 may provide access to networks external to computing system 90 . For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other form of link.

It will be understood that, although the terms "first," "second," and other terms may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from each other. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the teachings of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the inventive concept has been specifically shown and described with reference to example embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the scope of the inventive concept. The subject matter disclosed above is to be regarded as illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, improvements and other embodiments which fall within the scope of the inventive concept.

Claims (20)

1. An integrated circuit, comprising:

a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction, the first row extending in the first direction; and

a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row,

wherein the plurality of first active patterns includes any two first active patterns adjacent to each other in the first direction, the two first active patterns have a first width and a second width in the second direction, respectively, and the first width and the second width are the same or differ by a first offset amount or a second offset amount.

2. The integrated circuit of claim 1, wherein the plurality of gate electrodes extend in the second direction and have a first pitch,

the first width and the second width are different, and

the two first active patterns are spaced apart from each other in the first direction by at least the first pitch.

3. The integrated circuit of claim 2, wherein there is no active pattern between the two first active patterns.

4. The integrated circuit of claim 1, wherein each of the plurality of first active patterns has the first width or the second width that is wider than the first width by the first offset.

5. The integrated circuit of claim 1, wherein the integrated circuit further comprises a second active pattern group extending along the first direction in a second row adjacent to the first row, the second active pattern group comprising a plurality of second active patterns that overlap each other in the first direction, wherein the first row and the second row have different widths in the second direction.

6. The integrated circuit of claim 5, wherein the plurality of second active patterns comprises any two second active patterns adjacent to each other in the first direction and having the same width in the second direction or having widths in the second direction that differ by a third offset or a fourth offset, and the third offset is different from the first offset and the second offset.

7. The integrated circuit of claim 5, wherein a widest width of the plurality of first active patterns in the second direction is different from a widest width of the plurality of second active patterns in the second direction.

8. The integrated circuit of claim 5, wherein a narrowest width of the plurality of first active patterns in the second direction is different from a narrowest width of the plurality of second active patterns in the second direction.

9. The integrated circuit of claim 1, further comprising: a third active pattern group extending in the first direction in the first row and including a plurality of third active patterns overlapping each other in the first direction,

wherein the plurality of third active patterns includes any two third active patterns adjacent to each other in the first direction and having the same width in the second direction or having widths different from each other by the first offset amount or the second offset amount in the second direction.

10. The integrated circuit of claim 9, wherein the plurality of third active patterns includes respective side surfaces aligned along the first direction.

11. The integrated circuit of claim 10, wherein the respective side surfaces of the plurality of first active patterns are first outside surfaces, and the plurality of first active patterns further comprise respective first inside surfaces opposite the first outside surfaces,

The respective side surfaces of the plurality of third active patterns are third outside surfaces, and the plurality of third active patterns further include respective third inside surfaces opposite the third outside surfaces, and

the first inner side surface faces the third inner side surface.

12. The integrated circuit of claim 10, wherein respective side surfaces of the plurality of first active patterns and respective side surfaces of the plurality of third active patterns are spaced apart from each other and face each other in the second direction.

13. The integrated circuit of claim 10, wherein respective side surfaces of the plurality of third active patterns face the plurality of first active patterns.

14. The integrated circuit of claim 9, wherein each first active pattern of the plurality of first active patterns is spaced apart from a corresponding third active pattern of the plurality of third active patterns in the second direction by a first distance.

15. The integrated circuit of claim 9, wherein the plurality of first active patterns have respective center points aligned along the first direction, and

the plurality of third active patterns have respective center points aligned along the first direction.

16. The integrated circuit of claim 9, wherein one of the plurality of first active patterns and one of the plurality of third active patterns face each other and have different widths in the second direction.

17. The integrated circuit of claim 1, wherein each of the plurality of first active patterns comprises at least one nanoplatelet that overlaps at least one of the plurality of gate electrodes in the second direction and a third direction, the third direction being perpendicular to the first direction and the second direction.

18. An integrated circuit includes a plurality of first functional units arranged in a first row extending in a first direction,

wherein each of the plurality of first functional units comprises:

a first active pattern extending along the first direction; and

at least one first gate electrode extending in a second direction perpendicular to the first direction,

wherein the plurality of first functional units includes two first functional units adjacent to each other, the two first functional units include two first active patterns, respectively, and

the two first active patterns overlap each other in the first direction, have respective widths in the second direction, and have the same width or differ by a first offset amount or a second offset amount.

19. The integrated circuit of claim 18, wherein the widths of the two first active patterns are different, and

the integrated circuit further comprises a filler unit located between the two first functional units.

20. An integrated circuit, comprising:

a plurality of units;

a first pattern and a second pattern extending in a first direction, adjacent to each other, and configured to supply power to a first cell of the plurality of cells;

a plurality of first active patterns extending in the first direction between the first pattern and the second pattern and overlapping each other in the first direction; and

a plurality of first gate electrodes extending between the first pattern and the second pattern in a second direction perpendicular to the first direction,

wherein the plurality of first active patterns includes any two first active patterns adjacent to each other in the first direction, the two first active patterns having respective widths that are the same, or differ by a first offset or a second offset, in the second direction.