CN116734409A - Air conditioner wire controller circuit and control method thereof - Google Patents

Abstract

The application discloses an air conditioner wire controller circuit and a control method thereof, wherein the circuit comprises: a control processing chip provided with a first GPIO port and a second GPIO port; the touch key unit, the WIFI unit, the infrared remote control receiving circuit, the EEPROM storage unit, the indoor unit communication unit, the power-down detection unit, the power supply circuit unit, the clock management unit and the power management unit are electrically connected with the control processing chip, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, namely, the control processing chip is in a power-down mode, the control processing chip is connected with the low-speed clock module of the clock management unit, the functional modules such as the touch key unit are controlled to stop running, and the EEPROM storage unit keeps input unchanged. Based on the scheme of the application, when the power-down mode is entered, the interface input of the EEPROM storage unit is kept unchanged, the power consumption of the EEPROM of the air conditioner wire controller is reduced, the service life of the EEPROM of the air conditioner wire controller is prolonged, and the cost of the air conditioner wire controller is reduced.

Description

Air conditioner wire controller circuit and control method thereof

Technical Field

The application relates to the technical field of electronic circuits, in particular to an air conditioner wire controller circuit and a control method thereof.

Background

The conventional air conditioner wire controller is internally provided with an EEPROM memory chip, each time a user carries out parameter change, the user setting is memorized once, the air conditioner can continue to work under the condition that the power of the air conditioner is cut off and then the power is supplied, the method cannot solve the problem that the calendar work is reset when the system is used for 24 hours, and the conditions that the air quantity, the wind direction and the set temperature are required to be frequently changed in a large public place have obvious influence on the service life of the EEPROM loaded in the air conditioner wire controller, and the EEPROM device is required to be frequently replaced, so that the cost of the air conditioner wire controller is high.

Disclosure of Invention

The embodiment of the application provides an air conditioner wire controller circuit and a control method thereof, which can effectively reduce the power consumption of an EEPROM of the air conditioner wire controller, and prolong the service life of the EEPROM of the air conditioner wire controller, thereby reducing the cost of the air conditioner wire controller.

In a first aspect, an embodiment of the present application provides an air conditioner wire controller circuit, including:

the control processing chip is provided with a first GPIO port and a second GPIO port;

the touch key unit is electrically connected with the control processing chip through a T_SDA interface and a T_SCL interface;

the indicator lamp unit is electrically connected with the control processing chip through a preset interface;

the WIFI unit is electrically connected with the control processing chip through a W_RXD interface and a W_TXD interface;

the infrared remote control receiving circuit is electrically connected with the control processing chip through an REC interface;

the EEPROM storage unit is electrically connected with the control processing chip through an E_SDA interface and an E_SCL interface;

the indoor unit communication unit is electrically connected with the control processing chip through an RXD interface and a TXD interface;

the power-down detection unit is electrically connected with the first GPIO port and the second GPIO port;

the power supply circuit unit is electrically connected with the control processing chip and the power failure detection unit respectively;

the clock management unit comprises a high-speed clock module and a low-speed clock module, and the control processing chip is respectively and electrically connected with the high-speed clock module and the low-speed clock module;

the power management unit is electrically connected with the power supply circuit unit and the control processing chip respectively;

when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface and the TXD interface all output low levels, the control processing chip is connected to the low-speed clock module, and the e_sda interface and the e_scl interface keep the input unchanged.

In some embodiments, the power failure detection unit includes an isolation optocoupler, a first resistor and a second resistor, wherein a first pin of the isolation optocoupler is electrically connected with the first resistor, a second pin and a fourth pin of the isolation optocoupler are grounded, and the second resistor is electrically connected with a third pin of the isolation optocoupler, a first VDD power supply voltage and the first GPIO port, respectively.

In some embodiments, the power failure detection unit further includes a third resistor, a first capacitor, and a reverse diode, where an anode of the reverse diode is grounded, a cathode of the reverse diode is electrically connected to the first pin of the isolation optocoupler, one end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to the first pin of the isolation optocoupler, one end of the third resistor is grounded, and the other end of the third resistor is electrically connected to the first pin of the isolation optocoupler.

In some embodiments, the power failure detection unit further includes a first schottky diode, an anode of the first schottky diode being electrically connected to the first resistor, and a fourth resistor being electrically connected to a cathode of the first schottky diode and the second GPIO port, respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level.

In some embodiments, the power supply circuit unit includes a first power supply circuit and a second capacitor, the second VDD power supply voltage is electrically connected to the first power supply circuit and the second capacitor, respectively, the first power supply circuit includes a second schottky diode and a fifth resistor, and the fifth resistor is electrically connected to a cathode of the second schottky diode and the second VDD power supply voltage, respectively.

In some embodiments, the power supply circuit unit further includes a second power supply circuit including a third schottky diode, a fourth schottky diode, a sixth resistor and a third capacitor, the sixth resistor is electrically connected to an anode of the third schottky diode, a cathode of the third capacitor is grounded, an anode of the third capacitor is electrically connected to a cathode of the third schottky diode and an anode of the fourth schottky diode, respectively, and a cathode of the fourth schottky diode is electrically connected to the second VDD power supply voltage.

In a second aspect, an embodiment of the present application provides a control method based on an air conditioner wire controller circuit, which is applied to the air conditioner wire controller circuit of the embodiment of the first aspect, where the power management unit includes a triode, and the method includes:

when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the triode is closed;

controlling the preset interface to output a high level;

controlling the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output low level;

disconnecting the high-speed clock module and switching on the low-speed clock module;

and controlling the E_SDA interface and the E_SCL interface to keep the input unchanged.

In some embodiments, the EEPROM memory unit includes a first data area, a second data area, and a third data area, the first data area storing first data, the second data area storing second data, the third data area storing third data, wherein the first data area is an active data area, the method comprising:

and synchronizing the second data and the third data to the first data when the first GPIO port outputs a high level and the second GPIO port outputs a low level.

In some embodiments, after said synchronizing said second data and said third data to said first data, said method further comprises:

and when the first GPIO port outputs a low level and the second GPIO port outputs a high level, determining target data from the first data, the second data and the third data, wherein the target data comprises first target data and second target data with the same data, and determining a data area corresponding to the first target data or a data area corresponding to the second target data as a current active data area.

In some embodiments, after said synchronizing said second data and said third data to said first data, said method further comprises:

switching on the high-speed clock module and switching off the low-speed clock module;

starting the triode, controlling the first GPIO port to output a low level, and controlling the second GPIO port to output a high level;

controlling the preset interface to output a low level;

controlling the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output high level;

and controlling the E_SDA interface and the E_SCL interface to keep the input unchanged.

The embodiment of the application discloses an air conditioner wire controller circuit and a control method thereof, wherein the air conditioner wire controller circuit comprises: the control processing chip is provided with a first GPIO port and a second GPIO port; the touch key unit is electrically connected with the control processing chip through a T_SDA interface and a T_SCL interface; the indicator lamp unit is electrically connected with the control processing chip through a preset interface; the WIFI unit is electrically connected with the control processing chip through a W_RXD interface and a W_TXD interface; the infrared remote control receiving circuit is electrically connected with the control processing chip through an REC interface; the EEPROM storage unit is electrically connected with the control processing chip through an E_SDA interface and an E_SCL interface; the indoor unit communication unit is electrically connected with the control processing chip through an RXD interface and a TXD interface; the power-down detection unit is electrically connected with the first GPIO port and the second GPIO port; the power supply circuit unit is electrically connected with the control processing chip and the power failure detection unit respectively; the clock management unit comprises a high-speed clock module and a low-speed clock module, and the control processing chip is respectively and electrically connected with the high-speed clock module and the low-speed clock module; the power management unit is electrically connected with the power supply circuit unit and the control processing chip respectively; when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface and the TXD interface all output low levels, the control processing chip is connected to the low-speed clock module, and the e_sda interface and the e_scl interface keep the input unchanged. The control processing chip of the application combines the power failure detection unit and the power management unit to execute a corresponding power management strategy, so that under the condition that the first GPIO port outputs a high level and the second GPIO port outputs a low level, namely when entering a power failure mode, the input of an EEPROM storage unit interface can be kept unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wire controller, prolonging the service life of the EEPROM of the air conditioner wire controller and reducing the cost of the air conditioner wire controller.

Drawings

Fig. 1 is a circuit configuration diagram of an air conditioner wire controller circuit according to an embodiment of the present application;

FIG. 2 is a flow chart of steps of a control method based on an air conditioner wire controller circuit according to another embodiment of the present application;

FIG. 3 is a flow chart of steps of a data retention method according to another embodiment of the present application;

FIG. 4 is a flow chart of steps of a data retention method according to another embodiment of the present application;

fig. 5 is a flowchart of a step of an incoming call resetting method based on an air conditioner wire controller circuit according to another embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

It will be appreciated that although functional block diagrams are depicted in the device diagrams, logical sequences are shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the block diagrams in the device. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The application provides an air conditioner wire controller circuit and a control method thereof, wherein the air conditioner wire controller circuit comprises: the control processing chip is provided with a first GPIO port and a second GPIO port; the touch key unit is electrically connected with the control processing chip through a T_SDA interface and a T_SCL interface; the indicator lamp unit is electrically connected with the control processing chip through a preset interface; the WIFI unit is electrically connected with the control processing chip through a W_RXD interface and a W_TXD interface; the infrared remote control receiving circuit is electrically connected with the control processing chip through an REC interface; the EEPROM storage unit is electrically connected with the control processing chip through an E_SDA interface and an E_SCL interface; the indoor unit communication unit is electrically connected with the control processing chip through an RXD interface and a TXD interface; the power-down detection unit is electrically connected with the first GPIO port and the second GPIO port; the power supply circuit unit is electrically connected with the control processing chip and the power failure detection unit respectively; the clock management unit comprises a high-speed clock module and a low-speed clock module, and the control processing chip is respectively and electrically connected with the high-speed clock module and the low-speed clock module; the power management unit is electrically connected with the power supply circuit unit and the control processing chip respectively; when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface and the TXD interface all output low levels, the control processing chip is connected to the low-speed clock module, and the e_sda interface and the e_scl interface keep the input unchanged. The control processing chip of the application combines the power failure detection unit and the power management unit to execute a corresponding power management strategy, so that under the condition that the first GPIO port outputs a high level and the second GPIO port outputs a low level, namely when entering a power failure mode, the input of an EEPROM storage unit interface can be kept unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wire controller, prolonging the service life of the EEPROM of the air conditioner wire controller and reducing the cost of the air conditioner wire controller.

Embodiments of the present application will be further described below with reference to the accompanying drawings.

As shown in fig. 1, fig. 1 is a circuit configuration diagram of an air conditioner wire controller circuit according to an embodiment of the present application, and the embodiment of the present application provides an air conditioner wire controller circuit, including:

a control processing chip 101 provided with a first GPIO port and a second GPIO port;

the touch key unit 102 is electrically connected with the control processing chip 101 through a T_SDA interface and a T_SCL interface;

the indicator light unit 103 is electrically connected with the control processing chip 101 through a preset interface;

the WIFI unit 104 is electrically connected with the control processing chip 101 through a W_RXD interface and a W_TXD interface;

the infrared remote control receiving circuit 105 is electrically connected with the control processing chip 101 through an REC interface;

the EEPROM storage unit 106 is electrically connected with the control processing chip 101 through an E_SDA interface and an E_SCL interface;

the indoor unit communication unit 107 is electrically connected with the control processing chip 101 through an RXD interface and a TXD interface;

the power-down detection unit 108 is electrically connected with the first GPIO port and the second GPIO port;

a power supply circuit unit 109, the power supply circuit unit 109 being electrically connected to the control processing chip 101 and the power-down detection unit 108, respectively;

the clock management unit comprises a high-speed clock module and a low-speed clock module, and the control processing chip 101 is respectively and electrically connected with the high-speed clock module and the low-speed clock module;

a power management unit 110, the power management unit 110 being electrically connected to the power supply circuit unit 109 and the control processing chip 101, respectively;

when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface, and the TXD interface all output low levels, the control processing chip 101 switches on the low-speed clock module, and the e_sda interface and the e_scl interface remain unchanged in input.

It can be understood that the air conditioner wire controller circuit of the embodiment of the present application includes a control processing chip 101 provided with a first GPIO port and a second GPIO port; the touch key unit 102, the WIFI unit 104, the infrared remote control receiving circuit 105, the EEPROM storage unit 106, the indoor unit communication unit 107, the power failure detection unit 108, the power supply circuit unit 109, the clock management unit and the power management unit 110 are electrically connected with the control processing chip 101, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the control processing chip 101 conducts the low-speed clock module of the clock management unit, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface and the TXD interface output low levels, that is, the functional modules of the touch key unit 102, the WIFI unit 104, the infrared remote control receiving circuit 105, the indoor unit communication unit 107 and the like stop running, and the EEPROM storage unit 106 keeps the input unchanged. According to the scheme of the application, when the air conditioner wire controller circuit enters the power-down mode, the corresponding power management strategy can be executed based on the control processing chip 101 and combined with the power-down detection unit 108 and the power management unit 110, so that the communication among all module units in the air conditioner wire controller circuit is improved, the interface input of the EEPROM storage unit 106 is kept unchanged, the autonomous processing capacity of the module units can be remarkably reduced, the energy consumption of the EEPROM of the air conditioner wire controller is reduced, the service life of the EEPROM of the air conditioner wire controller is prolonged, and the cost of the air conditioner wire controller is reduced.

It should be noted that, the air conditioner wire controller circuit of the embodiment of the present application may further include functional modules such as an LCD display management unit, a backlight unit 111, and a buzzer unit 112, and referring to fig. 1, the backlight unit 111 is electrically connected to the control processing chip 101 through a BL interface, and the buzzer unit 112 is electrically connected to the control processing chip 101 through a BUZZ interface.

In some embodiments, to further reduce energy consumption and maintain the display of the power-down mode, the LCD display management unit updates information such as a system clock, a calendar, a cycle time, an air conditioner running state, etc. at intervals of 100ms when the air conditioner drive-by-wire circuit is in the normal mode based on the system auxiliary clock, and displays the data refreshed by the dynamic video memory through the LCD; under the condition that the air conditioner wire controller circuit is in a power-down mode, the system clock, the calendar and the peripheral clock are updated in a flashing mode every 0.5 seconds, and information such as the running state of the air conditioner is kept to be displayed.

In some embodiments, the clock management unit is based on a system secondary clock, and the clock management unit continues to operate under the condition that the air conditioner wire controller circuit is in a power-down mode, and performs second timing increment, minute increment, hour increment, week increment, year, month and day increment after each 0.5s wake-up.

In addition, in some embodiments, the power failure detection unit 108 includes an isolation optocoupler U102, a first resistor R103, and a second resistor R104, where a first pin of the isolation optocoupler U102 is electrically connected to the first resistor R103, a second pin and a fourth pin of the isolation optocoupler U102 are grounded, and the second resistor R104 is electrically connected to a third pin of the isolation optocoupler U102, a first VDD power supply voltage, and a first GPIO port, respectively.

It can be understood that when the air conditioner is powered on and the power is stable, the air conditioner bus outputs power to provide stable power for the 86-box wire controller (i.e. the wire controller corresponding to the air conditioner wire controller circuit in this embodiment), the first pin of the isolation optocoupler U102 in the power failure detection unit 108 of the air conditioner wire controller circuit is electrically connected with the first resistor R103, the second pin of the isolation optocoupler U102 is grounded, and the second resistor R104 is electrically connected with the third pin of the isolation optocoupler U102, the first VDD power voltage (i.e. the bus power voltage) and the first GPIO port, respectively; when the bus power supply voltage VDD is +5v, it can be seen that the input working current value is within the range of 25mA, the input voltage drop is 1V-1.3V at 10mA, and the resistance at the input end can reach a better working state when the input resistor is about 10mA during conduction, so that the values of the input resistor and the first resistor R103 are as follows: r103= (5V-1.2V)/10ma=38Ω, one end of the second resistor R104 is connected with the power supply voltage VDD, and the other end of the second resistor R104 is connected with the first GPIO port; when the bus power supply is normal, the diode of the isolation optocoupler U102 is conducted, the diode emits light, the third pin and the fourth pin of the isolation optocoupler U102 are conducted, the second resistor R104 is provided with current to pass, and at the moment, the isolation optocoupler U102 reaches a saturated state; when the first GPIO port of the control processing chip 101 detects a low level, the current bus power supply is in a normal state; otherwise, when the bus power supply is powered down or abnormal, the diode of the isolation optocoupler U102 cannot provide normal on voltage, the diode does not emit light, the output end is cut off, and the first GPIO port detects a high level.

In addition, in some embodiments, the power failure detection unit 108 further includes a third resistor R106, a first capacitor C103, and a reverse diode D105, where an anode of the reverse diode D105 is grounded, a cathode of the reverse diode D105 is electrically connected to the first pin of the isolation optocoupler U102, one end of the first capacitor C103 is grounded, the other end of the first capacitor C103 is electrically connected to the first pin of the isolation optocoupler U102, one end of the third resistor R106 is grounded, and the other end of the third resistor R106 is electrically connected to the first pin of the isolation optocoupler U102.

It can be understood that, in order to ensure the reliability of the line controller during power failure detection, the power failure detection unit 108 adds a third resistor R106, a first capacitor C103 and a reverse diode D105 at the input end of the bus, the anode of the reverse diode D105 is grounded, the cathode of the reverse diode D105 is electrically connected with the first pin of the isolation optocoupler U102, one end of the first capacitor C103 is grounded, the other end of the first capacitor C103 is electrically connected with the first pin of the isolation optocoupler U102, one end of the third resistor R106 is grounded, the other end of the third resistor R106 is electrically connected with the first pin of the isolation optocoupler U102, the reverse diode D105 is used for preventing the reverse connection of an input signal, avoiding the reverse withstand voltage of the input exceeding 5V and damaging the diode inside the isolation optocoupler U102, and accessing the reverse diode D105 to realize reverse voltage input, and ensuring the normal reverse voltage limit within 1V. The first capacitor C103 is used for filtering, and if the input signal has high-frequency interference, the parallel capacitor and the series current limiting resistor form an RC low-pass filter effect to filter the interference with higher frequency. The third resistor R106 can remove some interference from the bus external serial connection, so that the isolation optocoupler U102 is not conducted by the lower-voltage interference signal input, the error detection of the bus electric power restoration is avoided, the frequent awakening of the control processing chip 101 is reduced, the electric quantity of the backup power supply is consumed, and the service time of the extension line controller is prolonged; on the other hand, the third resistor R106 can accelerate the discharging time of the first capacitor C103, so that after the bus power fails, the output end can immediately make a judgment, and execute a preset power management policy.

In addition, in some embodiments, the power failure detection unit 108 further includes a first schottky diode D104 and a fourth resistor R105, where an anode of the first schottky diode D104 is electrically connected to the first resistor R103, and the fourth resistor R105 is electrically connected to a cathode of the first schottky diode D104 and the second GPIO port, respectively, where the second GPIO port outputs a low level when the first GPIO port outputs a high level.

It can be understood that, in order to ensure that the environment is detected correctly, the power-down detection unit 108 further adds a first schottky diode D104 and a fourth resistor R105 at the bus input end, the anode of the first schottky diode D104 is electrically connected with the first resistor R103, and the fourth resistor R105 is electrically connected with the cathode of the first schottky diode D104 and the second GPIO port respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level; since the first schottky diode D104 is connected to the fourth resistor R105, the fourth resistor R105 can perform dual detection with the second GPIO interface of the control processing chip 101, so as to ensure that the power-down detection signal detected by the second GPIO interface corresponds to a high level and is in a power-down state.

In addition, in some embodiments, the power supply circuit unit 109 includes a first power supply circuit and a second capacitor C102, the second VDD power supply voltage is electrically connected to the first power supply circuit and the second capacitor C102, respectively, the first power supply circuit includes a second schottky diode D101 and a fifth resistor R102, and the fifth resistor R102 is electrically connected to the cathode of the second schottky diode D101 and the second VDD power supply voltage, respectively.

It can be understood that, based on the structure of this embodiment, when the 86-box wire controller works normally, the bus power supply voltage +5v passes through the second schottky diode D101, the resistance value of the fifth resistor R102 is set to 18 ohms, the fifth resistor R102 is electrically connected with the second capacitor C102, and the first power supply circuit supplies power to the control processing chip 101 and the functional modules such as the LCD display management unit, the indoor unit communication unit 107, the WIFI unit 104, and the like; the second schottky diode D101 functions to prevent the first power supply circuit from reversely supplying power to the bus circuit and the external device; the resistance value of the fifth resistor R102 is set to be 18 ohms, current limiting protection is achieved on bus output, and the situation that the current is too large and a three-terminal power supply voltage stabilizing device is damaged when the 86 and the WIFI unit 104 of the line controller, the touch key unit 102 and other functional modules are simultaneously started is effectively avoided.

In addition, in some embodiments, the power supply circuit unit 109 further includes a second power supply circuit including a third schottky diode D102, a fourth schottky diode D103, a sixth resistor R101, and a third capacitor C101, the sixth resistor R101 is electrically connected to the anode of the third schottky diode D102, the cathode of the third capacitor C101 is grounded, the anode of the third capacitor C101 is electrically connected to the cathode of the third schottky diode D102 and the anode of the fourth schottky diode D103, respectively, and the cathode of the fourth schottky diode D103 is electrically connected to the second VDD power supply voltage.

It can be understood that the bus power supply voltage is outside the normal power supply to the wire controller assembly, and simultaneously, the second power supply circuit stores energy for the third capacitor C101 through the sixth resistor R101 and the third schottky diode D102, and the third capacitor C101 supplies power to the second VDD power supply voltage through the fourth schottky diode D103. The third schottky diode D102 functions to prevent the second power supply circuit from reversely supplying power to the bus circuit and the external device; the fourth schottky diode D103 is used to prevent the second power supply circuit from accumulating excessive current in unidirectional energy, and to borrow power from the first power supply circuit and the power supply device of the external device, and delay the reset time sequence to cause the dislocation and the asynchronization. The sixth resistor R101 can improve the charging surge when the second power supply circuit performs unidirectional energy storage on the third capacitor C101, and causes the second secondary pollution to the bus power supply.

In addition, referring to fig. 2 and 1, an embodiment of the present application further provides a control method based on an air conditioner wire controller circuit, which is applied to the air conditioner wire controller circuit described in the above embodiment, and the power management unit 110 includes a transistor Q101, and the control method includes, but is not limited to, the following steps:

step S110, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the triode Q101 is turned off;

step S120, controlling a preset interface to output a high level;

step S130, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface are controlled to output low level;

step S140, disconnecting the high-speed clock module and conducting the low-speed clock module;

in step S150, the e_sda interface and the e_scl interface are controlled to keep the inputs unchanged.

It can be understood that when the bus power supply is normal, the 86-box wire controller starts to work, and the triode Q101 is started, so that the VCC power supply of the functional modules such as the indoor unit communication unit 107, the WIFI unit 104, the infrared wireless remote control receiving circuit and the like is started, and all circuit components enter normal work after being initialized; when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the air conditioner wire controller circuit enters a power down mode, and the control processing chip 101 executes a power management strategy, specifically as follows: the triode Q101 is turned off, and the emitter of the triode Q101 is electrically connected with the VCC power supply voltage, so that the VCC power supply voltage can be cut off by the triode Q101; the preset interface is controlled to output high level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface are controlled to output low level, the high-speed clock module is disconnected, the low-speed clock module is conducted, the E_SDA interface and the E_SCL interface are controlled to keep unchanged input, that is, when the air conditioner wire controller circuit enters a power down mode, the corresponding power management strategy can be executed by combining the power down detection unit 108 and the power management unit 110 based on the control processing chip 101, communication among all module units in the air conditioner wire controller circuit is improved, the input of the EEPROM storage unit 106 is kept unchanged, so that the autonomous processing capacity of the module units can be remarkably reduced, the power consumption of the EEPROM of the air conditioner wire controller is reduced, the service life of the EEPROM of the air conditioner wire controller is prolonged, and the cost of the air conditioner wire controller is reduced.

In some embodiments, referring to fig. 3, the eeprom storage unit 106 includes a first data area, a second data area and a third data area, where the first data area stores first data, the second data area stores second data, and the third data area stores third data, and the first data area is an active data area, and the control method based on the air conditioner wire controller circuit according to the embodiment of the present application further includes, but is not limited to, the following steps:

in step S210, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized into the first data.

Referring to fig. 4, in some embodiments, after performing step S210 in the embodiment shown in fig. 3, the control method based on the air conditioner wire controller circuit according to the embodiment of the present application further includes, but is not limited to, the following steps:

in step S310, when the first GPIO port outputs a low level and the second GPIO port outputs a high level, the target data is determined from the first data, the second data and the third data, the target data includes the first target data and the second target data with the same data, and the data area corresponding to the first target data or the data area corresponding to the second target data is determined as the current active data area.

It can be appreciated that the EEPROM storage unit 106 of the line controller may include a first data area, a second data area and a third data area, where when the line controller circuit is powered on and operates normally, the first data area stores working data, and is an active data area, and the second data area and the third data area are inactive data areas; when the line controller circuit is powered down, namely when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized into first data, and at the moment, the second data area and the third data area are used as backup data areas of the first data area; after that, when the first GPIO port outputs a low level from a high level change and the second GPIO port outputs a high level from a level change, that is, in the case of an incoming call reset, data is read from the first data area, the second data area and the third data area, the first data, the second data and the third data are compared, target data are determined from the first data, the second data and the third data, the target data comprise the first target data and the second target data which are identical in data, the data area corresponding to the first target data or the data area corresponding to the second target data is determined as a current active data area, that is, 2 data areas with identical storage data are screened as new candidate active data areas, and a new target active area is randomly determined from the 2 new candidate active data areas, so that data retention management based on the EEPROM memory unit 106 is realized. In some embodiments, when the first data, the second data, and the third data are different from each other, i.e., in an initialized state, initial value data is used as the target data, and the first data area, the second data area, and the third data area are all inactive areas.

In addition, referring to fig. 5, in some embodiments, after performing step S210 in the embodiment shown in fig. 3, the control method based on the air conditioner wire controller circuit according to the embodiment of the present application further includes, but is not limited to, the following steps:

step S410, a high-speed clock module is conducted, and a low-speed clock module is disconnected;

step S420, turn on triode Q101, control the first GPIO port to output low level, and control the second GPIO port to output high level;

step S430, controlling a preset interface to output a low level;

step S440, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface are controlled to output high level;

in step S450, the e_sda interface and the e_scl interface are controlled to keep the inputs unchanged.

It will be appreciated that after the 86-box line controller is in the power-down mode, the bus power supply voltage detects that the first GPIO interface changes from the output high level to the low level, generating a falling edge signal interrupt, and the dual detection interface, i.e. the second GPIO interface, detects the high level, the line controller determines that the external bus is powered back up, and the power management unit 110 performs the reset action as follows: the high-speed clock module is conducted, the low-speed clock module is disconnected, the triode Q101 is started, the first GPIO port is controlled to output a low level, the second GPIO port is controlled to output a high level, the preset interface is controlled to output a low level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface are controlled to output high levels, the E_SDA interface and the E_SCL interface are controlled to keep the input unchanged, and therefore the wire controller returns to a normal mode from a power-down mode, and functional modules such as the indoor unit communication unit 107, the WIFI unit 104 and the infrared wireless remote control receiving circuit continue to work based on working data before power failure.

Claims (10)

1. An air conditioner wire controller circuit, comprising:

the control processing chip is provided with a first GPIO port and a second GPIO port;

the touch key unit is electrically connected with the control processing chip through a T_SDA interface and a T_SCL interface;

the indicator lamp unit is electrically connected with the control processing chip through a preset interface;

the WIFI unit is electrically connected with the control processing chip through a W_RXD interface and a W_TXD interface;

the infrared remote control receiving circuit is electrically connected with the control processing chip through an REC interface;

the EEPROM storage unit is electrically connected with the control processing chip through an E_SDA interface and an E_SCL interface;

the indoor unit communication unit is electrically connected with the control processing chip through an RXD interface and a TXD interface;

the power-down detection unit is electrically connected with the first GPIO port and the second GPIO port;

the power supply circuit unit is electrically connected with the control processing chip and the power failure detection unit respectively;

the clock management unit comprises a high-speed clock module and a low-speed clock module, and the control processing chip is respectively and electrically connected with the high-speed clock module and the low-speed clock module;

the power management unit is electrically connected with the power supply circuit unit and the control processing chip respectively;

when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the t_sda interface, the t_scl interface, the w_rxd interface, the w_txd interface, the REC interface, the RXD interface and the TXD interface all output low levels, the control processing chip is connected to the low-speed clock module, and the e_sda interface and the e_scl interface keep the input unchanged.

2. The air conditioner wire controller circuit of claim 1, wherein the power down detection unit comprises an isolation optocoupler, a first resistor and a second resistor, wherein a first pin of the isolation optocoupler is electrically connected with the first resistor, a second pin and a fourth pin of the isolation optocoupler are grounded, and the second resistor is electrically connected with a third pin of the isolation optocoupler, a first VDD supply voltage and the first GPIO port, respectively.

3. The air conditioner wire controller circuit according to claim 2, wherein the power failure detection unit further comprises a third resistor, a first capacitor and a reverse diode, wherein an anode of the reverse diode is grounded, a cathode of the reverse diode is electrically connected with a first pin of the isolation optocoupler, one end of the first capacitor is grounded, the other end of the first capacitor is electrically connected with the first pin of the isolation optocoupler, one end of the third resistor is grounded, and the other end of the third resistor is electrically connected with the first pin of the isolation optocoupler.

4. The air conditioner wire controller circuit of claim 3 wherein the power down detection unit further comprises a first schottky diode and a fourth resistor, the anode of the first schottky diode being electrically connected to the first resistor, the fourth resistor being electrically connected to the cathode of the first schottky diode and the second GPIO port, respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level.

5. The air conditioner wire controller circuit of claim 1 wherein the power circuit unit comprises a first power circuit and a second capacitor, a second VDD supply voltage is electrically connected to the first power circuit and the second capacitor, respectively, the first power circuit comprises a second schottky diode and a fifth resistor, the fifth resistor is electrically connected to a cathode of the second schottky diode and the second VDD supply voltage, respectively.

6. The air conditioner wire controller circuit according to claim 5, wherein the power supply circuit unit further comprises a second power supply circuit comprising a third schottky diode, a fourth schottky diode, a sixth resistor and a third capacitor, the sixth resistor is electrically connected to the anode of the third schottky diode, the cathode of the third capacitor is grounded, the anode of the third capacitor is electrically connected to the cathode of the third schottky diode and the anode of the fourth schottky diode, respectively, and the cathode of the fourth schottky diode is electrically connected to the second VDD power supply voltage.

7. A control method based on an air conditioner wire controller circuit, wherein the power management unit includes a triode, and the method includes:

when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the triode is closed;

controlling the preset interface to output a high level;

controlling the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output low level;

disconnecting the high-speed clock module and switching on the low-speed clock module;

and controlling the E_SDA interface and the E_SCL interface to keep the input unchanged.

8. The control method based on an air conditioner wire controller circuit according to claim 7, wherein the EEPROM storage unit includes a first data area, a second data area, and a third data area, the first data area stores first data, the second data area stores second data, and the third data area stores third data, wherein the first data area is an active data area, the method comprising:

and synchronizing the second data and the third data to the first data when the first GPIO port outputs a high level and the second GPIO port outputs a low level.

9. The air conditioner-based control method according to claim 8, wherein after the synchronizing the second data and the third data into the first data, the method further comprises:

and when the first GPIO port outputs a low level and the second GPIO port outputs a high level, determining target data from the first data, the second data and the third data, wherein the target data comprises first target data and second target data with the same data, and determining a data area corresponding to the first target data or a data area corresponding to the second target data as a current active data area.

10. The air conditioner-based control method according to claim 8, wherein after the synchronizing the second data and the third data into the first data, the method further comprises:

switching on the high-speed clock module and switching off the low-speed clock module;

starting the triode, controlling the first GPIO port to output a low level, and controlling the second GPIO port to output a high level;

controlling the preset interface to output a low level;

controlling the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output high level;

and controlling the E_SDA interface and the E_SCL interface to keep the input unchanged.