CN116701275B - Terminal equipment expansion equipment, method and device and bus standard equipment - Google Patents
Terminal equipment expansion equipment, method and device and bus standard equipment Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
本发明公开了一种终端设备扩展设备、方法、装置及总线标准设备，属于PCIe设备领域，用于扩充基于FPGA实现的单个PCIe设备支持连接的终端设备的数量，解决了基于FPGA实现的单个PCIe设备支持连接的终端设备数量较少的问题。可以控制FPGA的IP核处于桥接模式下，并在连接于IP核的控制器内部设定了控制器可支持功能模块端口的预设数量，如此一来，在PCIe设备初始化阶段，主机便可以扫描控制器所支持的预设数量个功能模块端口并完成PCIe设备的拓扑初始化，由于预设数量可自主改动，从而使得单个PCIe设备可提供大量的功能模块端口数量，从而可以连接大量的终端设备，满足了用户需求，提升了用户体验。
The invention discloses a terminal equipment expansion equipment, method, device and bus standard equipment, which belongs to the field of PCIe equipment and is used to expand the number of terminal equipment supported by a single PCIe equipment implemented based on FPGA, and solve the problem of a single PCIe equipment implemented based on FPGA. The device supports the problem of a small number of connected terminal devices. The IP core that can control the FPGA is in bridge mode, and the preset number of functional module ports that the controller can support is set inside the controller connected to the IP core. In this way, during the initialization phase of the PCIe device, the host can scan The controller supports a preset number of functional module ports and completes the topology initialization of the PCIe device. Since the preset number can be changed independently, a single PCIe device can provide a large number of functional module ports and can connect a large number of terminal devices. Meets user needs and improves user experience.
Description
Technical Field
The invention relates to the field of PCIe equipment, in particular to terminal equipment expansion equipment, and further relates to a terminal equipment expansion method, a terminal equipment expansion device, high-speed serial computer expansion bus standard equipment, a server and a computer readable storage medium.
Background
When implementing PCIe (Peripheral Component Interconnect express, high-speed serial computer expansion bus standard) devices using FPGA (Field Programmable Gate Array ), an IP (Intellectual Property, intellectual property) core in the FPGA is generally used as a core of the PCIe device, however, the number of EPs (End Point) that can be supported by the PCIe device is limited by the IP core in the FPGA, that is, the number of ports for connecting EPs provided by the IP core cannot be modified, so that only a small number of terminal devices can be implemented in one PCIe device based on FPGA design at present, which is difficult to satisfy user requirements and reduces user experience.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention aims to provide terminal equipment expansion equipment, and the preset number in a controller can be changed automatically, so that a single PCIe equipment can provide a large number of functional module ports, a large number of terminal equipment can be connected, the user requirements are met, and the user experience is improved; another object of the present invention is to provide a method and apparatus for expanding a terminal device, a high-speed serial computer expansion bus standard device, a server, and a computer readable storage medium, in which a preset number in a controller can be changed autonomously, so that a single PCIe device can provide a large number of ports of functional modules, and thus a large number of terminal devices can be connected, thereby meeting user requirements and improving user experience.
In order to solve the above technical problems, the present invention provides a terminal device extension device, including:
the controller is connected with the intellectual property core of the high-speed serial computer expansion bus standard equipment and is used for responding to a port scanning request sent by a host through the intellectual property core in the initialization stage of the high-speed serial computer expansion bus standard equipment so that the host can complete scanning of a preset number of function module ports supported by the controller and topology initialization work of the high-speed serial computer expansion bus standard equipment; the method is also used for storing initialization data generated in the topology initialization process, which is sent by the host through the intellectual property core, to pre-stored port configuration data;
the first end is connected with the intellectual property core, the second end is connected with the controller, and the third end is connected with each functional module of the high-speed serial computer expansion bus standard equipment, and is used for realizing data communication between the intellectual property core and the controller and between the intellectual property core and the functional modules;
the intellectual property cores are intellectual property cores in a field programmable gate array, the intellectual property cores are in a bridge mode, and the upper limit of the preset number is the total amount of bus resources specified by a high-speed serial computer expansion bus standard.
In another aspect, the signal transmission module includes:
a first end is connected with the intellectual property core, a second end is connected with the controller, a third end is connected with each functional module of the high-speed serial computer expansion bus standard equipment, and a first signal transmission sub-module is used for sending a request sent by the intellectual property core to the controller or the designated functional module and sending response data of the controller and the functional module for the intellectual property core to the intellectual property core;
the first end is connected with the intellectual property core, the second end is connected with the second signal transmission sub-module of the controller, and is used for sending the request sent by the functional module to the intellectual property core, and sending the response signal sent by the intellectual property core to the request sent by the functional module to the appointed functional module.
On the other hand, the terminal equipment expansion equipment is arranged in a field programmable gate array where the high-speed serial computer expansion bus standard equipment is located.
In another aspect, the controller includes a first controller core and a first memory module;
the first controller core is configured to communicate with the first signal transmission submodule through a flow-oriented advanced expansion bus interface of the first controller core, respond to a port scanning request sent by a host through the intellectual property core in an initialization stage of the high-speed serial computer expansion bus standard device, and store initialization data generated in the topology initialization process and sent by the host through the intellectual property core into pre-stored port configuration data;
The first storage module is used for storing data.
In another aspect, the controller further comprises:
and the first signal connection module is connected with the first controller core and is used for generating a plurality of signal interfaces of specified types based on the simplified advanced expansion bus interface of the first controller core.
In another aspect, the first signal connection module includes a first port expansion module and a first port conversion module;
the first port expansion module is configured to expand the simplified advanced expansion bus interface of the first controller core into a plurality of simplified advanced expansion bus interfaces;
the first port conversion module is configured to convert a single simplified advanced expansion bus interface provided by the first port expansion module into a signal interface of a target type;
wherein the target type includes a universal input output interface and a serial interface.
On the other hand, the controller comprises a second controller inner core, a second storage module and a signal switching module;
the second controller core is configured to communicate with the advanced expansion bus interface of the first signal transmission sub-module, which faces the flow, under the cooperation of the client instruction interface and the signal switching module, and respond to a port scanning request sent by the host through the intellectual property core in an initialization stage of the high-speed serial computer expansion bus standard device, and store initialization data generated in the topology initialization process and sent by the host through the intellectual property core to pre-stored port configuration data;
The second storage module is used for storing data;
the signal transfer module is configured to send data of the client instruction interface of the second controller core to the stream-oriented advanced expansion bus interface of the first signal transmission sub-module according to a status signal of the stream-oriented advanced expansion bus interface of the first signal transmission sub-module, and cache the data sent by the stream-oriented advanced expansion bus interface of the first signal transmission sub-module, so that the second controller core reads the cached data through the client instruction interface.
In another aspect, the controller further comprises:
and the second signal connection module is connected with the second controller core and is used for generating a plurality of signal interfaces of specified types based on the advanced expansion bus interface of the second controller core.
On the other hand, the second signal connection module comprises a second port expansion module and a second port conversion module;
the second port expansion module is configured to expand the simplified advanced expansion bus interface of the second controller core into a plurality of ports;
the second port conversion module is configured to convert a single simplified advanced expansion bus interface provided by the second port expansion module into a signal interface of a target type;
Wherein the target type includes a universal input output interface and a serial interface.
In another aspect, the controller is further configured to:
and responding to a modification instruction sent by the host through the intellectual property core, and modifying the port configuration data and/or the preset quantity.
In another aspect, the terminal device extension device further includes:
and the man-machine interaction module is connected with the controller and used for changing the port configuration data and/or the preset quantity in the controller.
In another aspect, the first signal transmission sub-module is further configured to:
and determining a base address register space number to which the request of the intellectual property core sent to the specified functional module belongs, and binding and sending the base address register space number and the corresponding request to the specified functional module.
In another aspect, the controller is further configured to, in an initialization stage of the high-speed serial computer expansion bus standard device, initialize interrupt data pre-stored in a designated memory in response to an interrupt data initialization instruction sent by the host through an intellectual property core of the high-speed serial computer expansion bus standard device, so that the functional module sends an interrupt request to the host through the interrupt data.
In another aspect, the designated memory is a memory in a field programmable gate array in which the high speed serial computer expansion bus standard device resides.
In order to solve the technical problem, the invention also provides a terminal equipment expansion method, which is applied to a controller and comprises the following steps:
in the initialization stage of the high-speed serial computer expansion bus standard equipment, responding to a port scanning request sent by a host through the intellectual property core, so that the host can complete scanning of a preset number of function module ports supported by the controller and topology initialization work of the high-speed serial computer expansion bus standard equipment;
storing initialization data generated in the topology initialization process and sent by the host through the intellectual property core to pre-stored port configuration data;
the intellectual property core of the high-speed serial computer expansion bus standard device is the intellectual property core in the field programmable gate array, the intellectual property core of the high-speed serial computer expansion bus standard device is in a bridging mode, and the upper limit of the preset number is the total amount of bus resources specified by the high-speed serial computer expansion bus standard.
On the other hand, the terminal equipment expansion method further comprises the following steps:
in the initialization stage of the high-speed serial computer expansion bus standard device, in response to an interrupt data initialization instruction sent by the host through the intellectual property core of the high-speed serial computer expansion bus standard device, initializing interrupt data pre-stored in a designated memory so that the functional module sends an interrupt request to the host through the interrupt data.
In another aspect, the designated memory is a memory in a field programmable gate array in which the high speed serial computer expansion bus standard device resides.
On the other hand, the terminal equipment expansion method further comprises the following steps:
and responding to a modification instruction sent by the host through the intellectual property core, and modifying the port configuration data and/or the preset quantity.
In order to solve the above technical problem, the present invention further provides a terminal device extension apparatus, which is applied to a controller, and includes:
the transmitting module is used for responding to a port scanning request transmitted by the host through the intellectual property core in the initialization stage of the high-speed serial computer expansion bus standard equipment so that the host can complete scanning of a preset number of function module ports supported by the controller and topology initialization work of the high-speed serial computer expansion bus standard equipment;
The storage module is used for storing initialization data generated in the topology initialization process and sent by the host through the intellectual property core to pre-stored port configuration data;
the intellectual property core of the high-speed serial computer expansion bus standard device is the intellectual property core in the field programmable gate array, the intellectual property core of the high-speed serial computer expansion bus standard device is in a bridging mode, and the upper limit of the preset number is the total amount of bus resources specified by the high-speed serial computer expansion bus standard.
In order to solve the technical problem, the invention also provides high-speed serial computer expansion bus standard equipment, which comprises the terminal equipment expansion equipment.
In order to solve the technical problem, the invention also provides a server which comprises the high-speed serial computer expansion bus standard equipment.
To solve the above technical problem, the present invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the terminal device extension method as described above.
The beneficial effects are that: the invention provides terminal equipment extension equipment, which considers that the quantity of the terminal equipment supported by PCIe equipment can be flexibly configured through another controller, and the IP core of the intellectual property of an FPGA can be connected with the other controller in a bridging mode, so that the IP core of the FPGA can be controlled to be in the bridging mode, and the preset quantity of ports of the functional module supported by the controller is set in the controller connected with the IP core.
The invention also provides a terminal equipment expansion method, a device, a high-speed serial computer expansion bus standard equipment, a server and a computer readable storage medium, which have the same beneficial effects as the terminal equipment expansion method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the related art and the drawings required to be used in the embodiments, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of an extension device of a terminal device provided by the present invention;
fig. 2 is a schematic structural diagram of another terminal device expansion device provided by the present invention;
FIG. 3 is a schematic diagram of a controller according to the present invention;
FIG. 4 is a schematic diagram of another controller according to the present invention;
fig. 5 is a schematic flow chart of a terminal device expansion method provided by the invention;
fig. 6 is a schematic structural diagram of an extension device of a terminal device provided by the present invention;
fig. 7 is a schematic structural diagram of a computer readable storage medium according to the present invention.
Detailed Description
The core of the invention is to provide a terminal equipment expansion device, because the preset number in the controller can be changed automatically, a single PCIe device can provide a large number of function module ports, thereby being capable of connecting a large number of terminal equipment, meeting the user demands and improving the user experience; the invention further provides a terminal equipment expansion method, a terminal equipment expansion device, a high-speed serial computer expansion bus standard equipment, a server and a computer readable storage medium, and because the preset number in the controller can be changed automatically, a single PCIe equipment can provide a large number of function module ports, so that a large number of terminal equipment can be connected, the user requirements are met, and the user experience is improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a terminal device extension device provided by the present invention, where the terminal device extension device includes:
the controller 1 is connected with the intellectual property core of the high-speed serial computer expansion bus standard equipment and is used for responding to a port scanning request sent by the host through the intellectual property core in the initialization stage of the high-speed serial computer expansion bus standard equipment so that the host can complete scanning of the ports of the preset number of functional modules supported by the controller 1 and topology initialization work of the high-speed serial computer expansion bus standard equipment; the method is also used for storing initialization data generated in the topology initialization process, which is sent by the host through the intellectual property core, into pre-stored port configuration data;
The first end is connected with the intellectual property core, the second end is connected with the controller 1, and the third end is connected with the signal transmission module 2 of each functional module of the high-speed serial computer expansion bus standard equipment, and the signal transmission module is used for realizing data communication between the intellectual property core and the controller 1 and between the functional modules;
the intellectual property cores are intellectual property cores in the field programmable gate array, the intellectual property cores are in a bridge mode, and the upper limit of the preset quantity is the total quantity of bus resources specified by the expansion bus standard of the high-speed serial computer.
Specifically, considering the technical problems in the background art as above, in combination with considering that the controller 1 outside the IP core of the PCIe device can implement flexible configuration for the number of End devices that can be supported by the PCIe device, and the intellectual property IP core of the FPGA can connect to another controller 1 in the bridge mode, so in the embodiment of the present invention, the IP core of the PCIe device can be controlled to be in the bridge mode, and the controller 1 connected to the IP core of the PCIe device is set, so that support of a large number of function module ports is implemented based on the controller 1, thereby expanding the number of connectable End devices (EP, end Point), and for the IP core, the related parameters inside the controller cannot be changed after leaving the factory, including the number of support of function module ports for the PCIe device, that is, limiting the number of End devices that are connected to the function module ports of the PCIe device, and the controller 1 serves as a bridge device for the PCIe device, where the preset number of supportable function module ports can be set, and the preset number can be flexibly changed, so that the preset number can be set within an upper limit, and the number of autonomously expanding the number of possible End devices for the PCIe device.
The bridge mode may be various types, for example, a bridge mode or a TLP (Transaction Layer Packet ) Bypass mode, which is not limited herein.
Specifically, the terminal device may refer to various functional modules connected to ports of the functional modules, which are implemented at the end in the topology of the PCIe device, and include a PF (Physical Function ) module, a VF (Virtual Function) module, etc., which is not limited herein.
Specifically, the host may scan the EP devices existing on the PCIe bus through the IP core, and based on the preset number set in the controller 1, the controller 1 performs an effective response to the query messages of the existing EP devices, and performs an ineffective response to the query messages exceeding the preset number. Based on the above process, the host completes the topology initialization work of the PCIe device. And the controller 1 can also store related initialization data (mainly related to related data of a function module currently connected with the PCIe device) generated by the host in a topology initialization process in pre-stored port configuration data, so that subsequent calling is facilitated.
The signal transmission module 2 can realize communication between the IP core and the functional module besides communication between the IP core and the controller 1, so that data interaction between the host and the functional module through the IP core is realized.
Specifically, after the PF function in EP is identified by the host, continuing to enable the SR-IOV (Single Root I/O Virtualization) function may increase the support for VF. When the number of VFs needs to be greater than 8, ARI (Alternative Routing-ID, alternative route ID) characteristics of the PCIe device need to be enabled, each PF module obtains a Bus number, and each PF module can enable 255 VF modules at maximum based on the configuration of a user, so that the number of VF modules supported in the PCIe device is also expanded.
Specifically, the preset number may be set autonomously, for example, set to 64, where the upper limit may be the total amount of bus resources specified by the PCIe protocol, and since the total amount of bus resources specified by the PCIe protocol is far greater than the number of ports for connecting to EPs provided by the IP core of the FPGA, the PCIe device may provide a large number of ports for connecting to EPs by flexibly setting the preset number.
The controller 1 may be of various types, for example, may be a single chip microcomputer, etc., and the embodiment of the present invention is not limited herein.
The invention provides terminal equipment extension equipment, which is characterized in that the number of the supported terminal equipment of PCIe equipment can be flexibly configured through another controller 1, and the other controller 1 can be connected with the IP core of the intellectual property of the FPGA in a bridging mode, so that the IP core of the FPGA can be controlled to be in the bridging mode, and the preset number of ports of the supportable functional modules of the controller 1 is set in the controller 1 connected with the IP core, therefore, in the initialization stage of the PCIe equipment, a host can scan the preset number of ports of the functional modules supported by the controller 1 and complete the topology initialization of the PCIe equipment, and because the preset number can be independently changed, a single PCIe equipment can provide a large number of ports of the functional modules, thereby being capable of connecting a large number of terminal equipment, meeting the user requirements and improving the user experience.
Based on the above embodiments:
as an embodiment, the signal transmission module 2 includes:
the first end is connected with the intellectual property core, the second end is connected with the controller 1, the third end is connected with each functional module of the high-speed serial computer expansion bus standard equipment, and the first signal transmission sub-module is used for sending the request sent by the intellectual property core to the controller 1 or the designated functional module, and sending the response data of the controller 1 and the functional module for the request sent by the intellectual property core to the intellectual property core;
the first end is connected with the intellectual property core, and the second end is connected with the second signal transmission sub-module of the controller 1, and is used for sending the request sent by the functional module to the intellectual property core, and sending the response signal sent by the intellectual property core to the request sent by the functional module to the appointed functional module.
For better explaining the embodiments of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of another terminal device expansion device provided by the present invention, where the completer request interface and the completer completion interface in fig. 2 form a first signal transmission sub-module, and the requester request interface and the requester completion interface form a second signal transmission sub-module.
Specifically, the first signal transmission sub-module may be configured to transmit a request actively sent by the intellectual property core and response data thereof, the completer request interface may transmit the request actively sent by the intellectual property core to the controller 1 or the specified functional module, and the completer completion interface may transmit response data of the controller 1 and the functional module to the intellectual property core for the request sent by the intellectual property core to the intellectual property core; and the second signal transmission sub-module can be used for transmitting the request sent by the functional module and the response data thereof, wherein the request interface of the requester can send the request sent by the functional module to the intellectual property core, and the completion interface of the requester can send the response signal sent by the intellectual property core to the request sent by the functional module to the appointed functional module.
The signal transmission module 2 in the embodiment of the invention can smoothly realize data transmission between each functional module in the intellectual property core and the PCIe equipment.
Of course, other specific forms of the signal transmission module 2 besides this specific architecture are also possible, and the embodiments of the present invention are not limited herein.
As an embodiment, the terminal device expansion device is arranged in a field programmable gate array where the high-speed serial computer expansion bus standard device is located.
Specifically, considering that the FPGA has the advantages of fast data processing speed, the terminal device extension device in the embodiment of the present invention may be disposed in the FPGA where the PCIe device is located.
Of course, the terminal device extension device may be disposed outside the FPGA, and the embodiment of the present invention is not limited herein.
As an embodiment, the controller 1 includes a first controller core and a first memory module;
the first controller core is used for communicating with the first signal transmission sub-module through the own advanced expansion bus interface facing the flow, responding to the port scanning request sent by the host through the intellectual property core in the initialization stage of the high-speed serial computer expansion bus standard equipment, and storing the initialization data generated in the topology initialization process and sent by the host through the intellectual property core into the pre-stored port configuration data;
and the first storage module is used for storing data.
Specifically, considering that the IP cores in FPGAs of different manufacturers are different, the specific situation when the controller 1 is designed based on the IP cores in the FPGAs is different, and in combination, in order to improve the data transmission efficiency, the communication interfaces between the controller 1 and the completer request interface and between the controller and the completer completion interface can be designed to be flow-oriented advanced expansion bus interfaces (AXIS, advanced eXtensible Interface Stream), while the IP cores of FPGAs of some manufacturers are provided with the AXIS interfaces, so that the controller 1 designed based on the IP cores can directly communicate with the first signal transmission submodule through the AXIS interfaces.
As an embodiment, the controller 1 further includes:
the first signal connection module is connected with the first controller core and is used for generating a plurality of signal interfaces of specified types based on the simplified advanced expansion bus interface of the first controller core.
Specifically, in consideration of that, besides communication with the first signal transmission sub-module, there are other communication requirements of the first controller core of the controller 1, so more interfaces are required, so in the embodiment of the present invention, the first signal connection module may be configured for the controller 1, so as to generate a plurality of signal interfaces of a specified type based on the simplified advanced expansion bus interface of the first controller core, thereby supporting more communication requirements of the controller 1.
As one embodiment, the first signal connection module includes a first port expansion module and a first port conversion module;
the first port expansion module is used for expanding the simplified advanced expansion bus interface of the first controller core into a plurality of simplified advanced expansion bus interfaces;
the first port conversion module is used for converting the single simplified advanced expansion bus interface provided by the first port expansion module into a signal interface of a target type;
the target type comprises a general input/output interface and a serial interface.
Specifically, for better explaining the embodiments of the present invention, please refer to fig. 3, fig. 3 is a schematic structural diagram of a controller provided by the present invention, and the first port conversion module includes a first conversion module, a second conversion module and a third conversion module in fig. 3.
Specifically, in view of the limited number of data interfaces in the IP core, in order to implement more interfaces, the simplified advanced expansion bus interface (AXI-Lite) of the first controller core may be expanded into a plurality of interfaces by the first port expansion module, and then a single simplified advanced expansion bus interface provided by the first port expansion module may be converted into a signal interface of a target type by the first port conversion module. Specifically, in fig. 3, the first to third conversion modules may respectively convert signal interfaces of corresponding target types, for example, may include a universal input/output interface, a serial interface, and an interrupt controller interface (axi_intc), through which external debugging of the first controller core may be implemented.
The first controller core may be a MicroBlaze IP core of Xilinx.
As an embodiment, the controller 1 includes a second controller core, a second storage module, and a signal transfer module;
the second controller kernel is used for communicating with the advanced expansion bus interface facing the flow of the first signal transmission sub-module under the cooperation of the client instruction interface and the signal transfer module, responding to the port scanning request sent by the host through the intellectual property core in the initialization stage of the high-speed serial computer expansion bus standard equipment, and storing the initialization data generated in the topology initialization process and sent by the host through the intellectual property core into pre-stored port configuration data;
the second storage module is used for storing data;
the signal transfer module is used for sending the data of the client instruction interface of the second controller core to the stream-oriented advanced expansion bus interface of the first signal transmission sub-module according to the state signal of the stream-oriented advanced expansion bus interface of the first signal transmission sub-module, and caching the data sent by the stream-oriented advanced expansion bus interface of the first signal transmission sub-module so that the second controller core can read the cached data through the client instruction interface.
Specifically, for better illustrating an embodiment of the present invention, please refer to fig. 4, fig. 4 is a schematic structural diagram of another controller according to the present invention.
Specifically, considering that some manufacturer's IP cores (the IP cores in fig. 4 may be Nios-V/g) do not have an AXIS interface, in order to implement the communication of the AXIS interface, in this embodiment of the present invention, a signal switching module is designed, so that, under the cooperation of the client instruction interface of the second controller core and the signal switching module, the second controller core may communicate with the advanced expansion bus interface facing the flow of the first signal transmission sub-module, where the signal switching module in fig. 4 includes a custom module 0-3, and the Nios-V uses a dedicated CI (Custom Instruction, client instruction) interface for supporting the client instruction. Each instruction is connected with an independent interface, and the realization of the instruction is realized by a client through verilog code coding. In this example, 4 axis interfaces are needed, so that 4 instructions are respectively corresponding, but only two interface modes of axis master and slave are actually needed, only 2 Custom modules are needed to be designed, and Custom-0/2 (namely Custom module 0/2) is the master mode of axis, and the implementation process is as follows: the guest instruction loads 2 operands, data0 is 32 bits of data to be sent onto the axis bus, and data1 is last flag bit to be sent onto the axis bus. If the ready signal of the axis bus is 1, data is sent and the valid signal is also set to 1, otherwise the ready signal is waited to become 1. When the Ready and valid signals are simultaneously 1, the successful sending is indicated, and a result 0 is returned. Custom-1/3 (i.e., custom module 1/3) is an axis slave mode, implemented as follows: the client instruction module uses a built-in FIFO (First Input First Output, first-in first-out memory) to receive data on the axis bus, and based on the packet mode, pauses the reception of bus data every time a data packet is received until the software instruction finishes receiving the data packet and then continues to receive new data. The guest instruction does not load an operand, but the functional area in the instruction indicates whether the instruction reads the status of the FIFO or the data content in the FIFO. And reading the FIFO state, returning the data depth in the FIFO through a result interface, and if the depth is 0, expressing that no valid data exists. If a non-0 value is returned, a number of read data instructions are initiated consecutively based on the value, the data content in the FIFO is read out. At this point the result interface returns the data content.
As an embodiment, the controller 1 further includes:
and the second signal connection module is connected with the second controller core and is used for generating a plurality of signal interfaces of specified types based on the advanced expansion bus interface of the second controller core.
In particular, in view of the limited number of data interfaces that are provided in the IP core itself, in order to implement more interfaces, several signal interfaces of a specified type may be generated based on the advanced expansion bus interface of the second controller core, so as to support more communication requirements of the controller 1.
As one embodiment, the second signal connection module includes a second port expansion module and a second port conversion module;
the second port expansion module is used for expanding the simplified advanced expansion bus interface of the second controller core into a plurality of ports;
the second port conversion module is used for converting the single simplified advanced expansion bus interface provided by the second port expansion module into a signal interface of a target type;
the target type comprises a general input/output interface and a serial interface.
Specifically, the advanced expansion bus interface of the second controller core may be first expanded into a plurality of advanced expansion bus interfaces by the second port expansion module, and then a single AXI interface provided by the second port expansion module may be converted into a target type signal interface by the second port conversion module. Specifically, in fig. 4, the fourth to fifth conversion modules may respectively convert signal interfaces of corresponding target types, for example, may respectively convert a general input/output interface, a serial interface, and the like, and may implement debugging of the second controller core through the serial interface.
The AXI interface of the second controller core may be an AXI4 (For high-performance memory-mapped requirements, for high-performance memory mapping requirements), which mainly faces to the requirements of high-performance address mapping communication, and is an address mapping-oriented interface, which allows For maximum 256 rounds of data burst transmission.
Of course, the second signal connection module may be of other types besides this specific configuration, and embodiments of the present invention are not limited herein.
As an embodiment, the controller 1 is further configured to:
and responding to a modification instruction sent by the host through the intellectual property core, and modifying the port configuration data and/or the preset quantity.
Specifically, considering that the host may have a need for modifying the port configuration data or the preset number of ports of the functional module, in the embodiment of the present invention, the port configuration data and/or the preset number may be modified in response to a modification instruction sent by the host through the intellectual property core.
As an embodiment, the terminal device extension device further includes:
the man-machine interaction module is connected with the controller 1 and is used for changing port configuration data and/or preset quantity in the controller 1.
Specifically, considering that a worker near the controller 1 also has a need to modify the port configuration data or the preset number of ports of the functional module, in the embodiment of the present invention, a man-machine interaction module connected to the controller 1 may be configured to modify the port configuration data and/or the preset number in the controller 1 through the man-machine interaction module.
The man-machine interaction module may be of various types, such as a notebook computer, and the embodiment of the invention is not limited herein.
As an embodiment, the first signal transmission sub-module is further configured to:
and determining the space number of the base address register to which the target memory address of the request sent to the specified functional module by the intellectual property core belongs, and binding the space number of the base address register with the corresponding request and sending the binding to the specified functional module.
Specifically, considering that the functional module needs to determine the base address register space number to which the target memory address of the request belongs by itself after receiving the request, the first signal transmission submodule itself can determine the content more efficiently, so the first signal transmission submodule in the embodiment of the present invention is further configured to: and determining the space number of the base address register to which the target memory address of the request sent to the specified functional module by the intellectual property core belongs, and binding the space number of the base address register with the corresponding request and sending the binding to the specified functional module.
As an embodiment, the controller 1 is further configured to initialize the interrupt data pre-stored in the specified memory 3 in response to an interrupt data initialization instruction sent by the host through the intellectual property core of the high-speed serial computer expansion bus standard device in an initialization phase of the high-speed serial computer expansion bus standard device, so that the functional module sends an interrupt request to the host through the interrupt data.
Specifically, considering that the host also needs to initialize interrupt data in the initialization stage of the PCIe device, so that the function module generates an interrupt request sent to the IP core through the interrupt data, in order to fully utilize the computing capability of the controller 1, in the embodiment of the present invention, the controller 1 is further configured to, in the initialization stage of the high-speed serial computer expansion bus standard device, respond to an interrupt data initialization instruction sent by the host through the intellectual property core of the high-speed serial computer expansion bus standard device, initialize the interrupt data pre-stored in the specified memory 3, so that the function module sends an interrupt request to the host through the interrupt data.
Specifically, the interrupt data may include three types of data, which are stored in the form of tables, respectively, including an interrupt configuration table, an interrupt vector table, and a pending bit table, where whether each PF or VF uses interrupts, and the number of interrupts used and the offset position in the interrupt vector table are recorded in the interrupt configuration table. The definitions of the interrupt vector table and the pending bit table are consistent with the definitions in the PCIe specification. Interrupt data can be read and written by the controller 1 and the user interrupt request processing module, respectively.
Specifically, the interrupt request processing module in fig. 2: and receiving an interrupt sending application of a user through the functional module, checking an interrupt configuration table, and reading the interrupt vector table if the equipment has interrupt enabling. If the interrupt mask bit is not enabled, an interrupt application is sent, and a PBA (suspension flag) bit is cleared (PBA is zero representing non-suspension waiting and 1 representing suspension waiting); otherwise, if the interrupt mask bit enabled condition is encountered, the PBA is set to 1, and the interrupt application is abandoned. When the module does not receive the interrupt sending application of the user, polling the interrupt vector table, and finding that the effective unmasked interrupt vector of the PBA bit exists, then sending the interrupt application.
The topology initialization command and the interrupt data initialization command in the data frame sent by the intellectual property core need to be forwarded to the controller 1 by the completer request interface, and other data frames irrelevant to the controller 1 are sent to the downstream functional modules.
As an example, memory 3 is designated as memory in a field programmable gate array in which a high-speed serial computer expansion bus standard device resides.
Specifically, considering that the memory in the FPGA has the characteristic of fast data processing speed, in order to improve the transmission rate of the interrupt data, the designated memory 3 in the embodiment of the present invention is a memory in the field programmable gate array where the high-speed serial computer expansion bus standard device is located.
Referring to fig. 5, fig. 5 is a flow chart of a terminal device expansion method provided by the present invention, where the terminal device expansion method is applied to a controller 1, and includes:
s501: in the initialization stage of the high-speed serial computer expansion bus standard equipment, responding to a port scanning request sent by a host through an intellectual property core, so that the host can complete scanning of a preset number of function module ports supported by the controller 1 and topology initialization work of the high-speed serial computer expansion bus standard equipment;
s502: storing initialization data generated in a topology initialization process, which is sent by a host through an intellectual property core, into pre-stored port configuration data;
the intellectual property core of the high-speed serial computer expansion bus standard device is the intellectual property core in the field programmable gate array, the intellectual property core of the high-speed serial computer expansion bus standard device is in a bridge mode, and the upper limit of the preset quantity is the total quantity of bus resources specified by the high-speed serial computer expansion bus standard.
As an embodiment, the terminal device extension method further includes:
s503: in the initialization stage of the high-speed serial computer expansion bus standard device, in response to an interrupt data initialization instruction sent by the host through the intellectual property core of the high-speed serial computer expansion bus standard device, the interrupt data pre-stored in the designated memory 3 is initialized so that the functional module sends an interrupt request to the host through the interrupt data.
As an example, memory 3 is designated as memory in a field programmable gate array in which a high-speed serial computer expansion bus standard device resides.
As an embodiment, the terminal device extension method further includes:
s504: and responding to a modification instruction sent by the host through the intellectual property core, and modifying the port configuration data and/or the preset quantity.
For the description of the terminal device extension method provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the terminal device extension device, and the embodiment of the present invention is not repeated herein.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a terminal device expansion device provided by the present invention, where the terminal device expansion device is applied to a controller 1, and includes:
a transmitting module 61, configured to respond to a port scanning request sent by the host through the intellectual property core in an initialization stage of the high-speed serial computer expansion bus standard device, so that the host finishes scanning a preset number of ports of the functional module supported by the controller 1 and finishes topology initialization work for the high-speed serial computer expansion bus standard device;
a storage module 62, configured to store initialization data generated in a topology initialization process, which is sent by a host through an intellectual property core, to pre-stored port configuration data;
The intellectual property core of the high-speed serial computer expansion bus standard device is the intellectual property core in the field programmable gate array, the intellectual property core of the high-speed serial computer expansion bus standard device is in a bridge mode, and the upper limit of the preset quantity is the total quantity of bus resources specified by the high-speed serial computer expansion bus standard.
For the description of the terminal device expansion apparatus provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the terminal device expansion apparatus, and the embodiment of the present invention is not repeated herein.
The invention also provides high-speed serial computer expansion bus standard equipment, which comprises the terminal equipment expansion equipment.
For the description of the high-speed serial computer expansion bus standard device provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the terminal device expansion device, and the embodiment of the present invention is not repeated herein.
The invention also provides a server comprising the high-speed serial computer expansion bus standard device.
For the introduction of the server provided by the embodiment of the present invention, reference is made to the foregoing embodiment of the terminal device extension apparatus, and the embodiment of the present invention is not repeated herein.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer readable storage medium provided in the present invention, in which a computer program 71 is stored in the computer readable storage medium 70, and the computer program 71 implements the steps of the terminal device extension method when executed by a processor.
For the description of the computer readable storage medium provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the terminal device extension apparatus, and the embodiment of the present invention is not repeated here.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (18)
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