CN116685140A - Manufacturing method of semiconductor device, semiconductor device and stacking device - Google Patents

Abstract

The embodiment of the present disclosure discloses a manufacturing method of a semiconductor device, a semiconductor device and a stacked device. The manufacturing method includes: forming a common lower plate on a substrate; forming an isolation layer on the common lower plate and being defined by the isolation layer A plurality of sacrificial layers extending along the first direction and arranged along the second direction; forming a first conductive layer extending along the first direction on the sacrificial layer; forming a first conductive layer on the first conductive layer, the sacrificial layer and the isolation layer an insulating layer; etching the first insulating layer to form a first trench extending along the second direction and exposing a plurality of sacrificial layers; removing the sacrificial layer through the first trench to form a plurality of channels connected to the first trench A hole structure; respectively forming a first dielectric layer and a second dielectric layer in the hole structure and the first trench; etching the first insulating layer to form a second trench and a third trench on both sides of the second dielectric layer Groove; forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively.

Description

Manufacturing method of semiconductor device, semiconductor device and stacked device

technical field

The present disclosure relates to the field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor device, a semiconductor device and a stacked device.

Background technique

A semiconductor device, such as a dynamic random access memory (DRAM), generally includes a substrate, a transistor in the substrate, and a capacitor on the substrate, the capacitor is used to store charges, and the transistor and the capacitor constitute a storage unit.

However, in related technologies, the capacitor usually extends along a fixed direction, and the surface area of the capacitor is small, resulting in a low charge storage capacity of the capacitor; in addition, the capacitor often has a large depth, which can accommodate The capacitance of the semiconductor device is less, and the storage density of the semiconductor device is lower.

Contents of the invention

An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

provide the substrate;

forming a common lower plate on the substrate;

Forming an isolation layer and a plurality of sacrificial layers extending along the first direction defined by the isolation layer on the common lower electrode plate, and the plurality of sacrificial layers are arranged and distributed along the second direction;

forming a plurality of first conductive layers extending along the first direction on the plurality of sacrificial layers;

forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer;

etching the first insulating layer to form a first trench extending along the second direction, the first trench exposing a plurality of the sacrificial layers;

removing a plurality of the sacrificial layers through the first trench to form a plurality of hole structures communicating with the first trench;

forming a first dielectric layer in the plurality of hole structures, and forming a second dielectric layer in the first groove;

Etching the first insulating layer to form a plurality of second grooves exposing the first dielectric layer, and a plurality of third grooves exposing the common lower plate, the second grooves and the third trench are arranged on both sides of the second dielectric layer;

A second conductive layer and a third conductive layer are respectively formed in the second trench and the third trench.

In some embodiments, removing the plurality of sacrificial layers through the first trench includes: passing an etching solution into the first trench, and the etching solution removes the plurality of sacrificial layers; Wherein, the etching rate of the sacrificial layer is greater than the etching rate of the isolation layer.

In some embodiments, after forming the first insulating layer, the method further includes:

A plurality of channel layers extending along the first direction and a buried layer between the plurality of channel layers are formed on the first insulating layer, and the plurality of channel layers extend along the second direction arranged.

In some embodiments, the channel layer and the buried layer are formed before forming the first trench, and the first trench, the second trench, and the third trench all pass through the The channel layer; the method also includes:

A first spacer layer extending in the second direction and cutting the channel layer is formed in the channel layer and the buried layer, the first spacer layer and the first trench divide the trench The channel layer is divided into discrete active regions.

In some embodiments, the channel layer and the buried layer are formed after the second conductive layer and the third conductive layer are formed, and the channel layer and the buried layer cover the first insulating layer. layer, the second conductive layer, the third conductive layer, and the second dielectric layer, the channel layer is in contact with the second conductive layer and the third conductive layer; the method also includes:

A first spacer layer and a second spacer layer extending along the second direction and cutting off a plurality of the channel layers are formed in the channel layer and the buried layer, and the first spacer layer and the first spacer layer Two separation layers separate the channel layer into separate active regions; wherein, the second separation layer covers the second dielectric layer.

In some embodiments, the method also includes:

forming a third dielectric layer on the channel layer and the buried layer, and forming a word line material layer on the third dielectric layer;

etching the word line material layer to form a word line layer extending along the second direction;

A fourth dielectric layer is formed on the substrate, and the fourth dielectric layer covers the third dielectric layer and the word line layer.

In some embodiments, the method also includes:

forming a second insulating layer on the fourth dielectric layer;

Etching the second insulating layer, the fourth dielectric layer, and the third dielectric layer to expose the channel layer, forming a plurality of bit line contact holes arranged along the second direction;

forming a bit line contact plug in the bit line contact hole;

A plurality of bit line layers extending along the first direction are formed on the bit line contact plug and the second insulating layer, and the plurality of bit line layers are arranged along the second direction.

An embodiment of the present disclosure also provides a semiconductor device, including:

a substrate and a common lower plate on said substrate;

An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending along the first direction defined by the isolation layer, and the plurality of first dielectric layers are arranged and distributed along the second direction;

a plurality of first conductive layers respectively located on the plurality of first dielectric layers and extending along the first direction;

A first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first groove extending along the second direction, and is disposed on the first insulating layer. A plurality of second grooves and a plurality of third grooves on both sides of the first groove; wherein, the second grooves expose the first dielectric layer, and the third grooves expose the common lower plate;

The second dielectric layer, the second conductive layer and the third conductive layer are respectively located in the first trench, the second trench and the third trench.

In some embodiments, in the first direction, both ends of the first conductive layer are indented inwardly relative to both ends of the first dielectric layer; in the second direction, the first The two ends of a conductive layer protrude outward relative to the two ends of the first dielectric layer.

In some embodiments, the semiconductor device further includes: a plurality of channel layers extending along the first direction on the first insulating layer and a buried layer between the plurality of channel layers, A plurality of the channel layers are arranged along the second direction.

In some embodiments, the first trench, the second trench, and the third trench all penetrate the channel layer; the semiconductor device further includes: a first trench extending along the second direction a spacer layer, the first spacer layer is located in the channel layer and the buried layer and cuts off a plurality of the channel layers, the first spacer layer and the first trench divide the channel The layers are separated into discrete active regions.

In some embodiments, the channel layer is located above the second conductive layer, the third conductive layer, and the second dielectric layer, and the channel layer and the second conductive layer, the first Three conductive layer contacts; the semiconductor device further includes: a first separation layer and a second separation layer extending along the second direction, the first separation layer and the second separation layer are located between the channel layer and the second separation layer In the buried layer and cut off a plurality of the channel layers, the first separation layer and the second separation layer separate the channel layer into a plurality of active regions; wherein the second separation layer covering the second dielectric layer.

In some embodiments, the semiconductor device further includes: a third dielectric layer covering the channel layer and the buried layer; a word line layer extending along the second direction, the The word line layer is located on the third dielectric layer; the fourth dielectric layer covers the third dielectric layer and the word line layer.

In some embodiments, the semiconductor device further includes: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending along the first direction, located on the fourth dielectric layer On the two insulating layers and arranged along the second direction; a bit line contact plug, the bit line contact plug is connected with the bit line layer and the channel layer.

An embodiment of the present disclosure also provides a stacked device, including:

a substrate and a plurality of memory structures stacked on the substrate;

The storage structure includes:

Common lower plate;

An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending along the first direction defined by the isolation layer, and the plurality of first dielectric layers are arranged and distributed along the second direction;

a plurality of first conductive layers respectively located on the plurality of first dielectric layers and extending along the first direction;

A first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first groove extending along the second direction, and is disposed on the first insulating layer. A plurality of second grooves and a plurality of third grooves on both sides of the first groove; wherein, the second grooves expose the first conductive layer, and the third grooves expose the common lower plate;

The second dielectric layer, the second conductive layer and the third conductive layer are respectively located in the first trench, the second trench and the third trench.

An embodiment of the present disclosure discloses a manufacturing method of a semiconductor device, a semiconductor device, and a stacked device, wherein the manufacturing method includes: providing a substrate; forming a common lower plate on the substrate; An isolation layer and a plurality of sacrificial layers extending along the first direction defined by the isolation layer are formed on the board, and the plurality of sacrificial layers are arranged and distributed along the second direction; a first conductive layer extending in the first direction; a first insulating layer is formed on the first conductive layer, the sacrificial layer and the isolation layer; the first insulating layer is etched to form a The first trenches extending in two directions, the first trenches expose a plurality of the sacrificial layers; the plurality of sacrificial layers are removed through the first trenches to form a plurality of the first trenches A connected hole structure; forming a first dielectric layer in the plurality of hole structures, forming a second dielectric layer in the first trench; etching the first insulating layer to form a plurality of exposed The second groove of the first dielectric layer, and a plurality of third grooves exposing the common lower plate, the second groove and the third groove are arranged on both sides of the second dielectric layer side; forming a second conductive layer and a third conductive layer in the second trench and the third trench, respectively. The common lower plate, the first conductive layer, the second conductive layer, the third conductive layer, the first dielectric layer and the second dielectric layer provided by the embodiments of the present disclosure constitute a capacitor for storing charges, wherein the first conductive layer is different from the extension direction of the second conductive layer and the third conductive layer, that is, the capacitance in the embodiments of the present disclosure extends in two different directions, compared with the capacitance in the related art that only extends in one direction, The capacitor provided by the embodiment of the present disclosure has a larger surface area, so that it can have a larger charge storage capacity; at the same time, compared with the capacitor in the related art, the capacitor in the embodiment of the present disclosure can have a smaller depth, so that the The semiconductor device can accommodate more capacitors per unit volume, which can increase the storage density of the semiconductor device. In addition, in the embodiments of the present disclosure, there is no need to provide a support structure for supporting capacitors, which simplifies the manufacturing process of the semiconductor device.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

2a to 18b are process flow diagrams of semiconductor devices provided by embodiments of the present disclosure;

19a to 25b are process flow charts of a semiconductor device provided by another embodiment of the present disclosure;

FIG. 26 is a schematic diagram of a stacked device provided by an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. , adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Whereas a second element, component, region, layer or section is discussed, it does not indicate that the present disclosure necessarily presents a first element, component, region, layer or section.

Spatial terms such as "below...", "below...", "below", "below...", "on...", "above" and so on, can be used here for convenience are used in description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

A semiconductor device, such as a dynamic random access memory (DRAM), generally includes a substrate, a transistor in the substrate, and a capacitor on the substrate, the capacitor is used to store charges, and the transistor and the capacitor constitute a storage unit.

However, in related technologies, the capacitor usually extends along a fixed direction, and the surface area of the capacitor is small, resulting in a low charge storage capacity of the capacitor; in addition, the capacitor often has a large depth, which can accommodate The capacitance of the semiconductor device is less, and the storage density of the semiconductor device is lower.

Based on this, the following technical solutions of the disclosed embodiments are proposed:

An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, please refer to FIG. 1 for details. As shown, the method includes the following steps:

Step 101, providing a substrate;

Step 102, forming a common lower plate on the substrate;

Step 103, forming an isolation layer and a plurality of sacrificial layers extending along the first direction defined by the isolation layer on the common lower electrode plate, and the plurality of sacrificial layers are arranged and distributed along the second direction;

Step 104, forming a plurality of first conductive layers extending along the first direction on the plurality of sacrificial layers;

Step 105, forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer;

Step 106, etching the first insulating layer to form a first trench extending along the second direction, the first trench exposing a plurality of the sacrificial layers;

Step 107, removing a plurality of the sacrificial layers through the first trench to form a plurality of hole structures communicating with the first trench;

Step 108, forming a first dielectric layer in the plurality of hole structures, and forming a second dielectric layer in the first trenches;

Step 109, etching the first insulating layer to form a plurality of second grooves exposing the first dielectric layer, and a plurality of third grooves exposing the common lower plate, the first The second groove and the third groove are arranged on both sides of the second dielectric layer;

Step 110 , forming a second conductive layer and a third conductive layer in the second trench and the third trench respectively.

The common lower plate, the first conductive layer, the second conductive layer, the third conductive layer, the first dielectric layer and the second dielectric layer provided by the embodiments of the present disclosure form a capacitor for storing charges, and the first conductive layer and The extension directions of the second conductive layer and the third conductive layer are different, that is, the capacitance in the embodiment of the present disclosure extends along two different directions. Compared with the capacitance extending in only one direction in the related art, the present disclosure The capacitor provided by the embodiment has a larger surface area, so it can have a larger charge storage capacity; at the same time, the capacitor in the embodiment of the present disclosure can have a smaller depth, so that the semiconductor device can accommodate more charges per unit volume. Capacitance can increase the storage density of semiconductor devices. In addition, in the embodiments of the present disclosure, there is no need to provide a support structure for supporting capacitors, which simplifies the manufacturing process of the semiconductor device.

The manufacturing method provided by the embodiments of the present disclosure can be used to manufacture dynamic random access memory (DRAM), but is not limited thereto. Any semiconductor device with capacitance can be manufactured using the method provided by the embodiments of the present application.

The specific implementation manners of the present disclosure will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of illustration, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

Figures 2a to 18b are process flow charts of semiconductor devices provided by embodiments of the present disclosure, and Figures 19a to 25b are process flow charts of semiconductor devices provided by another embodiment of the present disclosure; wherein, Figure 2a, Figure 3a, and Figure 4a , Figure 5a, Figure 6a, Figure 7a, Figure 8a, Figure 9a, Figure 10a, Figure 11a, Figure 12a, Figure 13a, Figure 14a, Figure 15a, Figure 16a, Figure 17a, Figure 18a are semiconductors provided by embodiments of the present disclosure The schematic top view of the manufacturing method of the device in different process steps, Fig. 2b, Fig. 3b, Fig. 4b, Fig. 5b, Fig. 6b, Fig. 7b, Fig. 8b, Fig. 9b, Fig. 10b, Fig. 11b, Fig. 12b, Fig. 13b, Fig. 14b, FIG. 15b, FIG. 16b, FIG. 17b, and FIG. 18b are respectively along FIG. 2a, FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. Fig. 13a, Fig. 14a, Fig. 15a, Fig. 16a, Fig. 17a, Fig. 17a, Fig. 17a, Fig. 17a, Fig. 18a is a schematic cross-sectional structural diagram taken along the line AA'; Fig. 19a, Fig. 20a, Fig. 21a, Fig. 22a, Fig. 23a, Fig. 24a, Fig. 25a are the present disclosure Another embodiment provides a schematic top view of a semiconductor device manufacturing method in different process steps, Figure 19b, Figure 20b, Figure 21b, Figure 22b, Figure 23b, Figure 24b, Figure 25b are respectively along Figure 19a, Figure 20a, 21a, 22a, 23a, 24a, 25a are schematic cross-sectional structural diagrams taken along line AA'. The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure will be further described in detail below with reference to FIGS. 2 a to 25 b.

Firstly, step 101 is executed, as shown in FIG. 2 a to FIG. 2 b , a substrate 20 is provided.

The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

Next, step 102 is performed, as shown in FIG. 3 a to FIG. 3 b , forming a common lower plate 32 on the substrate 20 .

The material of the common lower plate 32 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal One or more of alloys, for example, titanium nitride (TiN).

Referring to FIG. 3b again, in one embodiment, before forming the common lower plate 32 on the substrate 20, the method further includes: forming an interlayer insulating layer 31 on the substrate 20, the interlayer The insulating layer 31 is located under the common lower plate 32 for electrically isolating the substrate 20 and the common lower plate 32 . The interlayer insulating layer 31 can be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. After the insulating layer 31 , a planarization process, such as chemical mechanical polishing (CMP) and/or etching process, can also be used to make the upper surface of the interlayer insulating layer 31 more flat. The material of the interlayer insulating layer 31 may be oxide, for example, silicon oxide.

Next, step 103 is executed, as shown in FIG. 4a to FIG. 4b, an isolation layer 33 and a plurality of sacrificial layers 34 extending along the first direction defined by the isolation layer 33 are formed on the common lower electrode plate 32. The sacrificial layers 34 are arranged and distributed along the second direction.

In an embodiment, the first direction and the second direction are parallel to the surface of the substrate 20 . In some embodiments, the first direction is perpendicular to the second direction. But not limited thereto, the first direction may also be oblique to the second direction.

It should be noted that the number and arrangement of the multiple sacrificial layers 34 are not limited to those shown in FIG. . In one embodiment, the plurality of sacrificial layers 34 are respectively arranged in an array along the first direction and the second direction.

As shown in FIG. 4 b , the lower surface of the sacrificial layer 34 is in contact with the common lower electrode plate 32 , and the upper surface of the sacrificial layer 34 is flush with the upper surface of the isolation layer 33 . The formation method of the isolation layer 33 and the sacrificial layer 34 may be, for example: first, the isolation layer 33 is formed on the common lower plate 32; The opening (not marked) that shares the lower plate 32 and extends along the first direction, and a plurality of the openings (not marked) are arranged along the second direction; finally formed in the opening (not marked) The sacrificial layer 34 . The material of the isolation layer 33 is insulating material. Subsequently, an etching process will be performed to remove the sacrificial layer 34 and retain the isolation layer 33. Therefore, under preset etching conditions, the etching rate of the sacrificial layer 34 should be much higher than that of the isolation layer 33. The etch rate, that is, the sacrificial layer 34 and the isolation layer 33 have a relatively large etching selectivity, so that only the sacrificial layer 34 can be removed and the isolation layer 33 can be retained in a subsequent process. In a specific embodiment, the range of the etching selectivity ratio is greater than 10, such as between 20 and 100, the material of the sacrificial layer 34 is, for example, polysilicon, and the material of the isolation layer 33 is, for example, silicon nitride wait.

Next, step 104 is performed, as shown in FIG. 5 a to FIG. 5 b , forming a plurality of first conductive layers 35 extending along the first direction on the plurality of sacrificial layers 34 .

In some embodiments, in the first direction, the two ends of the first conductive layer 35 are indented inwardly relative to the two ends of the sacrificial layer 34 , so that the first conductive layer 35 can be avoided The two ends of the first conductive layer 35 are in contact with other conductive layers; in the second direction, the two ends of the first conductive layer 35 protrude outward relative to the two ends of the sacrificial layer 34, so that the first conductive layer 35 has a larger surface area, which increases the surface area of the capacitor C (see FIG. 11 a to FIG. 11 b ) formed in the subsequent process, so that half of the charge storage capacity of the capacitor C can be increased. The material of the first conductive layer 35 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal One or more of alloys, for example, titanium nitride (TiN). In one embodiment, the material of the first conductive layer 35 is the same as that of the common lower plate 32 .

Next, step 105 is performed, as shown in FIGS. 6 a to 6 b , forming a first insulating layer 36 on the first conductive layer 35 , the sacrificial layer 34 and the isolation layer 33 .

The material of the first insulating layer 36 may be oxide, such as silicon oxide. In one embodiment, the material of the first insulating layer 36 is the same as that of the interlayer insulating layer 31 .

Next, step 106 is performed, as shown in FIG. 7a to FIG. multiple sacrificial layers 34 .

In one embodiment, the first insulating layer 36 is etched from top to bottom along a direction perpendicular to the surface of the substrate 20 to form the first trench T1, and the first trench T1 extends downward. The direction is perpendicular to the surface of the substrate 20 .

In one embodiment, during the process of forming the first trench T1, after etching the first insulating layer 36, etching part of the sacrificial layer 34 and/or part of the isolation layer 33 is further included. until the common lower plate 32 is exposed, the sidewall of the first trench T1 exposes a plurality of sacrificial layers 34 , and at the same time exposes the isolation layer 33 between the plurality of sacrificial layers 34 . In some embodiments, the sidewall of the first trench T1 exposes one of the two ends of the sacrificial layer 34 in the first direction.

Next, step 107 is executed, as shown in FIG. 8 a to FIG. 8 b , removing a plurality of the sacrificial layers 34 through the first trenches T1 to form a plurality of hole structures S1 communicating with the first trenches T1 .

In one embodiment, removing the plurality of sacrificial layers 34 through the first trench T1 includes: passing an etchant into the first trench T1, and the etchant removes the plurality of sacrificial layers 34 . Sacrificial layer 34; wherein, the etching rate of the sacrificial layer 34 is greater than the etching rate of the isolation layer 33, so that the isolation layer is retained while the sacrificial layer 34 is removed to form a plurality of hole structures S1 33 , the plurality of hole structures S1 extend along the first direction and are arranged along the second direction, and the plurality of hole structures S1 are separated by the isolation layer 33 .

Next, step 108 is executed, as shown in FIG. 9a to FIG. 9b , forming a first dielectric layer 41 in the plurality of hole structures S1 , and forming a second dielectric layer 42 in the first trench T1 .

Here, the number of the first dielectric layer 41 is multiple, and the multiple first dielectric layers 41 extend along the first direction and are arranged along the second direction; the second dielectric layer 42 is arranged along the second direction. extending in the second direction and connected to a plurality of the first dielectric layers 41 . The material of the first dielectric layer 41 and the material of the second dielectric layer 42 can be high dielectric constant materials, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide , yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate, etc. In a more specific embodiment, the material of the first dielectric layer 41 is the same as that of the second dielectric layer 42 .

Next, step 109 is performed, as shown in FIG. 10a to FIG. The third trench T3 of the common lower plate 32 , the second trench T2 and the third trench T3 are disposed on both sides of the second dielectric layer 42 .

As shown in FIG. 10b, the bottom of the second trench T2 exposes the first dielectric layer 41, and the sidewall of the second trench T2 exposes the first conductive layer 35; During the process of the three trenches T3, after etching the first insulating layer 36 , it also includes etching the isolation layer 33 to expose the common lower electrode plate 32 .

In one embodiment, the plurality of second trenches T2 and the plurality of third trenches T3 are perpendicular to the surface of the substrate 20 and arranged along the second direction. In some embodiments, the second trench T2 and the third trench T3 are symmetrically disposed on two sides of the second dielectric layer 42 .

Next, step 110 is executed, as shown in FIGS. 11 a to 11 b , forming a second conductive layer 43 and a third conductive layer 44 in the second trench T2 and the third trench T3 respectively.

The number of the second conductive layer 43 and the number of the third conductive layer 44 are multiple, and the multiple second conductive layers 43 and the multiple third conductive layers 44 are respectively in the second medium The two sides of the layer 42 are arranged along the second direction, and the multiple second conductive layers 43 are connected to the multiple first conductive layers 35 in one-to-one correspondence, and the multiple third conductive layers 44 are connected to the common The lower pole plate 32 is connected.

In the embodiment of the present disclosure, the first dielectric layer 41 is firstly formed and the second dielectric layer 42 is formed in the first trench T1, and then the two sides of the second dielectric layer 42 are formed respectively. The second conductive layer 43 connected to the first conductive layer 35 and the third conductive layer 44 connected to the common lower plate 32, instead of forming the second conductive layer in the first trench T1 first The conductive layer 43, in this way, in the case where the bottom of the first trench T1 exposes the common lower plate 32, it is avoided that the second conductive layer 43 is simultaneously connected with the first conductive layer 35 and the The common lower plate 32 is connected to avoid short circuit phenomenon. The common lower plate 32, a plurality of the first conductive layers 35, a plurality of the second conductive layers 43, a plurality of the third conductive layers 44, a plurality of the first dielectric layers 41 and the The second dielectric layer 42 forms a plurality of capacitors C for storing charges, and the plurality of capacitors C are arranged along the second direction. The extending direction of the first conductive layer 35 is different from that of the second conductive layer 43 and the third conductive layer 44, that is, the capacitance C in the embodiment of the present disclosure extends along two different directions, which is different from that in the related art only Compared with the capacitance extending in one direction, the capacitor C provided by the embodiment of the present disclosure has a larger surface area, so that it can have a larger charge storage capacity; at the same time, compared with the capacitor in the related art, the capacitor C in the embodiment of the disclosure The capacitor C may have a smaller depth, so that the semiconductor device can accommodate more capacitors C per unit volume, which can increase the storage density of the semiconductor device. In addition, the capacitance C provided by the embodiment of the present disclosure is buried by the first insulating layer 36, so the structure of the capacitance C is more stable, no additional supporting structure for supporting the capacitance C is required, and multiple of the capacitance C The capacitor C has the same common lower plate 32, which simplifies the manufacturing process of the semiconductor device.

It should be noted that the number and arrangement of the capacitors C are not limited to those shown in FIG. 11 a , the number of the capacitors C can be more, and a plurality of the capacitors C can be arranged in an array. In an embodiment, the plurality of capacitors C are respectively arranged in an array along the first direction and the second direction. In some embodiments, in the first direction, the two ends of the first conductive layer 35 are indented inwardly relative to the two ends of the first dielectric layer 41, thus avoiding the The first conductive layer 35 of one of the two adjacent capacitors C in the direction and the third conductive layer 44 of the other are connected to each other, thereby reducing electric leakage.

The material of the second conductive layer 43 and the third conductive layer 44 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride ( TaN), one or more of metal silicides, metal alloys. In an embodiment, the material of the second conductive layer 43 and the third conductive layer 44 is the same as that of the common lower plate 32 , for example, titanium nitride (TiN).

In an embodiment, after the first insulating layer 36 is formed, the method further includes: forming a plurality of channel layers 37 extending along the first direction on the first insulating layer 36 and A buried layer 38 between a plurality of channel layers 37, and a plurality of channel layers 37 are arranged along the second direction, as shown in FIGS. 12a to 12b.

In one embodiment, the material of the channel layer 37 includes silicon, germanium, silicon germanium, indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium oxide, One or more of zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, tin aluminum zinc oxide. The channel layer 37 can be doped or undoped. When an indium gallium zinc oxide (IGZO) material is used as the channel layer 37 , electron mobility can be improved, thereby increasing the writing speed.

12a to 12b again, in a specific embodiment, the channel layer 37 and the buried layer 38 are formed after the second conductive layer 43 and the third conductive layer 44 are formed, and the channel layer 37 and the buried layer 38 are formed. The channel layer 37 and the buried layer 38 cover the first insulating layer 36, the second conductive layer 43, the third conductive layer 44 and the second dielectric layer 42, and the channel layer 37 and the The second conductive layer 43 and the third conductive layer 44 are in contact; the method further includes: forming in the channel layer 37 and the buried layer 38 a plurality of The first separation layer 39 and the second separation layer 53 of the channel layer 37, the first separation layer 39 and the second separation layer 53 separate the channel layer 37 into discrete active regions AA; wherein, The second separation layer 53 covers the second dielectric layer 42 and is in contact with the second dielectric layer 42 . There are multiple active areas AA, and the multiple active areas AA are arranged along the second direction. In a more specific embodiment, projections of the second spacer layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.

In one embodiment, the active region AA includes a first source/drain doped region (not marked) located at one end of the active region AA and adjacent to the first spacer layer 39 , located at the The other end of the active region AA and the second source/drain doped region (unmarked) in contact with the second conductive layer 43, the first source/drain doped region (unmarked) and the second Source/drain doped regions (not marked) can be formed in the active region AA by means of ion implantation. In a specific embodiment, the first source/drain doped region (not marked) and the second source/drain doped region (not marked) have the same conductivity type, such as n-type. In a more specific embodiment, the middle region of the active region AA has p-type doping.

In one embodiment, the method also includes:

A third dielectric layer 45 is formed on the channel layer 37 and the buried layer 38, and a word line material layer 46 is formed on the third dielectric layer 45, as shown in FIGS. 13a to 13b;

Etching the word line material layer 46 to form a word line layer 47 extending along the second direction, as shown in FIGS. 14a to 14b;

A fourth dielectric layer 48 is formed on the substrate 20, and the fourth dielectric layer 48 covers the third dielectric layer 45 and the word line layer 47, as shown in FIGS. 15a to 15b.

The word line material layer 46 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy one or more of . 13a to 13b again, in one embodiment, the word line material layer 46 includes a first sublayer 461 and a second sublayer 462 located on the first sublayer 461, the first sublayer 461 and the second sublayer 462 are made of different materials; etching the word line material layer 46 to form the word line layer 47 includes: etching the second sublayer 462 to form a second word line sublayer 472; The first sublayer 461 is etched to form a first word line sublayer 471, as shown in FIGS. 14a to 14b. In some embodiments, metal material is used as the word line layer 47 to reduce resistance.

In one embodiment, the word line layer 47 is formed between the first spacer layer 39 and the second conductive layer 43, the first conductive layer 35 and the first dielectric layer 41 are located between the Under the word line layer 47, the space under the word line layer 47 can be utilized, which improves the space utilization rate of the semiconductor device and further increases the storage density of the semiconductor device. In some embodiments, the word line layer 47 is disposed above the middle region of the active region AA, and the first source/drain doped region (not marked) and the second source/drain doped region Miscellaneous regions (not labeled) are separated.

In one embodiment, the third dielectric layer 45 covers both the first separation layer 39 and the second separation layer 53 . The material of the third dielectric layer 45 may include oxide, such as silicon oxide. The material of the fourth dielectric layer 48 includes but not limited to nitride, such as silicon nitride, which is used to protect the third dielectric layer 45 and the word line layer 47 .

In one embodiment, the method also includes:

Forming a second insulating layer 49 on the fourth dielectric layer 48; etching the second insulating layer 49, the fourth dielectric layer 48, and the third dielectric layer 45 to expose the channel layer 37, forming a plurality of bit line contact holes S2 arranged along the second direction, as shown in FIGS. 16a to 16b;

Forming a bit line contact plug 51 in the bit line contact hole S2, as shown in FIGS. 17a to 17b;

A plurality of bit line layers 52 extending along the first direction are formed on the bit line contact plug 51 and the second insulating layer 49, and the plurality of bit line layers 52 are arranged along the second direction , as shown in Figure 18a to Figure 18b.

Here, the bit line contact hole S2 is located between the first spacer layer 39 and the word line layer 47, exposing the active area AA, and the bit line layer 52 passes through the bit line contact plug 51. in contact with the active area AA. In one embodiment, in the first direction, there are multiple active areas AA, and each bit line layer 52 is connected to multiple active areas AA. In a specific embodiment, the bit line layer 52 is connected to the first source/drain doped region (not marked). The material of the bit line layer 52 and the bit line contact plug 51 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride ( TaN), one or more of metal silicides, metal alloys.

The channel layer 37 and the buried layer 38 shown in FIGS. 12 a to 18 b are formed after the second conductive layer 43 and the third conductive layer 44 are formed. In another embodiment of the present disclosure, the channel layer 37 and the buried layer 38 are formed before forming the first trench T1, the first trench T1, the second trench T2, The third trenches T3 all penetrate the channel layer 37 , as shown in FIGS. 19 a to 25 b .

Specifically, as shown in FIG. 19a to FIG. 19b, before forming the first trench T1, a plurality of rows extending along the first direction and extending along the second direction are formed on the first insulating layer 36. The channel layer 37 is distributed and the buried layer 38 is located between a plurality of the channel layers 37 .

Next, as shown in FIGS. 20a to 20b , etching the channel layer 37 , the buried layer 38 and the first insulating layer 36 to form a first trench T1 extending along the second direction, The first trench T1 exposes a plurality of the sacrificial layers 34 .

Referring again to FIGS. 19a to 20b , in an embodiment, the method further includes: forming in the channel layer 37 and the buried layer 38 a channel extending along the second direction and cutting off the channel layer 37 . The first separation layer 39 and the first trench T1 separate the channel layer 37 into discrete active regions AA.

Next, as shown in FIGS. 21 a to 21 b , a plurality of the sacrificial layers 34 are removed through the first trenches T1 to form a plurality of hole structures S1 communicating with the first trenches T1 .

Next, as shown in FIGS. 22 a to 22 b , a first dielectric layer 41 is formed in the plurality of hole structures S1 , and a second dielectric layer 42 is formed in the first trench T1 .

Next, as shown in FIGS. 23a to 23b, the channel layer 37 and the first insulating layer 36 are etched to form a plurality of second trenches T2 exposing the first dielectric layer 41, and a plurality of A third trench T3 exposing the common lower plate 32 , the second trench T2 and the third trench T3 are arranged on both sides of the second dielectric layer 42 .

Next, as shown in FIGS. 24 a to 24 b , a second conductive layer 43 and a third conductive layer 44 are respectively formed in the second trench T2 and the third trench T3 .

Finally, as shown in FIG. 25a to FIG. 25b, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, and the second insulating layer 49 are formed in the same manner as in the previous embodiment. , the bit line contact hole S2, the bit line contact plug 51 and the bit line layer 52, the third dielectric layer 45 covers the channel layer 37, the buried layer 38, the first The separation layer 39 , the second conductive layer 43 , the third conductive layer 44 and the second dielectric layer 42 . The above layers have been introduced in the foregoing embodiments, and will not be repeated here.

It should be noted that those skilled in the art can change the order of the above steps without departing from the protection scope of the present disclosure.

An embodiment of the present disclosure also provides a semiconductor device, as shown in FIG. 18a to FIG. 18b , including: a substrate 20 and a common lower plate 32 on the substrate 20; The isolation layer 33 and the plurality of first dielectric layers 41 extending along the first direction defined by the isolation layer 33, the plurality of first dielectric layers 41 are arranged and distributed along the second direction; the plurality of first conductive layers 35 , respectively located on a plurality of the first dielectric layers 41 and extending along the first direction; a first insulating layer 36 covering the first conductive layer 35 , the first dielectric layer 41 and the isolation layer 33 ; The first insulating layer 36 has a first trench T1 extending along the second direction, and a plurality of second trenches T2 and a plurality of third trenches arranged on both sides of the first trench T1 Groove T3; wherein, the second trench T2 exposes the first dielectric layer 41, and the third trench T3 exposes the common lower plate 32; the second dielectric layer 42, the second conductive layer 43 and the third conductive layer 44 are respectively located in the first trench T1 , the second trench T2 and the third trench T3 .

The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

In an embodiment, the first direction and the second direction are parallel to the surface of the substrate 20 . In some embodiments, the first direction is perpendicular to the second direction. But not limited thereto, the first direction may also be oblique to the second direction.

As shown in FIG. 18 b , the lower surface of the first dielectric layer 41 is in contact with the common lower electrode plate 32 , and the upper surface of the first dielectric layer 41 is flush with the upper surface of the isolation layer 33 . The material of the isolation layer 33 is an insulating material, such as silicon oxide.

In one embodiment, the bottom of the first trench T1 exposes the common lower electrode plate 32, and the sidewall of the first trench T1 exposes a plurality of the first dielectric layers 41, located in the The second dielectric layer 42 in the first trench T1 extends along the second direction and is connected to a plurality of the first dielectric layers 41 . In a specific embodiment, the sidewall of the first trench T1 exposes one of the two ends of the first dielectric layer 41 in the first direction. The material of the first dielectric layer 41 and the material of the second dielectric layer 42 can be high dielectric constant materials, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide , yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate, etc. In one embodiment, the material of the first dielectric layer 41 is the same as that of the second dielectric layer 42 .

In one embodiment, the first trench T1, the plurality of second trenches T2, and the plurality of third trenches T3 are all perpendicular to the surface of the substrate 20, and the second dielectric layer 42 . Both the second conductive layer 43 and the third conductive layer 44 are also perpendicular to the surface of the substrate 20 .

A plurality of the second trenches T2 and a plurality of the third trenches T3 are respectively arranged on both sides of the first trench T1 along the second direction; the number of the second conductive layer 43, The number of the third conductive layers 44 is multiple, and the plurality of second conductive layers 43 and the plurality of third conductive layers 44 are respectively arranged on both sides of the second dielectric layer 42 along the second direction. The multiple second conductive layers 43 are connected to the multiple first conductive layers 35 in one-to-one correspondence, and the multiple third conductive layers 44 are connected to the common lower plate 32 . In one embodiment, the second trench T2 and the third trench T3 are symmetrically arranged on both sides of the first trench T1, and the second conductive layer 43 and the third conductive layer 44 are symmetrically arranged on both sides of the second dielectric layer 42 . The materials of the common lower plate 32, the first conductive layer 35, the second conductive layer 43 and the third conductive layer 44 may include tungsten (W), copper (Cu), titanium (Ti), One or more of tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloys. In one embodiment, the material of the first conductive layer 35, the second conductive layer 43 and the third conductive layer 44 is the same as that of the common lower plate 32, for example, titanium nitride (TiN ).

The common lower plate 32, a plurality of the first conductive layers 35, a plurality of the second conductive layers 43, a plurality of the third conductive layers 44, a plurality of the first dielectric layers 41 and the The second dielectric layer 42 forms a plurality of capacitors C for storing charges, and the plurality of capacitors C are arranged along the second direction. The extending direction of the first conductive layer 35 is different from that of the second conductive layer 43 and the third conductive layer 44, that is, the capacitance C in the embodiment of the present disclosure extends along two different directions, which is different from that in the related art only Compared with the capacitance extending in one direction, the capacitor C provided by the embodiment of the present disclosure has a larger surface area, so that it can have a larger charge storage capacity; at the same time, compared with the capacitor in the related art, the capacitor C in the embodiment of the disclosure The capacitor C may have a smaller depth, so that the semiconductor device can accommodate more capacitors C per unit volume, which can increase the storage density of the semiconductor device. In addition, in the embodiment of the present disclosure, there is no need to provide a support structure for supporting the capacitors C, and multiple capacitors C have the same common lower plate 32 , which simplifies the manufacturing process of the semiconductor device.

A plurality of capacitors C may also be arranged in an array. In an embodiment, the plurality of capacitors C are respectively arranged in an array along the first direction and the second direction. In some embodiments, in the first direction, the two ends of the first conductive layer 35 are indented inwardly relative to the two ends of the first dielectric layer 41, thus avoiding the The first conductive layer 35 of one of the two capacitors C adjacent in the direction is connected to the third conductive layer 44 of the other; in the second direction, the first Both ends of the conductive layer 35 protrude outward relative to both ends of the first dielectric layer 41 , so that the first conductive layer 35 has a larger surface area, which increases the charge storage capacity of the capacitor C.

In one embodiment, the semiconductor device further includes an interlayer insulating layer 31, and the interlayer insulating layer 31 is located under the common lower plate 32 for electrically isolating the substrate 20 from the common lower plate. plate 32. The material of the interlayer insulating layer 31 may be oxide, for example, silicon oxide.

In an embodiment, the semiconductor device further includes: a plurality of channel layers 37 extending along the first direction located on the first insulating layer 36 and a plurality of channel layers 37 located between the plurality of channel layers 37 The buried layer 38 and the plurality of channel layers 37 are arranged along the second direction.

As shown in the figure, in a specific embodiment, the channel layer 37 is located above the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42, and the channel layer 37 is in contact with the second conductive layer 43 and the third conductive layer 44; the semiconductor device further includes: a first separation layer 39 extending along the second direction, a second separation layer 53, the first The separation layer 39 and the second separation layer 53 are located in the channel layer 37 and the buried layer 38 and cut off a plurality of the channel layers 37, the first separation layer 39 and the second separation layer 53 divides the channel layer 37 into a plurality of active regions AA; wherein, the second separation layer 53 covers the second dielectric layer 42 . There are multiple active areas AA, and the multiple active areas AA are arranged along the second direction. In a more specific embodiment, projections of the second spacer layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.

In one embodiment, the active region AA includes a first source/drain doped region (not marked) located at one end of the active region AA and adjacent to the first spacer layer 39 , located at the The other end of the active region AA and the second source/drain doped region (unmarked) in contact with the second conductive layer 43, the first source/drain doped region (unmarked) and the second Source/drain doped regions (not marked) can be formed in the active region AA by means of ion implantation. In a specific embodiment, the first source/drain doped region (not marked) and the second source/drain doped region (not marked) have the same conductivity type, such as n-type. In a more specific embodiment, the middle region of the active region AA has p-type doping.

In an embodiment, the semiconductor device further includes: a third dielectric layer 45 covering the channel layer 37 and the buried layer 38; word lines extending along the second direction layer 47 , the word line layer 47 is located on the third dielectric layer 45 ; a fourth dielectric layer 48 , the fourth dielectric layer 48 covers the third dielectric layer 45 and the word line layer 47 .

In one embodiment, the third dielectric layer 45 covers both the first separation layer 39 and the second separation layer 53 . The material of the third dielectric layer 45 may include oxide, such as silicon oxide.

In one embodiment, the word line layer 47 is located between the first spacer layer 39 and the second conductive layer 43, and the first conductive layer 35 and the first dielectric layer 41 are located between the word line Under the line layer 47, the space under the word line layer 47 can be utilized, which improves the space utilization rate of the semiconductor device and further increases the storage density of the semiconductor device. In a specific embodiment, the word line layer 47 is disposed above the middle region of the active region AA, and the first source/drain doped region (not marked) and the second source/drain Doped regions (not labeled) are separated. The material of the word line layer 47 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy one or more of. In one embodiment, the word line layer 47 includes a first word line sublayer 471 and a second word line sublayer 472 located on the first word line sublayer 471, the first word line sublayer 471 It is different from the material of the second word line sublayer 472 . The material of the fourth dielectric layer 48 includes but not limited to nitride, such as silicon nitride, which is used to protect the third dielectric layer 45 and the word line layer 47 .

In an embodiment, the semiconductor device further includes: a second insulating layer 49 covering the fourth dielectric layer 48; a plurality of bit line layers 52 extending along the first direction, Located on the second insulating layer 49 and arranged along the second direction; a bit line contact plug 51 , the bit line contact plug 51 is connected to the bit line layer 52 and the channel layer 37 .

Here, the bit line contact plug 51 is located between the first spacer layer 39 and the word line layer 47, and the bit line layer 52 is connected to the active area AA through the bit line contact plug 51. touch. In one embodiment, in the first direction, there are multiple active areas AA, and each bit line layer 52 is connected to multiple active areas AA. In a specific embodiment, the bit line layer 52 is connected to the first source/drain doped region (not marked). The material of the bit line layer 52 and the bit line contact plug 51 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride ( TaN), one or more of metal silicides, metal alloys.

The channel layer 37 and the buried layer 38 shown in FIGS. 18 a to 18 b are formed after the second conductive layer 43 and the third conductive layer 44 are formed. In another embodiment of the present disclosure, the channel layer 37 and the buried layer 38 may also be formed before forming the first trench T1 , as shown in FIGS. 25 a to 25 b . In this embodiment, before forming the first trench T1, the channel layer 37 and the buried layer 38 are formed on the first insulating layer 36, and then the first trench T1, The first dielectric layer 41, the second dielectric layer 42, the second trench T2, the third trench T3, the second conductive layer 43 and the third conductive layer 44, the The first trench T1, the second trench T2, and the third trench T3 all penetrate the channel layer 37; the semiconductor device further includes: a first separation layer 39 extending along the second direction , the first spacer layer 39 is located in the channel layer 37 and the buried layer 38 and cuts off a plurality of the channel layers 37, the first spacer layer 39 and the first trench T1 separate the The channel layer 37 is divided into discrete active regions AA; finally, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, the The second insulating layer 49 , the bit line contact plug 51 and the bit line layer 52 , the third dielectric layer 45 covers the channel layer 37 , the buried layer 38 , and the first spacer layer 39 , the second conductive layer 43 , the third conductive layer 44 and the second dielectric layer 42 . The above layers have been introduced in the foregoing embodiments, and will not be repeated here.

An embodiment of the present disclosure also provides a stacked device, as shown in FIG. 26 , including: a substrate 20 and a plurality of storage structures 30 stacked on the substrate 20; the storage structures 30 include: a common lower plate 32; the isolation layer 33 located on the common lower plate 32 and the plurality of first dielectric layers 41 extending along the first direction defined by the isolation layer 33, and the plurality of first dielectric layers 41 extending along the second direction direction arrangement and distribution; a plurality of first conductive layers 35 are respectively located on a plurality of the first dielectric layers 41 and extend along the first direction; a first insulating layer 36 covers the first conductive layers 35, the The first dielectric layer 41 and the isolation layer 33; the first insulating layer 36 has a first trench T1 extending along the second direction, and a plurality of trenches arranged on both sides of the first trench T1 A second trench T2 and a plurality of third trenches T3; wherein, the second trench T2 exposes the first dielectric layer 41, and the third trench T3 exposes the common lower plate 32; The second dielectric layer 42 , the second conductive layer 43 and the third conductive layer 44 are located in the first trench T1 , the second trench T2 and the third trench T3 respectively. In the embodiment of the present disclosure, a plurality of storage structures 30 are stacked on the substrate 20, and the plurality of storage structures 30 are separated by an interlayer insulating layer 31 (for example, a silicon oxide layer), and the stacked storage structures 30 are improved. The integration and storage density of memory devices.

It should be noted that the above descriptions are only optional embodiments of the present disclosure, and are not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure, etc. , should be included within the protection scope of the present disclosure.

Claims (15)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a common bottom plate on the substrate;

forming an isolation layer and a plurality of sacrificial layers which are defined by the isolation layer and extend along a first direction on the shared lower polar plate, wherein the sacrificial layers are distributed in a second direction;

forming a plurality of first conductive layers extending in the first direction on the plurality of sacrificial layers;

forming a first insulating layer on the first conductive layer, the sacrificial layer and the isolation layer;

etching the first insulating layer to form a first trench extending along the second direction, wherein the first trench exposes a plurality of the sacrificial layers;

removing the sacrificial layers through the first grooves to form a plurality of hole structures communicated with the first grooves;

forming a first dielectric layer in the hole structures and forming a second dielectric layer in the first groove;

Etching the first insulating layer to form a plurality of second grooves exposing the first dielectric layer and a plurality of third grooves exposing the common lower electrode plate, wherein the second grooves and the third grooves are arranged on two sides of the second dielectric layer;

and forming a second conductive layer and a third conductive layer in the second groove and the third groove respectively.

2. The method of manufacturing of claim 1, wherein removing the plurality of sacrificial layers through the first trench comprises: introducing etching liquid into the first groove, wherein the etching liquid removes the plurality of sacrificial layers; wherein the etching rate of the sacrificial layer is greater than the etching rate of the isolation layer.

3. The manufacturing method according to claim 1, wherein after forming the first insulating layer, the method further comprises:

a plurality of channel layers extending in the first direction and a buried layer located between the plurality of channel layers are formed on the first insulating layer, the plurality of channel layers being arranged in the second direction.

4. The method of manufacturing according to claim 3, wherein the channel layer and the buried layer are formed before the first trench is formed, and the first trench, the second trench, and the third trench each penetrate through the channel layer; the method further comprises the steps of:

A first separation layer is formed within the channel layer and the buried layer extending in the second direction and cutting off the channel layer, the first separation layer and the first trench separating the channel layer into discrete active regions.

5. The manufacturing method according to claim 3, wherein the channel layer and the buried layer are formed after the second conductive layer and the third conductive layer are formed, the channel layer and the buried layer cover the first insulating layer, the second conductive layer, the third conductive layer, and the second dielectric layer, and the channel layer is in contact with the second conductive layer and the third conductive layer; the method further comprises the steps of:

forming first and second separation layers within the channel layer and the buried layer, the first and second separation layers separating the channel layer into discrete active regions, the first and second separation layers extending in the second direction and cutting off the plurality of channel layers; wherein the second separation layer covers the second dielectric layer.

6. A method of manufacturing according to claim 3, wherein the method further comprises:

forming a third dielectric layer on the channel layer and the buried layer, and forming a word line material layer on the third dielectric layer;

Etching the word line material layer to form a word line layer extending along the second direction;

and forming a fourth dielectric layer on the substrate, wherein the fourth dielectric layer covers the third dielectric layer and the word line layer.

7. The method of manufacturing according to claim 6, further comprising:

forming a second insulating layer on the fourth dielectric layer;

etching the second insulating layer, the fourth dielectric layer and the third dielectric layer until the channel layer is exposed, so as to form a plurality of bit line contact holes which are distributed along the second direction;

forming a bit line contact plug in the bit line contact hole;

and forming a plurality of bit line layers extending along the first direction on the bit line contact plug and the second insulating layer, wherein the plurality of bit line layers are arranged along the second direction.

8. A semiconductor device, the semiconductor device comprising:

a substrate and a common bottom plate on the substrate;

the isolation layers are positioned on the shared lower polar plate, the first dielectric layers are limited by the isolation layers and extend along a first direction, and the first dielectric layers are distributed in a second direction;

a plurality of first conductive layers respectively located on the plurality of first dielectric layers and extending along the first direction;

A first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer is internally provided with a first groove extending along the second direction, a plurality of second grooves and a plurality of third grooves which are arranged on two sides of the first groove; wherein the second trench exposes the first dielectric layer, and the third trench exposes the common lower plate;

the second dielectric layer, the second conductive layer and the third conductive layer are respectively positioned in the first groove, the second groove and the third groove.

9. The semiconductor device according to claim 8, wherein both ends of the first conductive layer are recessed with respect to both ends of the first dielectric layer in the first direction; in the second direction, both ends of the first conductive layer protrude outward with respect to both ends of the first dielectric layer.

10. The semiconductor device according to claim 8, wherein the semiconductor device further comprises: a plurality of channel layers extending in the first direction on the first insulating layer, and a buried layer between the plurality of channel layers, the plurality of channel layers being arranged in the second direction.

11. The semiconductor device of claim 10, wherein the first trench, the second trench, and the third trench each extend through the channel layer; the semiconductor device further includes: a first separation layer extending in the second direction, the first separation layer being located within the channel layer and the buried layer and cutting off a plurality of the channel layers, the first separation layer and the first trench separating the channel layers into discrete active regions.

12. The semiconductor device according to claim 10, wherein the channel layer is over the second conductive layer, the third conductive layer, and the second dielectric layer, the channel layer being in contact with the second conductive layer and the third conductive layer; the semiconductor device further includes: a first separation layer and a second separation layer extending in the second direction, the first separation layer and the second separation layer being located in the channel layer and the buried layer and cutting off the plurality of channel layers, the first separation layer and the second separation layer separating the channel layer into a plurality of active regions; wherein the second separation layer covers the second dielectric layer.

13. The semiconductor device according to claim 10, wherein the semiconductor device further comprises: the third dielectric layer covers the channel layer and the buried layer; a word line layer extending along the second direction, the word line layer being located on the third dielectric layer; and the fourth dielectric layer covers the third dielectric layer and the word line layer.

14. The semiconductor device according to claim 13, wherein the semiconductor device further comprises: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending in the first direction, located on the second insulating layer and arranged in the second direction; and the bit line contact plug is connected with the bit line layer and the channel layer.

15. A stacked device, the stacked device comprising:

a substrate and a plurality of memory structures stacked on the substrate;

the storage structure includes:

sharing a lower polar plate;

the isolation layers are positioned on the shared lower polar plate, the first dielectric layers are limited by the isolation layers and extend along a first direction, and the first dielectric layers are distributed in a second direction;

A plurality of first conductive layers respectively located on the plurality of first dielectric layers and extending along the first direction;

a first insulating layer covering the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer is internally provided with a first groove extending along the second direction, a plurality of second grooves and a plurality of third grooves which are arranged on two sides of the first groove; wherein the second trench exposes the first conductive layer, and the third trench exposes the common lower plate;

the second dielectric layer, the second conductive layer and the third conductive layer are respectively positioned in the first groove, the second groove and the third groove.