CN116684021A - Communication device, communication system, and data transmission method - Google Patents

Abstract

The application discloses a communication device, a communication system and a data transmission method, wherein the communication device comprises: a data communication module for transmitting data signals and/or receiving data signals; the detection module is connected to the control module and used for detecting the pulse edge of the first clock signal and outputting a corresponding enabling signal to the control module, the first clock signal has a first frequency, and the enabling signal is used for enabling the control module when the receiving edge is detected; and the control module is connected to the data transmission module, and is used for detecting the edge of the second clock signal after being enabled by the enabling signal, and controlling the data communication module to transmit the data signal when the y appointed edge of the second clock signal is detected, or controlling the communication module to receive the data signal when the x appointed edge is detected. The communication device can reduce communication errors.

Description

Communication device, communication system, and data transmission method

Technical Field

The present application relates to the field of communications technologies, and in particular, to a communications device, a communications system, and a data transmission method.

Background

Data signal transmission between devices is performed following a specific communication protocol, a signal transmitting device transmits data according to the protocol, and a signal receiving device samples the transmitted data according to the protocol, thereby receiving a signal. In the synchronization signal transmission process, synchronization is performed between the transmitting device and the receiving device by a clock signal.

Please refer to fig. 1, which is a schematic diagram illustrating signal transmission between master and slave devices of a standard I2S protocol.

The I2S master transmits the sampling clock BCLK and the left and right channel clock LRCLK to the I2S slave so that clocks between the two devices are synchronized. Wherein the left and right channel clock LRCLK is used to switch left and right channel DATA, and the clock BCLK is used to control the transmission and sampling of the DATA.

Please refer to fig. 2, which is a timing diagram of data transmission and sampling of the I2S protocol. In the I2S protocol, it is prescribed that the transmitting device transmits DATA at the falling edge of the sampling clock BCLK, the DATA level is changed, flipped from the level to the high level, or flipped from the high level to the low level; and the receiving device samples the data at the rising edge of the sampling clock BCLK. Of course, it may be set that the transmitting apparatus transmits data on the rising edge of the sampling clock BCLK and the receiving apparatus transmits data on the falling edge of BCLK.

When there is a large equivalent capacitance on the path between two or more devices that are communicating, the rising and falling edges of the clock and data signals will be slowed down; or when there is a difference between the routing delay of the clock signal and the routing delay of the DATA signal, when the rising edge (sampling time) of the clock signal comes, the level of the DATA signal is not stable yet, so that the sampled DATA is wrong, referring to fig. 3, the timing sequence of the DATA relative to the sampling clock BCLK exceeds the protocol specified range, and the receiving device cannot sample the DATA normally, so that communication errors are caused.

How to avoid the above situation and further improve the communication reliability is a problem to be solved at present.

Disclosure of Invention

In view of the above, the present application provides a communication device, a communication system, and a data transmission method, so as to solve the problem that the existing communication is prone to error.

The present application provides a communication device including: the device comprises a data communication module, a detection module and a control module; the data communication module is used for sending and/or receiving data signals; the detection module is connected to the control module and is used for detecting the pulse edge of a first clock signal and outputting a corresponding enabling signal to the control module, the first clock signal has a first frequency, and the enabling signal is used for enabling the control module when the receiving edge is detected; the control module is connected to the data communication module and is used for detecting the edge of a second clock signal after being enabled by the enabling signal, and the second clock signal has a second frequency which is larger than the first frequency; the control module is used for controlling the data communication module to send a data signal when the y-th appointed edge of the second clock signal is detected, or controlling the data communication module to receive the data signal when the x-th appointed edge of the second clock signal is detected; wherein x and y are integers greater than or equal to 0 and are each less than 1/2 of the ratio of the second frequency to the first frequency.

Optionally, the detection module includes: the device comprises a trigger unit, a delay unit and an operation unit; the clock end of the trigger unit is used for receiving the second clock signal, the input end of the trigger unit is used for inputting the first clock signal, and the trigger unit is used for latching the current level of the first clock signal and outputting the current level at the trigger edge moment of the second clock signal; the delay unit is connected to the output end of the trigger unit and is used for delaying the output signal of the trigger unit and outputting the delayed output signal at the trigger edge moment of the second clock signal, wherein the delay time is the period of the second clock signal; the operation unit is connected to the output end of the delay unit and the output end of the trigger unit, and is used for performing an AND operation on one level of the current level of the first clock signal output by the trigger unit and the delay level of the last period output by the delay unit after inverting the other level.

Optionally, the delay unit includes a register.

Optionally, the operation unit includes an and gate, one input end of the and gate and an input end of the not gate are connected to an output end of the trigger unit and an output end of the delay unit, respectively, and an output end of the not gate is connected to another input end of the and gate.

Optionally, the control module includes a counter, an enable end of the counter is connected to the detection module, an input end of the counter is used for inputting the second clock signal, and the counter is used for counting a designated edge of the second clock signal after receiving the enable signal output by the detection module, and outputting a count value.

Optionally, the control module further includes a register and a comparator, where the register is used to store the value of y and/or x, and the comparator is connected to the output ends of the register and the counter, and is used to compare the count value output by the counter with the value of y and/or x, and when the count value reaches the value of y or x, output a corresponding data transmission control signal or a data reception control signal.

Optionally, the ratio of the second frequency to the first frequency is greater than or equal to 2.

The application also provides a data transmission method, which comprises the following steps: detecting a designated edge of a second clock signal after detecting a receiving edge of a pulse of a first clock signal, the second clock having a second frequency, the first clock having a first frequency, the second frequency being greater than the first frequency; transmitting data at a y-th designated edge of the second clock signal, wherein y is an integer greater than or equal to 0 and is less than 1/2 of a ratio of the second frequency to the first frequency; or, receiving data at an x-th designated edge of the second clock signal, wherein x is an integer greater than or equal to 0, and is less than 1/2 of the ratio of the second frequency to the first frequency.

Optionally, the second frequency is greater than or equal to 2 times the first frequency.

Optionally, the method for detecting the receiving edge of the first clock signal includes: latching and outputting the current level of the first clock signal at the trigger edge moment of the second clock signal; delaying the current level of the first clock signal and outputting the delayed current level at the trigger edge moment of the second clock signal, wherein the delay time is the period of the second clock signal; and inverting one level of the first clock signal in the current period and the delayed level of the first clock signal in the delayed previous period, and then performing AND operation with the other level, wherein the operation result of the AND operation is taken as a detection result.

The present application also provides a communication system comprising: a communication device as claimed in any preceding claim.

Optionally, when the communication device is configured to send data, the communication system further includes: and the data receiving device is in signal connection with the communication device and is used for receiving the data signal sent by the communication device at the moment of the receiving edge of the first clock signal.

Optionally, when the communication device is configured to receive data, the communication system further includes: and the data transmitting device is connected to the communication device in a signal way and is used for transmitting a data signal to the communication device at the moment of the transmitting edge of the first clock signal.

The communication equipment controls the data receiving and transmitting through two clock signals, and comprises a second clock signal with higher frequency and a first clock signal with lower frequency; the first clock signal is a sampling clock when receiving data, after the first clock signal generates a receiving edge corresponding to data sampling and receiving, the appointed edge number of the second clock signal is calculated, and before the first clock signal is overturned, the data is sent and overturned in advance or the data is received after the receiving edge of the first clock signal is delayed, so that the stability time of the sent data can be increased, and the reliability of communication is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of signal transmission between master and slave devices of a standard I2S protocol;

FIG. 2 is a timing diagram of data transmission and sampling for a standard I2S protocol;

FIG. 3 is a timing diagram of sampling clock and data signals when errors occur in standard I2S protocol communications;

fig. 4 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 5 is a schematic structural view of a communication device according to another embodiment of the present application;

fig. 6a is a schematic structural diagram of a detection module of a communication device according to an embodiment of the present application;

fig. 6b is a schematic structural diagram of a detection module of a communication device according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a control module of a communication device according to an embodiment of the present application;

fig. 8 is a schematic structural view of a control module of a communication device according to another embodiment of the present application;

fig. 9 is a schematic structural view of a communication device according to another embodiment of the present application;

fig. 10 is a schematic structural view of a communication device according to another embodiment of the present application;

fig. 11 is a schematic structural view of a communication device according to another embodiment of the present application;

fig. 12 is a schematic structural view of a control module of a communication device according to another embodiment of the present application;

fig. 13 is a schematic structural view of a communication device according to another embodiment of the present application;

fig. 14 is a schematic structural view of a communication device according to another embodiment of the present application;

FIG. 15 is a schematic signal timing diagram of a data transmission process according to an embodiment of the application;

fig. 16 is a signal timing diagram of a data transmission process according to an embodiment of the application.

Detailed Description

As described in the background art, in the communication process of the prior art, a problem of communication errors easily occurs due to a timing difference between a clock and a data signal. According to standard communication protocols, data is transmitted and sampled at half a clock cycle intervals, so that the data must be quickly stabilized within half a cycle after the clock signal edge of the corresponding transmit signal. However, in practical use, due to the influence of various factors such as external wiring, parasitic impedance and the like, the data stabilization time is often longer than half a clock period, which leads to communication errors.

Based on the technical analysis, the application provides the communication equipment, the communication system and the data transmission method, which can increase the stability time of the transmitted data, so that the data is stable when the receiving equipment samples the data, thereby improving the reliability of communication.

The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.

The communication device comprises a detection module, a control module and a data communication module. The communication equipment is provided with a data sending and/or receiving function, and the corresponding communication module is used for sending and/or receiving data. The communication device may also have both data transmission and reception functions, and may be used as a data transmission device or a data reception device. In the communication process, the communication device can be used as a master device or a slave device.

Fig. 4 is a schematic structural diagram of a communication device according to an embodiment of the application. In this embodiment, the communication device is a data transmission device, and in this embodiment, the data communication module includes a data transmission module.

The communication device comprises a detection module 110, a control module 120 and a data transmission module 130.

The data transmitting module 130 is configured to transmit a data signal.

The detection module 110 is connected to the control module 120, and is configured to detect a pulse edge of a first clock signal BCLK, and output a corresponding enable signal pos_edge to the control module 120, where the first clock signal BCLK has a first frequency f1, and the enable signal pos_edge is configured to enable the control module 120 when detecting a receiving edge of the first clock signal BCLK. The clock signal is typically a rectangular pulse signal, each pulse having a rising edge, which refers to a pulse edge that toggles from low to high, and a falling edge, which refers to a pulse edge that toggles from high to low. In the communication protocol, one edge of the first clock signal BCLK pulse is appointed as a receiving edge for controlling the data transmitting operation; the other edge is a transmitting edge for controlling the data receiving operation.

The control module 120 is connected to the data sending module 130, and is configured to detect an edge of a second clock signal MCLK after being enabled by the enable signal pos_edge, and control the data sending module 130 to send a data signal when a y-th designated edge of the second clock signal MCLK is set, where y is an integer greater than or equal to 0, the second clock signal MCLK has a second frequency f2, where the second frequency f2 is greater than the first frequency f1, and y is less than 1/2 of a ratio of the second frequency to the first frequency, that is, y is less than or equal to f2/2f1. y=0, means that the data transmission module 130 is controlled to transmit a data signal upon detecting a pulse edge of the first clock signal BCLK without waiting for a designated edge of the second clock signal MCLK to be generated. The designated edge refers to one of the rising edge or the falling edge of the pulse edge of the second clock signal MCLK, which may be the rising edge as the designated edge or the falling edge as the designated edge, and this may be set according to the logic requirement of the circuit.

The communication device performs data transmission at the y-th designated edge of the second clock signal MCLK after the reception edge of the first clock signal BCLK. Since y is smaller than 1/2 of the ratio of the second frequency f2 to the first frequency f1, at the designated edge of the y-th second clock signal MCLK, the other edge of the first clock signal BCLK pulse, i.e., the transmitting edge, is not yet generated, ensuring that the data transmission timing is before the level of the first clock signal BLCK is flipped again. When the receiving device will sample data at the next receiving edge, the data stabilization time is longer than half the period of the first clock signal BCLK, and the data stabilization time is improved, so that the communication error probability is reduced.

In some embodiments, the enable signal pos_edge may be a digital signal having a high level and a low level. The control module 120 is generally enabled when the enable signal pos_edge is high, i.e., when the receiving edge of the first clock signal BCLK is detected, correspondingly generating a high level of the enable signal pos_edge. In other embodiments, the control module 120 may be enabled low. The receiving edge of the first clock signal BCLK may be a rising edge or a falling edge. The correspondence between the receiving edge and the high and low levels of the enable signal may be set as needed, and the receiving edge may also be used as an edge for triggering the receiving device to receive data.

Taking the I2S communication protocol as an example, the first clock signal BCLK may be a sampling clock signal, and the receiving device side of the communication may perform data sampling at the receiving edge time of the first clock signal BCLK.

In other embodiments, the communication device may also support other communication protocols supporting the same first clock signal BCLK as the sampling clock signal, such as the SPI protocol, the I2C protocol, etc.

Fig. 5 is a schematic structural diagram of a communication device according to another embodiment of the application.

In this embodiment, the detection module 110 receives the first clock signal BCLK and the second clock signal MCLK simultaneously. The first clock signal BCLK is used as an input signal, the second clock signal MCLK is used as a sampling clock, and the first clock signal BCLK is sampled, so that the edge of the first clock signal BCLK is detected. For example, in the two sampling steps, the level obtained by sampling is changed from 0 to 1, and then a rising edge is detected; if the level obtained by sampling is changed from 1 to 0 in the front and back sampling, a falling edge is detected.

According to the sampling theorem, the frequency of the sampling clock needs to be 2 times or more of the frequency of the sampled clock. Therefore, in the embodiment of the present application, in order to accurately detect the edge of the first clock signal BCLK, the second frequency f2 of the second clock signal MCLK is greater than or equal to the first frequency f1 which is 2 times greater, that is, f2+.2f1.

When the first clock signal BCLK and the second clock signal MCLK are synchronous clock signals, MCLK and BCLK have the same phase, i.e., each rising/falling edge of BCLK corresponds to a rising edge or a falling edge of MCLK. Therefore, MCLK does not need to sample and synchronize BCLK to know the edge generation time point of BCLK, and therefore, only f2 is more than or equal to 2f1 to meet the requirement.

When the first clock signal BCLK and the second clock signal MCLK are asynchronous clock signals crossing clock domains, the second clock signal MCLK needs to be used for grabbing the first clock signal BCLK 2 times for detection, so as to reduce metastability of the digital circuit. At this time, the requirement f2 is not less than 4f1.

Fig. 6a is a schematic structural diagram of a detection module according to an embodiment of the application.

In this embodiment, the detection module 110 includes a trigger unit 111, a delay unit 112, and an operation unit 113.

The clock terminal clk of the trigger unit 111 is used for receiving the second clock signal MCLK, the input terminal in of the trigger unit 111 is used for inputting the first clock signal BCLK, and the trigger unit 111 is used for latching and outputting the current level bclk_val of the first clock signal BCLK at the trigger edge time of the second clock signal MCLK.

The delay unit 112 is connected to the output end out of the trigger unit 111 for delaying the output signal of the trigger unit 111 by a delay level BCLK_VAL at the trigger edge time of the second clock signal MCLK _delay The delay time is a period of the second clock signal MCLK.

The operation unit 113 is connected to the output end of the delay unit 112 and the output end out of the trigger unit 111 for outputting the current level BCLK_VAL of the first clock signal BCLK and the delay level BCLK_VAL of the last period of time output by the delay unit 112 _delay In (a) and (b)One performs an and operation with the other after inverting: (-BCLK_VAL _delay )&Bclk_val or bclk_val _delay &(-BCLK_VAL)。

In a specific embodiment, the flip-flop 111 may employ a D flip-flop, and the rising edge of the second clock signal MCLK is used to trigger the D flip-flop to perform data output, that is, when the rising edge of the second clock signal MCLK arrives, the output terminal of the flip-flop 111 outputs the current level of the first clock signal BCLK and holds the current level. In other embodiments, the flip-flop may be triggered to output data by the falling edge of the second clock signal MCLK by adding a logic device or adopting other flip-flop structures.

The delay unit 112 may be controlled by the second clock signal MCLK, and receives the current level bclk_val output from the trigger unit 111 at the first rising edge of the second clock signal MCLK, outputs the level value at the next rising edge of the second clock signal MCLK, delays the input and output by one period time of the second clock signal MCLK, so that the delay unit outputs the delay level bclk_val while the trigger unit 111 outputs the current level bclk_val _delay Delay level bclk_val _delay Corresponds to the level of BCLK at the rising edge of the last period of the second clock signal MCLK.

The operation unit 113 includes an NOT gate INV and an AND gate&. In this embodiment, the AND gate&Is connected to the output of the trigger unit 111, the input of the NOT gate INV is connected to the output of the delay unit 112, and the output of the NOT gate INV is connected to the AND gate&Is provided. Delay level bclk_val output from delay unit 112 _delay Inverted to (-BCLK_VAL) through NOT gate INV _delay ) And the current level bclk_val output from the flip-flop unit 111, and outputs an enable signal pos_edge:

Pos_edge＝(-BCLK_VAL _delay )&BCLK_VAL。

the rising edge of the previous MCLK is taken to a value of 0 and the next 1, at which time BCLK_VAL _delay Bclk_val=1, and BCLK level changes from 0 to 1, corresponding to the rising edge of BCLK, at which point pos_edge=1. In the present application, a logic 0 represents a low level, and a logic 1 represents a high level. In other cases, pos_edge= (-bclk_val) _delay )&Bclk_val=0. In this embodiment, the rising edge of the first clock signal BCLK is used as the receiving edge, and when the rising edge is detected, the operation result pos_edge=1, and the control enable signal pos_edge controls the control module 120 to enable.

In other embodiments, referring to fig. 6b, the non-gate INV may be connected to the output end of the trigger unit 111, and the output end of the delay unit 112 may be directly connected to the and gate&. At this time, the enable signal pos_edge=bclk_val _delay &(-bclk_val). The rising edge of the previous MCLK is taken to a value of 1 and the next to 0, at which time BCLK_VAL _delay =1, bclk_val=0, and BCLK level changes from 1 to 0, corresponding to the falling edge of BCLK, at which point pos_edge=1, controlling the control module 120 to enable. In this embodiment, the falling edge of the first clock signal BCLK is taken as the receiving edge.

In other embodiments, the not gate INV may be further disposed at the input end in of the trigger unit 111, and the first clock signal BCLK is inverted and then detected, so that the detection of the falling edge of BCLK can be also realized.

Fig. 7 is a schematic structural diagram of a control module 120 according to an embodiment of the application.

IN this embodiment, the control module 120 has an enable terminal EN for receiving the enable signal pos_edge outputted from the detection module 110, an input terminal IN for inputting the second clock signal MCLK, and a value input terminal THRES for inputting the value of y, and an output terminal out for outputting a data transmission control signal when detecting the designated edge of the y-th MCLK.

Referring to fig. 8, an internal structure of the control module 120 is shown in an embodiment.

The control module 120 includes a counter 121, an enable terminal EN of the counter 121 is connected to the detection module 110, an input terminal IN of the counter 121 is used as an input terminal of the control module 120 for inputting the second clock signal MCLK, and the counter 121 is used for counting a designated edge of the second clock signal MCLK when enabled by an enable signal pos_edge outputted by the detection module 110 and outputting a count value.

The control module 120 further includes a register 122 and a comparator 123, the register 122 is configured to store a value of y, the comparator 123 is connected to the output ends of the register 122 and the counter 121, and is configured to compare a count value output by the counter 121 with the value of y, and when the count value reaches the value of y, the comparator 123 sends a data transmission control signal to the data transmission module 130. The data transmission control signal corresponds to a high level of the control module 120 output signal.

The data transmission module 130 transmits a data signal after receiving the data transmission control signal.

Fig. 9 is a schematic structural diagram of a communication device according to another embodiment of the present application. In this embodiment, the communication device further comprises a data receiving module 140. The communication device may be configured to receive data and may also be configured to transmit data, or may be configured to operate in duplex, with both the receiving and transmitting of data.

The data receiving module 140 is configured to receive a data signal sent by an external transmitting terminal at a receiving edge time of the first clock signal BCLK. The transmitting edge and the receiving edge of the first clock signal BCLK are respectively pulse edges of two different directions of a single pulse.

Please refer to fig. 10 and 11, which are schematic diagrams of a communication device according to another two embodiments of the present application. The communication device described in fig. 10 and 11 is a data receiving device, and the data communication module includes a data receiving module 230.

The communication device comprises a detection module 110 and a control module 220, a data receiving module 230. Unlike the foregoing embodiments, except that the data communication module is the data receiving module 230, the control module 220 is configured to detect an edge of the second clock signal MCLK after being enabled by the enable signal pos_edge, and control the data receiving module 230 to receive the data signal when an xth designated edge of the second clock signal MCLK is detected, where x is an integer greater than or equal to 0 and x is less than 1/2 of a ratio of the second frequency to the first frequency, i.e., y is less than or equal to f2/2f1.

The communication device performs data reception at the x-th designated edge of the second clock signal MCLK after the reception edge of the first clock signal BCLK. Since x is smaller than 1/2 of the ratio of the second frequency f2 to the first frequency f1, another edge (i.e., a transmitting edge) of the first clock signal BCLK pulse is not generated at the designated edge of the xth second clock signal MCLK, ensuring that the data receiving time is before the level of the first clock signal BLCK is flipped again. The external transmitting terminal device transmits data at the transmitting edge of the first clock signal BCLK, and the communication device of the embodiment receives data at the x-th designated edge of the second clock signal MCLK after the receiving edge of the first clock signal BCLK, so that the data stability time transmitted by the transmitting terminal is longer than half the period of the first clock signal BCLK, and the data stability time is improved, thereby reducing the communication error probability. Preferably, x is equal to or greater than 1, so as to ensure that the data receiving time is delayed from the transmitting edge of the first clock signal BCLK, so as to improve the data stabilizing time. In some embodiments, x may also be equal to 0, upon detection of a receive edge of the first clock signal BCLK, data reception occurs.

Referring to fig. 12, a schematic diagram of an implementation structure of the control module 220 when the communication device is used as a data transmission device is shown.

IN this embodiment, the control module 220 has an enable terminal EN for receiving the enable signal pos_edge outputted from the detection module 110, an input terminal IN for inputting the second clock signal MCLK, and a value input terminal THRES for inputting the value of x, and an output terminal out for outputting a data reception control signal when detecting the designated edge of the xth MCLK.

The internal structure of the control module 220 may be as shown in fig. 8, wherein the register is used for registering x as data, the comparator compares the count value output by the counter with the value of x, and when the count value reaches the value of x, the comparator sends a data receiving control signal to the data sending module 230.

Fig. 13 is a schematic structural diagram of a communication device according to another embodiment of the present application. In this embodiment, the communication device further includes a data sending module 240, where the communication device may be configured to receive data and may also be configured to send data, or may also be configured to operate in duplex, while receiving and sending data.

The data transmitting module 240 is configured to transmit a data signal at a transmission edge time of the first clock signal BCLK.

Fig. 14 is a schematic structural diagram of a communication device according to another embodiment of the present application.

In this embodiment, the data communication module of the communication device includes both a data sending module 130 and a data receiving module 230, and a corresponding control module 120 and control module 220.

The control module 120 outputs a data transmission control signal CTR1 to the data transmission module 130 at the y-th designated edge of the second clock signal MCLK after being enabled by pos_edge, and controls the data transmission module 130 to transmit data.

The control module 220 outputs a data reception control signal CTR2 to the data transmission module 230 at an x-th designated edge of the second clock signal MCLK after being enabled by pos_edge, controls the data reception module 230 to receive the data signal, and performs sampling.

The transmission or reception path thereof may be selected to operate according to circumstances, or both paths may be operated simultaneously to correspond to the reception device, the transmission device, or the simultaneous data reception and transmission device, respectively, which can improve the reliability of the communication process in each case.

The embodiment of the application also provides a data transmission method, which comprises the following steps: detecting a designated edge of the second clock signal MCLK after detecting a receiving edge of the pulse of the first clock signal BCLK; transmitting data at a y-th designated edge of the second clock signal; or at the x-th designated edge, receiving data; wherein y is an integer of 0 or more, and x is an integer of 0 or more; the first clock signal BCLK has a first frequency f1, the second clock signal has a second frequency f2, f1 > f2, and x, y are both less than f2/2f1.

In some embodiments, when the first clock signal BCLK and the second clock signal MCLK are synchronous clock signals, f2++2f1; when the first clock signal BCLK and the second clock signal MCLK are asynchronous clock signals crossing clock domains, the second clock signal MCLK needs to be used for grabbing the first clock signal BCLK 2 times for detection, so as to reduce metastability of the digital circuit. At this time, the requirement f2 is not less than 4f1.

In some embodiments, a method of detecting a receive edge of the first clock signal comprises: latching and outputting a current level bclk_val of the first clock signal BCLK at a trigger edge timing of the second clock signal MCLK; at the trigger edge time of the second clock signal MCLK, the current level of the first clock signal BCLK is delayed and then the delayed level BCLK_VAL is outputted _delay The delay time is a period of the second clock signal MCLK; for the current level BCLK_VAL of the first clock signal BCLK in the current period and the delayed level BCLK_VAL of the delayed last period _delay And operation is carried out on one level of the three-phase voltage source circuit and the other level after the phase inversion: (-BCLK_VAL _delay )&Bclk_val or bclk_val _delay &(-bclk_val) with the result of the and operation as the detection result.

When the receiving edge of the first clock signal is a rising edge, an operation (-BCLK_VAL) is performed _delay )&When BCLK_VAL is the rising edge, the operation result is 1; when the receiving edge of the first clock signal is a falling edge, the operation BCLK_VAL is performed _delay &(-BCLK_VAL), the result of the operation is 1 only when the rising edge occurs. Therefore, whether the first clock signal has a receiving edge or not can be judged according to the operation result.

The above communication method may be implemented by the communication device in the foregoing embodiment, and related features may be cited with each other, which is not described herein.

The embodiment of the application also provides a communication system, which comprises: the communication device as in any above embodiments.

In some embodiments, when the communication device in the communication system is used as a transmitting end for transmitting data, the communication system may further include a data receiving device at the other end, where the data receiving device is signal-connected to the communication device, and is configured to receive, at a time of a receiving edge of the first clock signal, a data signal transmitted by the communication device.

When a communication device serving as a data transmission is used as a master device, the communication device synchronously transmits a first clock signal BCLK to the data reception device. The communication device receives a first clock signal BCLK transmitted by the data reception device when the data reception device is a master device.

In some embodiments, the communication device is also provided with a data receiving module, and has data sending and receiving functions. The communication system may employ two communication devices described in the above embodiments, one of which serves as a transmitting device and the other of which serves as a receiving device.

In some embodiments, when the communication device in the communication system is used as a receiving end for receiving data, the communication system may further include a data transmitting device at the other end, where the data transmitting device is signal-connected to the communication device, and is configured to transmit a data signal to the communication device at a time of a transmission edge of the first clock signal.

The communication system comprises the communication device in the embodiment, and the communication device can send data signals in advance or receive data signals in a delayed manner, so that the data stabilization time is improved, and errors of data receiving and sampling are avoided. In the communication process, the data receiving or transmitting device on the other side can be adapted to the data receiving or transmitting device communicating according to the standard protocol without adjusting the data receiving or transmitting device on the other side.

The embodiment of the application also provides a data transmission method, which comprises the following steps: the data signal is transmitted and/or received using the data transmission method described in the above embodiments. The data transmission method improves the communication reliability by changing the data transmission and/or receiving method.

Fig. 15 is a schematic signal timing diagram of a data transmission process according to an embodiment of the application.

In FIG. 15, DATA_a is that the I2S connection parasitic parameter is larger in a certain product, resulting in a slower flip of the transmitted DATA DATA level relative to the rising edge of the first clock signal BCLK. According to the protocol, data is sampled at the rising edge of the first clock signal BCLK, and data is transmitted at the falling edge, the data is not stable when the data is sampled at the rising edge, and the sampled data is in error.

And data_b is DATA after using the DATA transmission method of the present application: after adding a second clock signal MCLK having a higher frequency than the first clock signal BCLK, rising edges of the first clock signal BCLK are detected in the 1 st and 2 nd periods of the second clock signal MCLK, wherein rising edges of MCLK of sequence number 1 and sequence number 2 are used to detect rising edges of BCLK. In this embodiment, the transmission method is improved, the frequency of the second clock signal MCLK is 10 times that of the first clock signal BCLK, and y=2 is configured, that is, the transmitting end transmits new data at the 2 nd MCLK rising edge (the MCLK rising edge corresponding to the sequence number 4) after the rising edge of the first clock signal BCLK. It can thus be seen that DATA_b is issued on the rising edge of MCLK with sequence number 4.

Comparing data_a and data_b shows that DATA of data_b is transmitted ahead of time Δt1, and that there is time (Δt1+t1/2) to stabilize DATA, and T1 is a period of the first clock signal BCLK, so that DATA can be stably sampled when a rising edge of BCLK arrives (see bold dotted line).

Y=1 (refer to the second BCLK period shown in fig. 15) may also be set, and the 1 st MCLK rising edge (i.e., the MCLK rising edge of sequence number 9) after the rising edge of BCLK is detected in the MCLK rising edge period of sequence numbers 7 and 8 transmits data, and at this time, the data can be seen to be increased by more stable time Δt2.

In other embodiments, y=0, or y=3 or other values less than or equal to f2/2f1 may also be set. In the communication process, y can be configured to be different values, and the value of y can be adjusted at any time in the communication process according to the change of external parasitic impedance and the change of the stabilization time required by data. Since the MCLK frequency is much greater than the BCLK frequency, the transmitted DATA DATA can be guaranteed to flip quickly to the next new value after being sampled, thereby greatly increasing the settling time.

Fig. 16 is a schematic signal timing diagram of a data transmission process according to an embodiment of the application.

And DATA is DATA after using the DATA transmission method of the present application, which improves the DATA receiving process, the rising edge of the first clock signal BCLK is detected in the period in which the rising edges of the serial numbers 7 and 8 of the second clock signal MCLK are located. The frequency of the second clock signal MCLK is 10 times that of the first clock signal BCLK, and x=1 is configured, that is, the transmitting end receives data after detecting and determining the rising edge of the first clock signal BCLK and delaying until the last 1 rising edge of MCLK (corresponding to the rising edge of MCLK with the sequence number 9), and the data stabilization time is increased by Δt3. Thus, by delaying the reception of data, the data stabilization time is improved, thereby improving the reliability of communication.

The foregoing embodiments of the present application are not limited to the above embodiments, but are intended to be included within the scope of the present application as defined by the appended claims and their equivalents.

Claims (13)

1. A communication device, comprising: the device comprises a data communication module, a detection module and a control module;

the data communication module is used for sending and/or receiving data signals;

the detection module is connected to the control module and is used for detecting the pulse edge of a first clock signal and outputting a corresponding enabling signal to the control module, the first clock signal has a first frequency, and the enabling signal is used for enabling the control module when the receiving edge is detected;

the control module is connected to the data communication module and is used for detecting the edge of a second clock signal after being enabled by the enabling signal, and the second clock signal has a second frequency which is larger than the first frequency; the control module is used for controlling the data communication module to send a data signal when the y-th appointed edge of the second clock signal is detected, or controlling the data communication module to receive the data signal when the x-th appointed edge of the second clock signal is detected; wherein x and y are integers greater than or equal to 0 and are each less than 1/2 of the ratio of the second frequency to the first frequency.

2. The communication device of claim 1, wherein the detection module comprises: the device comprises a trigger unit, a delay unit and an operation unit;

the clock end of the trigger unit is used for receiving the second clock signal, the input end of the trigger unit is used for inputting the first clock signal, and the trigger unit is used for latching the current level of the first clock signal and outputting the current level at the trigger edge moment of the second clock signal;

the delay unit is connected to the output end of the trigger unit and is used for delaying the output signal of the trigger unit and outputting the delayed output signal at the trigger edge moment of the second clock signal, wherein the delay time is the period of the second clock signal;

the operation unit is connected to the output end of the delay unit and the output end of the trigger unit, and is used for performing an AND operation on one level of the current level of the first clock signal output by the trigger unit and the delay level of the last period output by the delay unit after inverting the other level.

3. The communication device of claim 2, wherein the delay unit comprises a register.

4. The communication device according to claim 2, wherein the operation unit comprises an and gate, one input of the and gate and an input of the not gate being connected to the output of the trigger unit and the output of the delay unit, respectively, and the output of the not gate being connected to the other input of the and gate.

5. The communication device according to claim 1, wherein the control module includes a counter, an enable terminal of the counter is connected to the detection module, an input terminal of the counter is used for inputting the second clock signal, and the counter is used for counting a designated edge of the second clock signal and outputting a count value after receiving the enable signal output by the detection module.

6. The communication device according to claim 5, wherein the control module further comprises a register for storing the value of y and/or x and a comparator connected to the output terminals of the register and the counter for comparing the count value output by the counter with the value of y and/or x, and outputting a corresponding data transmission control signal or data reception control signal when the count value reaches the value of y or x.

7. The communication device of claim 1, wherein a ratio of the second frequency to the first frequency is greater than or equal to 2.

8. A data transmission method, comprising:

detecting a designated edge of a second clock signal after detecting a receiving edge of a pulse of a first clock signal, the second clock having a second frequency, the first clock having a first frequency, the second frequency being greater than the first frequency;

transmitting data at a y-th designated edge of the second clock signal, wherein y is an integer greater than or equal to 0 and is less than 1/2 of a ratio of the second frequency to the first frequency; or,

at an x-th designated edge of the second clock signal, data is received, wherein x is an integer greater than or equal to 0, and the x is less than 1/2 of a ratio of the second frequency to the first frequency.

9. The data transmission method of claim 8, wherein the second frequency is greater than or equal to 2 times the first frequency.

10. The data transmission method according to claim 8, wherein the method of detecting the reception edge of the first clock signal comprises: latching and outputting the current level of the first clock signal at the trigger edge moment of the second clock signal; delaying the current level of the first clock signal and outputting the delayed current level at the trigger edge moment of the second clock signal, wherein the delay time is the period of the second clock signal; and inverting one level of the first clock signal in the current period and the delayed level of the first clock signal in the delayed previous period, and then performing AND operation with the other level, wherein the operation result of the AND operation is taken as a detection result.

11. A communication system, comprising:

the communication device of any of claims 1 to 7.

12. The communication system according to claim 11, wherein when the communication device is configured to transmit data, the communication system further comprises: and the data receiving device is in signal connection with the communication device and is used for receiving the data signal sent by the communication device at the moment of the receiving edge of the first clock signal.

13. The communication system of claim 11, wherein when the communication device is configured to receive data, the communication system further comprises: and the data transmitting device is connected to the communication device in a signal way and is used for transmitting a data signal to the communication device at the moment of the transmitting edge of the first clock signal.