CN116683899A - High-reliability high-speed level shift circuit based on gallium nitride technology - Google Patents

Abstract

The invention provides a high-reliability high-speed level shift circuit based on a gallium nitride process, which comprises a level shift module, a latch module, a voltage bias module, a current mirror module, an acceleration pull-up module, a dVSW/dt resisting module and an output stage module, and can solve the problems of high delay and high power consumption of the traditional gallium nitride level shift circuit.

Description

A high-reliability and high-speed level shift circuit based on gallium nitride process

technical field

The invention relates to a power integrated circuit, in particular to a high-reliability and high-speed level shift circuit based on gallium nitride technology.

Background technique

GaN material is a recognized third-generation power semiconductor material, which has excellent physical and chemical properties such as greater electron mobility, greater critical electric field strength, and smaller thermal conductivity, so GaN power devices have high-speed , high reliability, and low loss characteristics, the application in the power conversion system can significantly improve the switching speed, conversion efficiency and power density of the system. The currently widely used GaN power device drive scheme is discrete drive, that is, silicon-based driver chips are used to drive discrete GaN devices. Due to the short board of the silicon-based chip's operating frequency, the high The frequency advantage cannot be fully utilized. On the contrary, with the increase of switching speed, the problem of parasitic inductance exposed by the discrete driving scheme becomes more and more prominent, which greatly reduces the reliability of the system. In order to solve this problem, it is often necessary to introduce technologies such as multilayer wiring and leadless packaging, but this inevitably increases the cost of PCB and chip packaging. Using gallium nitride technology to integrate the drive circuit and power devices on the same die can fundamentally solve the above problems, taking into account the high-frequency application and reliability of the system.

Since the P-type doping concentration of GaN materials is not high, P-type heavy doping cannot be achieved, resulting in low carrier mobility. Therefore, N-type GaN cannot be used in the existing commercial GaN process. Field effect transistors and P-type gallium nitride field effect transistors are matched, which prevents the structure in traditional CMOS circuits from being directly applied to gallium nitride circuits. Not only that, the current N-type GaN field effect transistor based on the GaN process has a low breakdown voltage (about 6V) and a high threshold voltage (about 2V), which greatly limits the flexibility of circuit design. Nowadays, with the continuous improvement of integration, the half-bridge driver chip based on gallium nitride technology is the future development direction. Circuit control is the key technology to realize dual-channel drive. However, the shortcomings of the above-mentioned gallium nitride material are more prominent in the design of the level shift circuit, so the design of the level shift circuit based on the gallium nitride process is extremely difficult.

In the practical application of a high-voltage driver chip, the switching of the power tube will introduce dVSW/dt noise into the driver chip, which will cause logic errors in the driver chip, and this problem will become more significant as the switching frequency increases.

Contents of the invention

The purpose of the present invention is to provide a level shift circuit based on gallium nitride process integrated circuit, which can overcome the problems of large time delay and high power consumption of the traditional gallium nitride level shift circuit. In order to realize the object of the invention, the technical scheme adopted in the present invention is as follows: a high-speed level shift circuit with low power consumption, including a level conversion module, a latch module, a voltage bias module, a current mirror module, an accelerated pull-up module, Anti-dVSW/dt module, output stage module.

The voltage bias module is composed of a voltage bias circuit 001, and the voltage bias circuit 001 includes a current source I0 and an enhanced NMOS transistor MN2. The connection relationship of the voltage bias circuit 001 is: one end of the current source is connected to the drain of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN3, and the gate of the enhanced NMOS transistor MN4 , the other end of the current source is connected to the power signal VDD of the low-voltage domain power rail, and the source of the enhanced NMOS transistor MN2 is connected to the ground signal VSS of the low-voltage domain power rail.

The current mirror module is composed of a current mirror circuit 002, and the current mirror circuit 002 includes enhanced NMOS transistors MN3-MN4 and capacitors C1-C2. The connection relationship of the current mirror circuit 002 is: the gate of the enhanced NMOS transistor MN3 is connected to the drain of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN4, and one end of the current source I0 The drain of the enhanced NMOS transistor MN3 is connected to one end of the capacitor C1, the source of the enhanced NMOS transistor MN5, the source of the enhanced NMOS transistor MN3 is connected to the ground signal VSS of the low-voltage domain power rail, and the other end of the capacitor C1 is connected to the low-voltage domain The ground signal VSS of the power rail, the drain of the enhanced NMOS transistor MN4 is connected to one end of the capacitor C2, the source of the enhanced NMOS transistor MN6, the source of the enhanced NMOS transistor MN4 is connected to the ground signal VSS of the low-voltage domain power rail, and the capacitor C2 The other end of the pin is connected to the ground signal VSS of the low-voltage domain power rail.

The low-voltage-high-voltage level shift module is composed of level conversion branches 003 and 004, and the level conversion branch 003 includes enhanced NMOS transistor MN5, high-voltage enhanced NMOS transistor HMN1, resistor R1, resistor R3, diode D3, and diode D5 , the level conversion branch 004 includes an enhanced NMOS transistor MN6, a high voltage enhanced NMOS transistor HMN2, a resistor R2, a resistor R4, a diode D4, and a diode D6. The connection relationship of the level conversion branch 003 is: the gate of the enhanced NMOS transistor MN5 is connected to the input signal VIN, the source of the enhanced NMOS transistor MN5 is connected to the drain of the enhanced NMOS transistor MN3, and one end of the capacitor C1. The drain of the tube MN5 is connected to the source of the high-voltage enhanced NMOS tube HMN1, the gate of the high-voltage enhanced NMOS tube HMN1 is connected to the power signal VDD of the low-voltage domain power rail, and the drain of the high-voltage enhanced NMOS tube HMN1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the gate of the enhanced NMOS transistor MN7, the gate of the enhanced NMOS transistor MN9, the gate of the enhanced NMOS transistor MN23, one end of the resistor R3, one end of the diode D3, one end of the diode D5, and the resistor R3 The other end of the diode D5 is connected to the power signal VBST of the high-voltage domain power rail, the other end of the diode D5 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of the diode D3 is connected to the ground signal VSW of the high-voltage domain power rail. The connection relationship of the level conversion branch 004 is: the output terminal of the inverter INV0 is connected to the gate of the enhanced NMOS transistor MN6, the source of the enhanced NMOS transistor MN6 is connected to the drain of the enhanced NMOS transistor MN4, and one end of the capacitor C2 , the drain of the enhanced NMOS transistor MN6 is connected to the source of the high-voltage enhanced NMOS transistor HMN2, the gate of the high-voltage enhanced NMOS transistor HMN2 is connected to the power signal VDD of the low-voltage domain power rail, and the drain of the high-voltage enhanced NMOS transistor HMN2 is connected to a resistor One end of R2 and the other end of resistor R2 are connected to the gate of enhanced NMOS transistor MN8, the gate of enhanced NMOS transistor MN10, the gate of enhanced NMOS transistor MN24, one end of resistor R4, one end of diode D4, and the gate of diode D6 One end, the other end of the resistor R4 is connected to the power signal VBST of the high-voltage domain power rail, the other end of the diode D6 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of the diode D4 is connected to the ground signal VSW of the high-voltage domain power rail.

The accelerated pull-up module is composed of accelerated pull-up circuits 005 and 006. The accelerated pull-up circuit 005 includes enhanced NMOS transistor MN7, enhanced NMOS transistor MN9, enhanced NMOS transistor MN11, enhanced NMOS transistor MN13, enhanced NMOS transistor MN15, Enhanced NMOS transistor MN17, resistor R5, capacitor C3, diode D1, accelerated pull-up circuit 006 includes enhanced NMOS transistor MN8, enhanced NMOS transistor MN10, enhanced NMOS transistor MN12, enhanced NMOS transistor MN14, enhanced NMOS transistor MN16 , Enhanced NMOS tube MN18, resistor R6, capacitor C4, diode D2. The connection relationship of the acceleration pull-up circuit 005 is as follows: the gate of the enhanced NMOS transistor MN7 is connected to the gate of the enhanced NMOS transistor MN23, one end of the resistor R3, one end of the diode D3, one end of the diode D5, and one end of the resistor R1. The source of the NMOS transistor MN7 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN7 is connected to the drain of the enhanced NMOS transistor MN11, the gate of the enhanced NMOS transistor MN15, and the gate of the enhanced NMOS transistor MN17. stage, one end of resistor R5, the other end of resistor R5 is connected to one end of diode D1, one end of capacitor C3, the other end of diode D1 is connected to the power signal VBST of the high-voltage domain power rail, and the source of the enhanced NMOS transistor MN11 is connected to the high-voltage domain power supply Rail ground signal VSW, the gate of the enhanced NMOS transistor MN11 is connected to the gate of the enhanced NMOS transistor MN13, the gate of the enhanced NMOS transistor MN12, the gate of the enhanced NMOS transistor MN14, one end of the resistor R9, and the gate of the resistor R10 At one end, the source of the enhanced NMOS transistor MN9 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN9 is connected to the source of the enhanced NMOS transistor MN15, the drain of the enhanced NMOS transistor MN13, and the capacitor C3. The other end is the gate of the enhanced NMOS transistor MN19, the drain of the enhanced NMOS transistor MN15 is connected to the power signal VBST of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN17 is connected to the power signal VBST of the high-voltage domain power rail. The source of the NMOS transistor MN17 is connected to the gate of the enhanced NMOS transistor MN21, the drain of the enhanced NMOS transistor MN22, one end of the resistor R8, the drain of the enhanced NMOS transistor MN20, and the input of the inverter INV1. The connection relationship of the acceleration pull-up circuit 006 is as follows: the gate of the enhanced NMOS transistor MN8 is connected to the gate of the enhanced NMOS transistor MN24, one end of the resistor R4, one end of the diode D4, one end of the diode D6, and one end of the resistor R2. The source of the NMOS transistor MN8 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN8 is connected to the drain of the enhanced NMOS transistor MN12, the gate of the enhanced NMOS transistor MN16, and the gate of the enhanced NMOS transistor MN18. stage, one end of resistor R6, the other end of resistor R6 is connected to one end of diode D2, one end of capacitor C4, the other end of diode D2 is connected to the power signal VBST of the high-voltage domain power rail, and the source of the enhanced NMOS transistor MN12 is connected to the high-voltage domain power supply Rail ground signal VSW, the gate of the enhanced NMOS transistor MN12 is connected to the gate of the enhanced NMOS transistor MN14, the gate of the enhanced NMOS transistor MN11, the gate of the enhanced NMOS transistor MN13, one end of the resistor R9, and the gate of the resistor R10 At one end, the source of the enhanced NMOS transistor MN10 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN10 is connected to the source of the enhanced NMOS transistor MN16, the drain of the enhanced NMOS transistor MN14, and the capacitor C4. The other end is the gate of the enhanced NMOS transistor MN20, the drain of the enhanced NMOS transistor MN16 is connected to the power signal VBST of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN18 is connected to the power signal VBST of the high-voltage domain power rail. The source of the NMOS transistor MN18 is connected to the gate of the enhanced NMOS transistor MN22, the drain of the enhanced NMOS transistor MN21, one end of the resistor R7, and the drain of the enhanced NMOS transistor MN19.

The latch module is composed of auxiliary latch circuit 007, including enhanced NMOS transistor MN19, enhanced NMOS transistor MN20, enhanced NMOS transistor MN21, enhanced NMOS transistor MN22, resistor R7, and resistor R8. The connection relationship is as follows: the gate of the enhanced NMOS transistor MN19 is connected to the drain of the enhanced NMOS transistor MN9, the source of the enhanced NMOS transistor MN15, the drain of the enhanced NMOS transistor MN13, and the other end of the capacitor C3. The gate of the transistor MN20 is connected to the drain of the enhanced NMOS transistor MN10, the source of the enhanced NMOS transistor MN16, the drain of the enhanced NMOS transistor MN14, and the other end of the capacitor C4, and the source of the enhanced NMOS transistor MN19 is connected to the high-voltage domain The ground signal VSW of the power rail, the source of the enhanced NMOS transistor MN20 is connected to the ground signal VSW of the high-voltage domain power rail, the drain of the enhanced NMOS transistor MN19 is connected to the drain of the enhanced NMOS transistor MN21, and the gate of the enhanced NMOS transistor MN22 electrode, one end of resistor R7, the source of enhanced NMOS transistor MN18, the drain of enhanced NMOS transistor MN20 is connected to the drain of enhanced NMOS transistor MN22, the gate of enhanced NMOS transistor MN21, one end of resistor R8, enhanced The source of the NMOS transistor MN17, the input terminal of the inverter INV1, the source of the enhanced NMOS transistor MN21 is connected to the ground signal VSW of the high-voltage domain power rail, and the source of the enhanced NMOS transistor MN22 is connected to the ground signal VSW of the high-voltage domain power rail , the other end of the resistor R7 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of the resistor R8 is connected to the power signal VBST of the high-voltage domain power rail.

The anti-dVSW/dt module is composed of an anti-dVSW/dt circuit 008, including enhanced NMOS transistor MN23, enhanced NMOS transistor MN24, resistor R9, and resistor R10. The connection relationship is as follows: the gate of the enhanced NMOS transistor MN23 is connected to the gate of the enhanced NMOS transistor MN7, the gate of the enhanced NMOS transistor MN9, one end of the resistor R1, one end of the resistor R3, one end of the diode D3, and one end of the diode D5. One end, the gate of the enhanced NMOS transistor MN24 is connected to the gate of the enhanced NMOS transistor MN8, the gate of the enhanced NMOS transistor MN10, one end of the resistor R2, one end of the resistor R4, one end of the diode D4, and one end of the diode D6. The source of the NMOS transistor MN23 is connected to the ground signal VSW of the high-voltage domain power rail, the source of the enhanced NMOS transistor MN24 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN23 is connected to the enhanced NMOS transistor MN24. The drain, one end of the resistor R10, and the other end of the resistor R10 are connected to the resistor R9, the gate of the enhanced NMOS transistor MN11, the gate of the enhanced NMOS transistor MN13, the gate of the enhanced NMOS transistor MN12, and the gate of the enhanced NMOS transistor MN14 The other end of the resistor R9 is connected to the power signal VBST of the high-voltage domain power rail.

The output module is composed of an output circuit 009, including an inverter INV1 and an inverter INV2. The connection relationship is: the input terminal of the inverter INV1 is connected to the source of the enhanced NMOS transistor MN17, the gate of the enhanced NMOS transistor MN21, the drain of the enhanced NMOS transistor MN22, one end of the resistor R8, and the enhanced NMOS transistor MN20 The drain of the inverter INV1 is connected to the input of the inverter INV2, and the output of the inverter INV2 is connected to the output signal VOUT.

Preferably: the enhanced NMOS transistors MN2-MN24 are all enhanced GaN field effect transistors, and the high-voltage enhanced NMOS transistors HMN1-HMN2 are all high-voltage enhanced GaN field-effect transistors.

Preferably: the resistors R1-R10 are resistors based on gallium nitride technology, depletion-type or enhancement-mode gallium nitride field-effect transistors in diode connection mode, depletion-type or enhancement-mode gallium nitride field-effect transistors with gate fixed voltage bias Gallium field effect transistors, or other material resistors in the gallium nitride process, including metal film resistors and polysilicon resistors;

The diodes D1-D6 are diode-connected depletion-mode or enhancement-mode gallium nitride field-effect transistors, on-chip integrated diode devices or externally connected diode devices;

The inverters INV0-INV2 are resistance inverters or totem-pole dual-N output inverters based on gallium nitride technology;

The current source I0 is a current source composed of a depletion-mode GaN field-effect transistor, a depletion-mode or an enhancement-mode GaN field-effect transistor with a fixed gate voltage bias.

Compared with the prior art, the present invention has the following advantages and remarkable effects:

(1) The delay of signal transmission can be effectively reduced. When the input signal VIN is low level, the upper end of capacitor C1 is about zero potential. When VIN becomes high level, since the voltage across capacitor C1 cannot change abruptly, the potential at the upper end of C1 will remain at zero potential for a short time. Compared with no capacitor In the case of C1, MN5 will obtain a larger gate-source voltage, which increases the current capability of MN5, enables the potential of point X to be pulled down quickly, and reduces the delay of signal transmission. When the potential at point X is turned from high to low, the potential of point S is turned from low to high, and the NMOS transistor MN17 in the acceleration pull-up circuit 005 is turned on, providing an additional pull-up current path for point B, making the potential of point B Fast inversion reduces the delay of signal transmission. The same is true when the input signal VIN changes from high level to low level.

(2) The power consumption when the circuit works can be effectively reduced. The voltage bias circuit 001 and the current mirror circuit 002 act as tail current sources to provide a relatively constant current for the level conversion branches 003 and 004, which greatly limits power consumption. When the potential at point X is flipped from low to high, the potential at point S is flipped from high to low, MN17 is turned off, and the extra pull-up current path of B is turned off, which saves power consumption while ensuring a faster flipping speed. The traditional level shift circuit based on gallium nitride technology includes structures such as pulse generation circuit and digital filter circuit, and uses a large number of logic gates. The present invention cancels the above two structures while realizing the same function, reducing a large amount of power consumption.

(3) It can effectively improve the anti-dVSW/dt ability. At the moment when dVSW/dt comes, point X and point Y are at low level at the same time, anti-dVSW/dt circuit 008 pulls point C to high level, and the two input terminals S and R of the latch circuit are set to low level , maintained in a latched state, making the output signal immune to dVSW/dt noise.

Description of drawings

Fig. 1 is a typical application diagram of the present invention in a half-bridge drive circuit based on gallium nitride technology;

Fig. 2 is a structural diagram of a traditional level shift circuit and a structural diagram of its internal pulse generation circuit;

FIG. 3 is a working waveform diagram of a conventional level shift circuit;

Figure 4 is a working waveform diagram of a traditional level shift circuit under the influence of dVSW/dt noise;

Fig. 5 is the structural diagram of the highly reliable high-speed level shift circuit that the present invention proposes;

Fig. 6 is the working waveform diagram of the highly reliable high-speed level shift circuit proposed by the present invention;

FIG. 7 is a working waveform diagram of the highly reliable high-speed level shift circuit proposed by the present invention under the influence of dVSW/dt noise.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

FIG. 1 is a typical application diagram of the present invention in a half-bridge driving circuit based on gallium nitride technology. A high-reliability and high-speed level shift circuit is used to replace the existing level shift circuit, and the rest is the same as the prior art. The half-bridge structure is a common structure in the power supply system. It is usually composed of two GaN power transistors in series, which are respectively a high-side GaN power transistor and a low-side GaN power transistor, and a high-side GaN power transistor. The bus voltage of the transistor T1 is VBUS, and the source of the high-side GaN power transistor T1 and the drain of the low-side GaN power transistor are VS, which are connected to the load of the subsequent circuit. The core of the half bridge drive circuit is the level shift circuit. Since VS is a floating potential, in order to realize the normal driving of the high-side GaN power transistor T1, it is necessary to rely on a level shift circuit, whose function is to convert the signal of the low-voltage domain power rail VCC-GND to the high-voltage domain power rail VBST In -VSW, it is used to drive the high-side GaN power transistor. The input HIN signal and LIN signal first pass through the high-side input logic circuit and the low-side input logic circuit respectively, and then the high-side signal is converted into a high-voltage domain signal through a level shift circuit, and then drives the high-side GaN power through the high-side output drive circuit. The low-side signal passes through the delay matching circuit and then drives the low-side GaN power transistor T2 through the low-side output driving circuit. In the half-bridge driving circuit, the high-voltage basin area usually adopts the form of bootstrap power supply, and the diode D1 and the capacitor C1 form a floating power supply VB to supply power for the high-voltage basin area circuit.

FIG. 2( a ) is a structural diagram of a conventional level shift circuit, including a pulse generation circuit 001 , a level conversion branch 002 , a digital filter circuit 003 , a latch circuit 004 , and a buffer stage circuit 005 . After the input signal VIN passes through the pulse generating circuit 001, two pulse signals are generated at the SET point and the RESET point. FIG. 2(b) is a structure diagram of the pulse generating circuit 001. The above two pulses enter the level conversion branch 002 and then are converted to the high-voltage domain power supply rail VBST-VSW, which are respectively output from points X and Y. The function of diodes D1 and D2 is to clamp the potentials of point X and point Y so that they will not be too much lower than VSW. The signal is transmitted to the latch circuit 004 after the dVSW/dt noise is filtered out in the digital filter circuit 003 . Latch circuit 004 is usually composed of RS flip-flops, and two NAND gates form positive feedback, which enhances the anti-interference ability of the circuit. The signal is finally shaped by the buffer stage circuit 005 to obtain the output signal VOUT. The circuit introduces the digital filter circuit 003, which has strong anti-dVSW/dt ability, but uses a large number of logic gates, which increases the power consumption and delay of the circuit. The circuit introduces the pulse generation circuit 001, which reduces the conduction time of the level conversion branch 002 and reduces the power consumption to a certain extent, but the pulse generation circuit 001 itself is also composed of a large number of logic gates, which increases the power consumption consumption.

Figure 3 is a working waveform diagram of a traditional level shift circuit. After the input signal VIN passes through the pulse generating circuit 001, a positive pulse is generated at the SET point and the RESET point, respectively, at the rising and falling edges of the input signal VIN, the above two pulses After entering the level conversion branch 002, the potentials at point X and point Y are respectively pulled to low level. When there is no dVSW/dt noise, the signals at point X and point Y can normally pass through the digital filter circuit 003 . Figure 4 is a working waveform diagram of a traditional level shift circuit under the influence of dVSW/dt noise. When there is dVSW/dt noise, the potentials of points X and Y are pulled to low level at the same time, and the same is true for points X1 and Y1. The potential of point Z is pulled to low level, the points R' and S' are pulled to high level at the same time, and the state of RS latch is maintained, so that the signal transmission is free from dVSW/dt noise interference. If there is no digital filter circuit 003, the latch circuit 004 will enter an indefinite state, and the output signal VOUT cannot be determined. Fig. 5 is a specific circuit diagram of the fully integrated GaN low-power high-speed level shift circuit proposed by the present invention, which is used to convert the signal in the low-voltage domain to the high-voltage domain, including a voltage bias circuit 001 and a current mirror circuit 002. Level switching branches 003 and 004, accelerated pull-up circuits 005 and 006, latch circuit 007, anti-dVSW/dt circuit 008, and output circuit 009. Wherein, the power rail of the low-voltage domain is the ground signal VSS-the power signal VDD, and the power rail of the high-voltage domain is the ground signal VSW-the power signal VBST.

The level shift circuit proposed by the present invention retains the level conversion branch in the traditional level shift circuit, and adds a voltage bias circuit 001, a current mirror circuit 002, an acceleration pull-up circuit 005 and 006, and an anti-dVSW/dt circuit 008 .

The voltage bias circuit 001 and the current mirror circuit 002 jointly constitute a tail current source, including a current source I0, enhanced NMOS transistors MN2-MN4, and capacitors C1-C2. After the current generated by the current source I0 flows through the enhanced NMOS transistor MN2 configured by the diode, a relatively constant voltage bias is generated on its gate, and then passes through the current mirror composed of the enhanced NMOS transistors MN3~MN4 to provide a voltage for the current Level switching branches 003 and 004 provide relatively constant current. Capacitors C1 and C2 are connected across the source and drain of MN3 and MN4 respectively. When the input signal VIN is low level, the upper end of capacitor C1 is about zero potential. When VIN becomes high level, since the voltage across capacitor C1 cannot change abruptly, the potential at the upper end of C1 will remain at zero potential for a short time. Compared with no capacitor In the case of C1, MN5 will obtain a larger gate-source voltage, which will increase the current capability of MN5, enable the potential of the point to be pulled down quickly, and reduce the delay of signal transmission. When the potential at point X is completely pulled down to a low level, C1 is fully charged, and the gate-source voltage and current capability of MN5 return to normal levels. The same is true when the input signal VIN changes from high level to low level. The addition of the capacitors C1 and C2 enables the circuit of the present invention to reduce the power consumption as much as possible while reducing the signal transmission delay.

Level conversion branches 003 and 004 are completely symmetrical, including enhanced NMOS transistors MN5 and MN6, high-voltage enhanced NMOS transistors HMN1 and HMN2, diodes D3-D6, and resistors R3 and R4. The working principle of the level conversion branch 003 and 004 is the same. The working principle of the level conversion branch 003 is as follows: After the input signal VIN is input to the gate of MN5, MN5 is turned on, and the potential at point X changes from high level to is low level. Design the resistance value of resistor R3 so that the voltage drop on resistor R3 is about VBST-VSW when the branch is turned on, then the high level at point X is VBST, and the low level is VSW, realizing the low-voltage domain power supply The purpose of converting the signal from the rail to the high voltage domain power rail. The purpose of the high-voltage device HMN1 is to protect other devices on the branch from being broken down by high voltage. At the moment of power tube switching or during dVSW/dt, the function of diode D3 is to clamp the potential at point X so that it will not be too much lower than VSW; the function of diode D5 is to clamp the potential at point X so that It will not be much higher than VBST. Resistor R1 is used as a damping resistor to suppress the oscillation generated by switching transient dVSW/dt noise.

Acceleration pull-up circuits 005 and 006 are completely symmetrical, including enhanced NMOS transistors MN7-MN18, diodes D1-D2, resistors R5-R6, and capacitors C3-C4. The working principles of acceleration pull-up circuits 005 and 006 are the same, and the working principle of acceleration pull-up circuit 005 is as follows: when point X is at high level, MN7 and MN9 are turned on, the potential at the lower end of capacitor C3 is zero, diode D1 is turned on, and VBST Capacitor C3 is charged through diode D1, the potential of the upper end of capacitor C3 is VDD-VD (VD is the forward conduction voltage of diode D1), and the voltage difference between both ends is VDD-VD; when point X becomes low level, MN7 and MN9 are turned off off, the potential of the upper end of capacitor C3 and the lower end of resistor R5 is approximately equal to VDD, which makes MN15 conduction, and the potential of the lower end of capacitor C3 becomes VDD. Since the voltage at both ends of the capacitor cannot change suddenly, the potential of the upper end of capacitor C3 is raised to 2VDD- VD (approximately equal to 2VDD), diode D1 is cut off. The circuit adopts the scheme of dual N-type transistor output, and introduces the bootstrap capacitor C3. On the one hand, this scheme ensures that the gate-source voltage of the upper transistor MN15 is zero when the output is low, eliminating the problem caused by the simultaneous conduction of the upper and lower transistors. The problem that the output low level is higher than the ground potential; on the other hand, by using the characteristic that the voltage at both ends of the capacitor cannot change suddenly, it is ensured that the gate-source voltage of the upper transistor MN15 is greater than the threshold voltage when the output is high, avoiding the problem caused by the incomplete conduction of the upper transistor. The problem of level loss caused by communication improves the reliability of the circuit.

The latch circuit 007 includes enhanced NMOS transistors MN19-MN22 and resistors R7-R8. Its working principle is as follows: when point X changes from high level to low level, MN19 is turned on, point S changes from low level to high level, and point A becomes low level, causing MN22 to be cut off, and VBST pulls the potential of point B To a high level, MN21 is turned on, and the potential of point A is further pulled to a low level, and the state is locked; during this process, MN17 is in a conductive state, and VBST charges point B through two branches of MN17 and R8 , greatly improving the potential flipping speed at point B. When point X changes from low level to high level, point S changes from high level to low level, MN17 is turned off, and the extra pull-up current path of B is turned off, which saves power consumption while ensuring faster flipping speed .

The anti-dVSW/dt circuit 008 includes enhanced NMOS transistors MN23-MN24 and resistors R9-R10. Its working principle is as follows: If the anti-dVSW/dt circuit 007 is not introduced, when the high-side channel changes from off state to on state, VSW will rise rapidly and generate a positive dVSW/dt noise. Inside, the potentials of points X and Y will drop to low level at the same time, and the potentials of points S and R will be pulled to high level at the same time. When the dVSW/dt noise ends, the latch circuit 007 will enter an indeterminate state, resulting in unsettled Expected logic error; after the anti-dVSW/dt circuit 007 is introduced, after the potentials of points X and Y drop to low level, MN23 and MN24 are cut off, the potential of point C becomes high level, MN11~MN14 are turned on, and the latch circuit The potentials of the two input terminals of 007 are pulled to low level, so that the current output state can be saved, and it is free from dVSW/dt noise interference.

The output circuit 009 includes inverters INV1 to INV2. Its purpose is to shape and filter the output signal and enhance its drive capability.

FIG. 6 is a working waveform diagram of the highly reliable high-speed level shift circuit proposed by the present invention. When the input signal VIN changes from a low level to a high level, the NMOS transistor MN5 is quickly turned on, and point X is quickly pulled to a low level. The inverse signal VIN' of the input signal VIN changes from high level to low level, which makes MN6 turn off quickly. Since the current capacity of the resistor is much lower than that of the MOS tube, the pull-up speed at point Y will be lower than the pull-down speed at point X. Under the action of the bootstrap capacitor C3, the gate voltage range of MN15 and MN17 increases from 0~VDD to 0~2VDD. When the signal at point X enters the acceleration pull-up circuit 005, MN17 is turned on, and the potential at point S is pulled to high Level, so that the NMOS transistor MN19 is turned on, and the potential of point A is quickly pulled to a low level. At the same time, the potential at point Y is gradually pulled to a high level. Under the action of the accelerated pull-up circuit 006, the potential at point R becomes low level. The ground is pulled to a high level, which reduces the delay of signal transmission. The same is true when the input signal VIN changes from high level to low level.

FIG. 7 is a working waveform diagram of the highly reliable high-speed level shift circuit proposed by the present invention under the influence of dVSW/dt noise. When there is dVSW/dt noise, the potentials of point X and point Y are pulled to low level at the same time, so that MN23 and MN24 tubes are turned off, point C is pulled to high level, MOS tubes MN11~14 are turned on, point S and R The point is pulled to low level at the same time, and the state of the latch circuit 008 is maintained, so that the signal transmission is free from dVSW/dt noise interference. Under the clamping action of diodes D3-D6, the potentials of points X and Y are limited between -VD-VDD+VD (VD is the voltage drop when the diode is turned on), protecting the device from being damaged by dVSW/dt noise.

Claims (10)

1. A high-reliability high-speed level shift circuit based on gallium nitride technology, including a voltage bias module, a current mirror module, a level conversion module, an accelerated pull-up module, a latch module, an anti-dVSW/dt module, and an output stage module; it is characterized in that: the voltage bias module includes a voltage bias circuit 001, the current mirror module includes a current mirror circuit 002, the level conversion module includes level conversion branches 003 and 004, and the acceleration pull-up module includes an acceleration pull-up circuit 005 and 006, the latch module includes a latch circuit 007, the anti-dVSW/dt module includes an anti-dVSW/dt circuit 008, and the output stage module includes an output stage circuit 009; the input signal VIN and its signal VIN' through the inverter INV0 are respectively connected to The input ends of the level conversion branches 003 and 004; the output ends of the level conversion branches 003 and 004 are points X and Y respectively, which are respectively connected to the input ends of the acceleration pull-up circuits 005 and 006; the acceleration pull-up circuits 005 and The output terminals of 006 are respectively connected to the two input terminals S and R of the latch circuit 007; the two output terminals A and B of the latch circuit 007 are respectively connected to the auxiliary pull-up tubes of the acceleration pull-up circuits 006 and 005 The purpose is to provide an additional charging path for point A and point B, and speed up the signal inversion speed of point A and point B; the output point B of the latch circuit 007 is connected to the input end of the output stage circuit 009, through two After two inverters INV1 and INV2, the output signal VOUT is obtained; the voltage bias circuit 001 provides a bias voltage, which is copied by MN3 and MN4 in the current mirror circuit 002, and supplies power to the level conversion branches 003 and 004 respectively; The output terminals X and Y of the level conversion branches 003 and 004 are connected to the input terminal of the anti-dVSW/dt circuit 008, and the output terminal C of the anti-dVSW/dt circuit 008 is connected to the control tubes in the acceleration pull-up circuits 005 and 006 The gate is used to pull down the output signals S and R of the acceleration pull-up circuits 005 and 006 to low level when the dVSW/dt noise comes. 2. The highly reliable high-speed level shift circuit based on GaN technology according to claim 1, characterized in that: the voltage bias circuit 001 includes a current source I0, an enhanced NMOS transistor MN2; the voltage bias circuit 001 The connection relationship is as follows: one end of the current source is connected to the drain of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN3, the gate of the enhanced NMOS transistor MN4, and the other end of the current source One end is connected to the power signal VDD of the low-voltage domain power rail, and the source of the enhanced NMOS transistor MN2 is connected to the ground signal VSS of the low-voltage domain power rail. 3. The highly reliable high-speed level shift circuit based on gallium nitride technology according to claim 2, characterized in that: the current mirror circuit 002 includes enhanced NMOS transistors MN3-MN4, capacitors C1-C2; the current mirror circuit The connection relationship of 002 is: the gate of the enhanced NMOS transistor MN3 is connected to the drain of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN2, the gate of the enhanced NMOS transistor MN4, and one end of the current source I0. The drain of the NMOS transistor MN3 is connected to one end of the capacitor C1, the source of the enhanced NMOS transistor MN5, the source of the enhanced NMOS transistor MN3 is connected to the ground signal VSS of the low-voltage domain power rail, and the other end of the capacitor C1 is connected to the ground signal of the low-voltage domain power rail. The ground signal VSS, the drain of the enhanced NMOS transistor MN4 is connected to one end of the capacitor C2, the source of the enhanced NMOS transistor MN6, the source of the enhanced NMOS transistor MN4 is connected to the ground signal VSS of the low-voltage domain power rail, and the other end of the capacitor C2 Connect to the ground signal VSS of the low-voltage domain power rail. 4. The high-reliability high-speed level shift circuit based on GaN technology according to claim 3, characterized in that: the level shift branch 003 includes an enhanced NMOS transistor MN5, a high-voltage enhanced NMOS transistor HMN1, a resistor R1, resistor R3, diode D3, diode D5, level conversion branch 004 includes enhanced NMOS tube MN6, high voltage enhanced NMOS tube HMN2, resistor R2, resistor R4, diode D4, diode D6; level conversion branch 003 The connection relationship is: the gate of the enhanced NMOS transistor MN5 is connected to the input signal VIN, the source of the enhanced NMOS transistor MN5 is connected to the drain of the enhanced NMOS transistor MN3, and one end of the capacitor C1, and the drain of the enhanced NMOS transistor MN5 is connected to the high voltage The source of the enhanced NMOS transistor HMN1, the gate of the high-voltage enhanced NMOS transistor HMN1 are connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NMOS transistor HMN1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the enhanced The gate of NMOS transistor MN7, the gate of enhanced NMOS transistor MN9, the gate of enhanced NMOS transistor MN23, one end of resistor R3, one end of diode D3, one end of diode D5, and the other end of resistor R3 is connected to the high-voltage domain power supply Rail power signal VBST, the other end of diode D5 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of diode D3 is connected to the ground signal VSW of the high-voltage domain power rail; the connection relationship of the level conversion branch 004 is: inverter The output terminal of INV0 is connected to the gate of the enhanced NMOS transistor MN6, the source of the enhanced NMOS transistor MN6 is connected to the drain of the enhanced NMOS transistor MN4, and one end of the capacitor C2, and the drain of the enhanced NMOS transistor MN6 is connected to the high voltage enhanced NMOS The source of the tube HMN2, the gate of the high-voltage enhanced NMOS tube HMN2 are connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NMOS tube HMN2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the enhanced NMOS tube The gate of MN8, the gate of enhanced NMOS transistor MN10, the gate of enhanced NMOS transistor MN24, one end of resistor R4, one end of diode D4, one end of diode D6, and the other end of resistor R4 is connected to the power supply of the high-voltage domain power rail signal VBST, the other end of the diode D6 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of the diode D4 is connected to the ground signal VSW of the high-voltage domain power rail. 5. The highly reliable high-speed level shift circuit based on GaN technology according to claim 4, characterized in that: the acceleration pull-up circuit 005 includes enhanced NMOS transistor MN7, enhanced NMOS transistor MN9, enhanced NMOS Tube MN11, enhanced NMOS tube MN13, enhanced NMOS tube MN15, enhanced NMOS tube MN17, resistor R5, capacitor C3, diode D1, acceleration pull-up circuit 006 includes enhanced NMOS tube MN8, enhanced NMOS tube MN10, enhanced NMOS tube MN12, enhanced NMOS tube MN14, enhanced NMOS tube MN16, enhanced NMOS tube MN18, resistor R6, capacitor C4, diode D2; the connection relationship of the accelerated pull-up circuit 005 is: the gate connection of the enhanced NMOS tube MN7 The gate of the enhanced NMOS transistor MN23, the gate of the enhanced NMOS transistor MN9, one end of the resistor R3, one end of the diode D3, one end of the diode D5, one end of the resistor R1, and the source of the enhanced NMOS transistor MN7 are connected to the high-voltage domain power supply The ground signal VSW of the rail, the drain of the enhanced NMOS transistor MN7 is connected to the drain of the enhanced NMOS transistor MN11, the gate of the enhanced NMOS transistor MN15, the gate of the enhanced NMOS transistor MN17, one end of the resistor R5, and the The other end is connected to one end of the diode D1 and one end of the capacitor C3, the other end of the diode D1 is connected to the power signal VBST of the high-voltage domain power rail, the source of the enhanced NMOS transistor MN11 is connected to the ground signal VSW of the high-voltage domain power rail, and the enhanced NMOS transistor The gate of MN11 is connected to the gate of the enhanced NMOS transistor MN13, the gate of the enhanced NMOS transistor MN12, the gate of the enhanced NMOS transistor MN14, one end of the resistor R9, one end of the resistor R10, and the source of the enhanced NMOS transistor MN9 Connect the ground signal VSW of the high-voltage domain power rail, the drain of the enhanced NMOS transistor MN9 is connected to the source of the enhanced NMOS transistor MN15, the drain of the enhanced NMOS transistor MN13, the other end of the capacitor C3, and the gate of the enhanced NMOS transistor MN19 The drain of the enhanced NMOS transistor MN15 is connected to the power signal VBST of the high-voltage domain power rail, the drain of the enhanced NMOS transistor MN17 is connected to the power signal VBST of the high-voltage domain power rail, and the source of the enhanced NMOS transistor MN17 is connected to the enhanced NMOS The gate of the transistor MN21, the drain of the enhanced NMOS transistor MN22, one end of the resistor R8, the drain of the enhanced NMOS transistor MN20, and the input terminal of the inverter INV1; the connection relationship of the accelerated pull-up circuit 006 is: enhanced NMOS The gate of the transistor MN8 is connected to the gate of the enhanced NMOS transistor MN24, the gate of the enhanced NMOS transistor MN10, one end of the resistor R4, one end of the diode D4, one end of the diode D6, one end of the resistor R2, and the enhanced NMOS transistor MN8. The source is connected to the ground signal VSW of the high-voltage domain power rail, the drain of the enhanced NMOS transistor MN8 is connected to the drain of the enhanced NMOS transistor MN12, the gate of the enhanced NMOS transistor MN16, the gate of the enhanced NMOS transistor MN18, and the resistor R6 One end of the resistor R6 is connected to one end of the diode D2 and one end of the capacitor C4, the other end of the diode D2 is connected to the power signal VBST of the high-voltage domain power rail, and the source of the enhanced NMOS transistor MN12 is connected to the ground signal of the high-voltage domain power rail VSW, the gate of the enhanced NMOS transistor MN12 is connected to the gate of the enhanced NMOS transistor MN14, the gate of the enhanced NMOS transistor MN11, the gate of the enhanced NMOS transistor MN13, one end of the resistor R9, and one end of the resistor R10. The source of the NMOS transistor MN10 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN10 is connected to the source of the enhanced NMOS transistor MN16, the drain of the enhanced NMOS transistor MN14, the other end of the capacitor C4, and the enhanced The gate of the enhanced NMOS transistor MN20, the drain of the enhanced NMOS transistor MN16 is connected to the power signal VBST of the high-voltage domain power rail, the drain of the enhanced NMOS transistor MN18 is connected to the power signal VBST of the high-voltage domain power rail, and the enhanced NMOS transistor MN18 The source is connected to the gate of the enhanced NMOS transistor MN22, the drain of the enhanced NMOS transistor MN21, one end of the resistor R7, and the drain of the enhanced NMOS transistor MN19. 6. The high-reliability high-speed level shift circuit based on GaN technology according to claim 5, characterized in that: the auxiliary latch circuit 007 includes an enhanced NMOS transistor MN19, an enhanced NMOS transistor MN20, an enhanced NMOS Tube MN21, enhanced NMOS tube MN22, resistor R7, and resistor R8; their connection relationship is: the gate of the enhanced NMOS tube MN19 is connected to the drain of the enhanced NMOS tube MN9, the source of the enhanced NMOS tube MN15, and the enhanced NMOS tube MN19 The drain of the transistor MN13, the other end of the capacitor C3, the gate of the enhanced NMOS transistor MN20 are connected to the drain of the enhanced NMOS transistor MN10, the source of the enhanced NMOS transistor MN16, the drain of the enhanced NMOS transistor MN14, and the capacitor C4 On the other end, the source of the enhanced NMOS transistor MN19 is connected to the ground signal VSW of the high-voltage domain power rail, the source of the enhanced NMOS transistor MN20 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN19 is connected to the enhanced The drain of the enhanced NMOS transistor MN21, the gate of the enhanced NMOS transistor MN22, one end of the resistor R7, the source of the enhanced NMOS transistor MN18, the drain of the enhanced NMOS transistor MN20 is connected to the drain of the enhanced NMOS transistor MN22, the enhanced The gate of the NMOS transistor MN21, one end of the resistor R8, the source of the enhanced NMOS transistor MN17, the input end of the inverter INV1, the source of the enhanced NMOS transistor MN21 is connected to the ground signal VSW of the high-voltage domain power rail, and the enhanced The source of the NMOS transistor MN22 is connected to the ground signal VSW of the high-voltage domain power rail, the other end of the resistor R7 is connected to the power signal VBST of the high-voltage domain power rail, and the other end of the resistor R8 is connected to the power signal VBST of the high-voltage domain power rail. 7. The highly reliable high-speed level shift circuit based on GaN technology according to claim 6, characterized in that: the anti-dVSW/dt circuit 008 includes an enhanced NMOS transistor MN23, an enhanced NMOS transistor MN24, and a resistor R9 , resistor R10; the connection relationship is: the gate of the enhanced NMOS transistor MN23 is connected to the gate of the enhanced NMOS transistor MN7, the gate of the enhanced NMOS transistor MN9, one end of the resistor R1, one end of the resistor R3, and one end of the diode D3 , one end of the diode D5, and the gate of the enhanced NMOS transistor MN24 are connected to the gate of the enhanced NMOS transistor MN8, the gate of the enhanced NMOS transistor MN10, one end of the resistor R2, one end of the resistor R4, one end of the diode D4, and the diode D6 The source of the enhanced NMOS transistor MN23 is connected to the ground signal VSW of the high-voltage domain power rail, the source of the enhanced NMOS transistor MN24 is connected to the ground signal VSW of the high-voltage domain power rail, and the drain of the enhanced NMOS transistor MN23 is connected to the enhanced The drain of the NMOS transistor MN24, one end of the resistor R10, and the other end of the resistor R10 are connected to the resistor R9, the grid of the enhanced NMOS transistor MN11, the grid of the enhanced NMOS transistor MN13, the grid of the enhanced NMOS transistor MN12, and the enhanced NMOS transistor MN12. The gate of the NMOS transistor MN14 and the other end of the resistor R9 are connected to the power signal VBST of the high-voltage domain power rail. 8. The high-reliability high-speed level shift circuit based on gallium nitride technology according to claim 7, characterized in that: the output circuit 009 includes an inverter INV1 and an inverter INV2; the connection relationship is: inversion The input end of the device INV1 is connected to the source of the enhanced NMOS transistor MN17, the gate of the enhanced NMOS transistor MN21, the drain of the enhanced NMOS transistor MN22, one end of the resistor R8, the drain of the enhanced NMOS transistor MN20, and the inverter The output terminal of INV1 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the output signal VOUT. 9. The highly reliable high-speed level shift circuit based on gallium nitride technology according to claim 8, characterized in that: the enhancement-type NMOS transistors MN2-MN24 are all enhancement-type gallium nitride field-effect transistors, and the high-voltage The enhanced NMOS transistors HMN1-HMN2 are all high-voltage enhanced GaN field effect transistors. 10. The highly reliable high-speed level shift circuit based on GaN technology according to claim 7, characterized in that: the resistors R1-R10 are depletion-type or diode-connected resistors based on GaN technology. Enhancement mode eGaN FETs, depletion mode or enhancement mode eGaN FETs with fixed gate voltage bias, or other material resistors in the GaN process, including metal film resistors and polysilicon resistors; The diodes D1-D6 are diode-connected depletion-mode or enhancement-mode gallium nitride field-effect transistors, on-chip integrated diode devices or externally connected diode devices; The inverters INV0-INV2 are resistance inverters or totem-pole dual-N output inverters based on gallium nitride technology; The current source I0 is a current source composed of a depletion-mode GaN field-effect transistor, a depletion-mode or an enhancement-mode GaN field-effect transistor with a fixed gate voltage bias.