CN116666406A - Front-illuminated image sensor and method of forming the same - Google Patents

Abstract

The invention discloses a front-illuminated image sensor and a forming method thereof. The method comprises: forming a first N-type doped region in a substrate; wherein, the substrate includes a pixel array region; forming a second N-type doped region surrounding the pixel array region; wherein, the second N-type doped region is connected to the first N-type doped region and connected to a positive voltage of a certain potential; wherein, The first N-type doped region and the second N-type doped region constitute a discharge path for discharging excess charge generated in the pixel array region. In the present invention, an N-type buried layer is added between the heavily doped P-type substrate and the bottom of the photosensitive unit, connected to a high potential, and the overflow electrons are sucked away to realize the "high light overflow protection function"; at the same time, in the pixel array area and the periphery An N-type doped region is added between the logic circuit regions to connect the N-type buried layer, and a high potential is connected to realize the absorption of overflow electrons, to prevent the influence of substrate electrons and peripheral circuit electrons on the readout signal, and to achieve a high signal-to-noise ratio.

Description

Front-illuminated image sensor and method for forming the same

technical field

The invention belongs to the field of semiconductor manufacturing, in particular to a front-illuminated image sensor and a forming method thereof.

Background technique

Complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) is a semiconductor device that converts optical images into electrical signals. A CIS includes a light-receiving component (often called a photodiode) for sensing light and a logic circuit for processing the sensed light into an electrical signal.

The current mainstream CIS uses silicon-based technology, including photosensitive pixel arrays, blackout pixel arrays, and peripheral logic circuits (devices). With the improvement of the semiconductor integrated circuit manufacturing process, the pixel size can be continuously reduced. At the same time, emerging scene applications such as security monitoring, machine vision, and vehicle imaging have put forward higher requirements for the performance of CIS. When the CIS is in a bright scene, the photogenerated electrons of the pixel photosensitive unit will exceed the full well capacity (Full Well Capacity, FWC) of the pixel, and the excess electrons will overflow to the adjacent pixels, making the adjacent pixels oversensitive, resulting in "highlight overflow" ", the picture is floating, which seriously reduces the image quality. When the CIS is in a dark scene, the electrical signal generated under low illumination is weak, and the peripheral circuits inevitably bring some noise, both of which seriously affect signal acquisition and image quality.

For low-illumination noise, the current optimization method commonly used in the industry is to increase sensor sensitivity and pixel full well capacity to reduce read noise and present clearer and more delicate image quality. One solution is to use a high-resolution back-illuminated image sensor with a Backside Deep Trench Isolation (BDTI) structure, one is to reduce metal blocking light to improve sensor sensitivity, and the other is to use BDTI to isolate pixels Optical and electrical crosstalk with pixels. In addition, although the influence of peripheral devices on pixels has been considered in the design, shallow trench isolation is filled in the pixel area and peripheral logic area, but the effect of improving the signal-to-noise ratio is not ideal. For back-illuminated image sensors, while increasing the full well capacity of pixels, it is necessary to consider how to reduce "blooming", so it is necessary to design an additional "blooming protection" function module in the pixel array area to absorb overflowing charges and reduce damage to adjacent pixels. crosstalk.

Compared to front-illuminated image sensors, back-illuminated image sensors are more expensive and require individual pixel designs to address "blooming" and low-light noise issues. The traditional front-illuminated image sensor has a more mature process and has a huge advantage in cost.

Contents of the invention

In order to solve the problems existing in the prior art, an integrated technical solution with the function of "overlight overflow protection" and low read noise is proposed.

In one aspect, the present invention provides a method for forming a front-illuminated image sensor, including: forming a first N-type doped region in a substrate; wherein, the substrate includes a pixel array region; forming a second N-type doped region surrounding the pixel array region; wherein, the second N-type doped region is connected to the first N-type doped region and connected to a positive voltage of a certain potential; wherein, The first N-type doped region and the second N-type doped region constitute a discharge path for discharging excess charge generated in the pixel array region.

In some embodiments, the substrate at least includes a heavily doped P-type substrate, the first N-type doped region and the first P-type doped region sequentially formed on the heavily doped P-type substrate. region; said forming a first N-type doped region in the substrate includes: forming said first N-type doped region by epitaxial growth on said heavily doped P-type substrate; said first N-type doped region The impurity region is epitaxially grown to form the first P-type doped region.

In some embodiments, the formation of the second N-type doped region surrounding the pixel array region in the substrate includes: ion implantation in the first P-type doped region corresponding to the pixel array region A photosensitive unit array is formed; a second N-type doped region surrounding the pixel array region is formed in the substrate by ion implantation.

In some embodiments, the forming of the second N-type doped region surrounding the pixel array region in the substrate includes: by etching, in the first P-type doped region corresponding to the pixel array region Forming a plurality of first trenches, and forming second trenches in the first P-type doped region corresponding to the periphery of the pixel array region; forming a third N-type doped region under the second trenches by ion implantation The impurity region; the fourth N-type doped region is epitaxially filled in the plurality of first trenches to form a photosensitive cell array, and the fifth N-doped region is epitaxially filled in the second trench; wherein, the third The N-doped region and the fifth doped region form the second N-type doped region; wherein, the third N-type doped region combines the fifth doped region and the first N-doped region area connected.

In some embodiments, the substrate at least includes a heavily doped P-type substrate, a first P-type doped region formed on the heavily doped P-type substrate; The N-type doped region includes: forming the first P-type doped region by epitaxial growth on the heavily doped P-type substrate; forming the first P-type doped region in the first P-type doped region by ion implantation. an N-type doped region.

In some embodiments, forming the second N-type doped region surrounding the pixel array region in the substrate includes: forming a photosensitive unit array in the pixel array region by ion implantation; A second N-type doped region surrounding the pixel array region is formed in the substrate.

In some embodiments, the forming of the second N-type doped region surrounding the pixel array region in the substrate includes: by etching, in the first P-type doped region corresponding to the pixel array region Forming a plurality of first trenches, and forming second trenches in the first P-type doped region corresponding to the periphery of the pixel array region; forming a third N-type doped region under the second trenches by ion implantation The impurity region; the fourth N-type doped region is epitaxially filled in the plurality of first trenches to form a photosensitive cell array, and the fifth N-doped region is epitaxially filled in the second trench; wherein, the third The N-doped region and the fifth doped region form the second N-type doped region; wherein, the third N-type doped region combines the fifth doped region and the first N-doped region area connected.

In some embodiments, the substrate further includes a logic circuit region; the second N-type doped region surrounds the logic circuit region.

On the other hand, the present invention also provides a front-illuminated image sensor, comprising: a substrate with a pixel array region; a first N-type doped region disposed in the substrate; A second N-type doped region, which is disposed in the substrate and located above the first N-type doped region; wherein, the second N-type doped region is the same as the first N-type doped region Regions are connected and connected to a positive voltage of a certain potential; wherein, the first N-type doped region and the second N-type doped region form a discharge path for discharging excess charges generated in the pixel array region.

In some embodiments, the substrate further includes a logic circuit region; the second N-type doped region surrounds the logic circuit region.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects.

In the embodiment of the present invention, based on the existing front-illuminated image sensor structure, an N-type buried layer is added between the heavily doped P-type substrate and the P-type isolation layer at the bottom of the pixel photosensitive unit, connected to a high potential , take away the overflow electrons, and realize the "high light overflow protection function"; at the same time, increase the N-type ion implantation between the pixel array area and the peripheral logic circuit area to connect the N-type buried layer, and connect the high potential, so in the realization of the absorption overflow At the same time, it prevents the influence of substrate electronics and peripheral circuit electronics on the readout signal, and achieves a high signal-to-noise ratio.

Description of drawings

The accompanying drawings of the present invention constitute a part of this specification and are used for further understanding of the present invention. The accompanying drawings show embodiments of the present invention and are used together with the description to illustrate the principles of the present invention.

FIG. 1 is a method for forming a front-illuminated image sensor according to an embodiment of the present invention;

2 to 4 are schematic cross-sectional views of a front-illuminated image sensor according to an embodiment of the present invention;

5 to 8 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention;

9 to 12 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention;

13 to 17 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention.

Detailed ways

The following detailed description is exemplary and intended to provide further explanation of the present invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

FIG. 1 is a method for forming a front-illuminated image sensor according to an embodiment of the present invention. The method includes the following steps.

Step S1: forming a first N-type doped region in a substrate; wherein, the substrate includes a pixel array region.

Step S2: forming a second N-type doped region surrounding the pixel array region in the substrate; wherein, the second N-type doped region is connected to the first N-type doped region and connected to Positive voltage of a certain potential; wherein, the first N-type doped region and the second N-type doped region form a discharge path for discharging excess charges generated in the pixel array region.

The method for forming the front-illuminated image sensor in FIG. 1 will be described in detail below with reference to the accompanying drawings.

2 to 4 are schematic cross-sectional views of a front-illuminated image sensor according to an embodiment of the present invention. Each step of the method for forming the front-illuminated image sensor in FIG. 1 will be described in detail below with reference to FIGS. 2 to 4 .

For step S1 , referring to FIG. 2 , a first N-type doped region 102 is formed in the substrate 10 ; wherein, the substrate 10 includes a logic circuit region and a pixel array region.

Specifically, the substrate 10 at least includes a heavily doped P-type substrate 101, the first N-type doped region 102 and the first P-type doped region 102 sequentially formed on the heavily doped P-type substrate. District 103. The heavily doped P-type substrate 101 may be a single crystal silicon material. It should be noted that multiple layers of doped regions of different doping types may be formed on the heavily doped P-type substrate 101 , which will not be repeated here.

In a specific implementation manner, the forming of the first N-type doped region 102 in the substrate 10 includes the following steps.

The first N-type doped region 102 is formed by epitaxial growth on the heavily doped P-type substrate 101 .

The first P-type doped region 103 is formed by epitaxial growth in the first N-type doped region 102 . The specific parameters of the epitaxial process will not be repeated here.

For step S2, referring to FIG. 3 and FIG. 4, a second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10; wherein, the second N-type doped region 12 and the first An N-type doped region 102 is connected and connected to a positive voltage of a certain potential; wherein, the first N-type doped region 102 and the second N-type doped region 12 form an excess voltage generated by the pixel array region. The discharge path for charge discharge.

Specifically, forming the second N-type doped region surrounding the pixel array region in the substrate includes the following steps.

Referring to FIG. 3 , by ion implantation, a photosensitive cell array 11 is formed in the first P-type doped region 103 corresponding to the pixel array region.

Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

Referring to FIG. 4 , the second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10 by ion implantation. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

The second N-type doped region 12 is connected to the first N-type doped region 102 and connected to a positive voltage of a certain potential (for example, 2.8V or 3.3V); wherein, the first N-type The doped region 102 and the second N-type doped region 12 form a discharge path for discharging excess charges generated in the pixel array region. The second N-type doped region 12 serves as a vertical overflow drain (Vertical Over Flow Drain, VOFD), which together with the first N-doped region 102 constitutes an overflow drain.

In a specific implementation manner, the second N-type doped region 12 surrounds the logic circuit region.

5 to 8 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention. Each step of the method for forming the front-illuminated image sensor in FIG. 1 will be described in detail below with reference to FIGS. 5 to 8 .

For step S1 , referring to FIG. 5 , a first N-type doped region 102 is formed in the substrate 10 ; wherein, the substrate 10 includes a logic circuit region and a pixel array region.

Specifically, the substrate 10 at least includes a heavily doped P-type substrate 101, the first N-type doped region 102 and the first P-type doped region 102 sequentially formed on the heavily doped P-type substrate. District 103. The heavily doped P-type substrate 101 may be a single crystal silicon material. It should be noted that multiple layers of doped regions of different doping types may be formed on the heavily doped P-type substrate 101 , which will not be repeated here.

In a specific implementation manner, the forming of the first N-type doped region 102 in the substrate 10 includes: forming the first N-type doped region 102 by epitaxial growth on the heavily doped P-type substrate 101 ; forming the first P-type doped region 103 by epitaxial growth in the first N-type doped region 102 . The specific parameters of the epitaxial process will not be repeated here.

For step S2, referring to FIG. 6 to FIG. 8, a second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10; wherein, the second N-type doped region 12 and the first An N-type doped region 102 is connected and connected to a positive voltage of a certain potential; wherein, the first N-type doped region 102 and the second N-type doped region 12 form an excess voltage generated by the pixel array region. The discharge path for charge discharge.

Specifically, forming the second N-type doped region 12 surrounding the pixel array region in the substrate 10 may include the following steps.

Referring to FIG. 6, by etching, a plurality of first grooves 11a are formed in the first P-type doped region 103 corresponding to the pixel array region, and the first P-type doped regions corresponding to the periphery of the pixel array region A second trench 11 b is formed in the region 103 .

Referring to FIG. 7 , a third N-type doped region 121 is formed under the second trench 11 b by ion implantation. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

Referring to FIG. 8, the fourth N-type doped region 11 is epitaxially filled in the plurality of first trenches 11a to form the photosensitive cell array 11, and the fifth N-doped region 122 is epitaxially filled in the second trench 11b. . Wherein, the second N-type doped region 12 is composed of the third N-doped region 121 and the fifth doped region 122; wherein, the third N-type doped region 121 combines the fifth doped region The region 122 is connected to the first N-doped region 102 . The second N-type doped region 12 serves as a VOFD, which together with the first N-doped region 102 constitutes an overflow drain.

In a specific implementation manner, the second N-type doped region 12 surrounds the logic circuit region.

9 to 12 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention. Each step of the method for forming the front-illuminated image sensor in FIG. 1 will be described in detail below with reference to FIGS. 9 to 12 .

For step S1 , referring to FIG. 9 and FIG. 10 , a first N-type doped region 102 is formed in the substrate 10 ; wherein, the substrate 10 includes a logic circuit region and a pixel array region.

Specifically, the substrate 10 at least includes a heavily doped P-type substrate 101 and a first P-type doped region 103 formed on the heavily doped P-type substrate. The heavily doped P-type substrate 101 may be a single crystal silicon material. It should be noted that multiple layers of doped regions of different doping types may be formed on the heavily doped P-type substrate 101 , which will not be repeated here.

In a specific implementation manner, the forming of the first N-type doped region 102 in the substrate 10 includes the following steps.

Referring to FIG. 9 , the first P-type doped region 103 is epitaxially grown on the heavily doped P-type substrate 101 ; specific parameters of the epitaxial process will not be repeated here.

Referring to FIG. 10 , the first N-type doped region 102 is formed in the first P-type doped region 103 by ion implantation. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

For step S2, referring to FIG. 11 and FIG. 12 , a second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10; wherein, the second N-type doped region 12 and the first An N-type doped region 102 is connected and connected to a positive voltage of a certain potential; wherein, the first N-type doped region 102 and the second N-type doped region 12 form an excess voltage generated by the pixel array region. The discharge path for charge discharge.

Specifically, forming the second N-type doped region 12 surrounding the pixel array region in the substrate 10 may include the following steps.

Referring to FIG. 11 , by ion implantation, a photosensitive unit array 11 is formed in the pixel array area. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

Referring to FIG. 12 , by ion implantation, a second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10 . Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

The second N-type doped region 12 is connected to the first N-type doped region 102 and connected to a positive voltage of a certain potential (for example, 2.8V or 3.3V); wherein, the first N-type The doped region 102 and the second N-type doped region 12 form a discharge path for discharging excess charges generated in the pixel array region. The second N-type doped region 12 serves as a vertical overflow drain VOFD, which together with the first N-type doped region 102 forms an overflow drain.

In a specific implementation manner, the second N-type doped region 12 surrounds the logic circuit region.

13 to 17 are schematic cross-sectional views of a front-illuminated image sensor according to another embodiment of the present invention. Each step of the method for forming the front-illuminated image sensor in FIG. 1 will be described in detail below with reference to FIGS. 13 to 17 .

For step S1 , referring to FIG. 13 and FIG. 14 , a first N-type doped region 102 is formed in the substrate 10 ; wherein, the substrate 10 includes a logic circuit region and a pixel array region.

Specifically, the substrate 10 at least includes a heavily doped P-type substrate 101 and a first P-type doped region 103 formed on the heavily doped P-type substrate. It should be noted that multiple layers of doped regions of different doping types may be formed on the heavily doped P-type substrate 101 , which will not be repeated here.

In a specific implementation manner, the forming of the first N-type doped region 102 in the substrate 10 includes the following steps.

Referring to FIG. 13 , the first P-type doped region 103 is epitaxially grown on the heavily doped P-type substrate 101 ; specific parameters of the epitaxial process will not be repeated here.

Referring to FIG. 14 , the first N-type doped region 102 is formed in the first P-type doped region 103 by ion implantation. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

For step S2, referring to FIG. 15 to FIG. 17, a second N-type doped region 12 surrounding the pixel array region is formed in the substrate 10; wherein, the second N-type doped region 12 and the first An N-type doped region 102 is connected and connected to a positive voltage of a certain potential; wherein, the first N-type doped region 102 and the second N-type doped region 12 form an excess voltage generated by the pixel array region. The discharge path for charge discharge.

Specifically, forming the second N-type doped region 12 surrounding the pixel array region in the substrate 10 may include the following steps.

Referring to FIG. 15, by etching, a plurality of first trenches 11a are formed in the first P-type doped region 103 corresponding to the pixel array region, and the first P-type doped regions corresponding to the periphery of the pixel array region A second trench 11 b is formed in the region 103 .

Referring to FIG. 16 , a third N-type doped region 121 is formed under the second trench 11 b by ion implantation. Specifically, a patterned mask layer (not shown in the figure) may be formed on the substrate 10 . The material of the mask layer may be photoresist material, silicon nitride, silicon oxide, silicon oxynitride and the like. The process parameters of the ion implantation will not be repeated here.

Referring to FIG. 17, the fourth N-type doped region 11 is epitaxially filled in the plurality of first trenches 11a to form the photosensitive cell array 11, and the fifth N-doped region 122 is epitaxially filled in the second trench 11b. . Wherein, the second N-type doped region 12 is composed of the third N-doped region 121 and the fifth doped region 122; wherein, the third N-type doped region 121 combines the fifth doped region The region 122 is connected to the first N-doped region 102 . The second N-type doped region 12 serves as a VOFD, which together with the first N-doped region 102 constitutes an overflow drain.

In a specific implementation manner, the second N-type doped region 12 surrounds the logic circuit region.

An embodiment of the present invention also provides a front-illuminated image sensor, including: a substrate, the pixel array area; a first N-type doped area, which is arranged in the substrate; a second pixel array area surrounded by An N-type doped region, which is disposed in the substrate and located above the first N-type doped region; wherein, the second N-type doped region is the same as the first N-type doped region connected, and connected in parallel to a positive voltage of a certain potential; wherein, the first N-type doped region and the second N-type doped region form a discharge path for discharging excess charges generated in the pixel array region.

In a specific implementation manner, the substrate 10 further includes a logic circuit region; the second N-type doped region 12 surrounds the logic circuit region.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A method for forming a front-illuminated image sensor, comprising: A first N-type doped region is formed in the substrate; wherein the substrate includes a pixel array region; A second N-type doped region surrounding the pixel array region is formed in the substrate; wherein, the second N-type doped region is connected to the first N-type doped region and connected to a certain potential positive voltage; Wherein, the first N-type doped region and the second N-type doped region constitute a discharge path for discharging excess charges generated in the pixel array region. 2. The forming method according to claim 1, wherein the substrate at least comprises a heavily doped P-type substrate, and the first N-type substrate sequentially formed on the heavily doped P-type substrate. a doped region and a first p-type doped region; The forming of the first N-type doped region in the substrate includes: forming the first N-type doped region by epitaxial growth on the heavily doped P-type substrate; The first P-type doped region is formed by epitaxial growth in the first N-type doped region. 3. The forming method according to claim 2, wherein forming the second N-type doped region surrounding the pixel array region in the substrate comprises: forming a photosensitive unit array in the first P-type doped region corresponding to the pixel array region by ion implantation; A second N-type doped region surrounding the pixel array region is formed in the substrate by ion implantation. 4. The forming method according to claim 2, wherein forming the second N-type doped region surrounding the pixel array region in the substrate comprises: By etching, a plurality of first grooves are formed in the first P-type doped region corresponding to the pixel array region, and a second groove is formed in the first P-type doped region corresponding to the periphery of the pixel array region groove; forming a third N-type doped region under the second trench by ion implantation; Epitaxially filling the fourth N-type doped regions in the plurality of first trenches to form a photosensitive cell array, and epitaxially filling the fifth N-doped regions in the second trenches; Wherein, the second N-type doped region is composed of the third N-doped region and the fifth doped region; wherein, the third N-type doped region combines the fifth doped region with the The first N-doped regions are connected. 5. The forming method according to claim 1, wherein the substrate comprises at least a heavily doped P-type substrate, a first P-type doped region formed on the heavily doped P-type substrate ; The forming of the first N-type doped region in the substrate includes: forming the first P-type doped region by epitaxial growth on the heavily doped P-type substrate; The first N-type doped region is formed in the first P-type doped region by ion implantation. 6. The forming method according to claim 5, characterized in that, The formation of the second N-type doped region surrounding the pixel array region in the substrate includes: By ion implantation, an array of photosensitive units is formed in the pixel array area; A second N-type doped region surrounding the pixel array region is formed in the substrate by ion implantation. 7. The forming method according to claim 5, wherein forming the second N-type doped region surrounding the pixel array region in the substrate comprises: By etching, a plurality of first grooves are formed in the first P-type doped region corresponding to the pixel array region, and a second groove is formed in the first P-type doped region corresponding to the periphery of the pixel array region groove; forming a third N-type doped region under the second trench by ion implantation; Epitaxially filling the fourth N-type doped regions in the plurality of first trenches to form a photosensitive cell array, and epitaxially filling the fifth N-doped regions in the second trenches; Wherein, the second N-type doped region is composed of the third N-doped region and the fifth doped region; Wherein, the third N-type doped region connects the fifth doped region with the first N-doped region. 8. The forming method according to any one of claims 1 to 7, wherein the substrate further comprises a logic circuit region; the second N-type doped region surrounds the logic circuit region. 9. A front-illuminated image sensor, comprising: a substrate, its pixel array region; a first N-type doped region disposed within the substrate; A second N-type doped region surrounding the pixel array region, which is disposed in the substrate and located above the first N-type doped region; wherein, the second N-type doped region and the The first N-type doped regions are connected and connected to a positive voltage of a certain potential; Wherein, the first N-type doped region and the second N-type doped region constitute a discharge path for discharging excess charges generated in the pixel array region. 10 . The front-illuminated image sensor according to claim 9 , wherein the substrate further comprises a logic circuit region; and the second N-type doped region surrounds the logic circuit region. 11 .