CN116636015A - Semiconductor device, manufacturing method thereof, and terminal equipment - Google Patents

Abstract

The present application provides a semiconductor device, a manufacturing method thereof, and a terminal device, which can reduce the current collapse effect of transistors in the semiconductor device. The semiconductor device is provided with a transistor, and the transistor includes a channel layer and a barrier layer stacked; the epitaxial part of the channel layer and the barrier layer is formed with a doped isolation region, and the epitaxial part of the channel layer and the barrier layer It is truncated on the outside of the doped isolation region to form a cross section.

Description

Semiconductor device, manufacturing method thereof, and terminal equipment technical field

The present application relates to the technical field of semiconductors, and in particular to a semiconductor device, a manufacturing method thereof, and a terminal device.

Background technique

GaN HEMT (high electron mobility transistor, high electron mobility transistor) has developed rapidly in the past 30 years. Compared with GaAs HEMT, GaN HEMT has higher breakdown voltage, higher electron saturation velocity, higher frequency and other advantages , are widely used in microwave devices and power electronics and other fields.

The current collapse effect (the phenomenon that the DC characteristics of the device degrade significantly after a certain period of DC bias stress is applied to the device) is a key factor affecting the performance of GaN HEMT devices. The power is reduced; therefore, reducing the collapse effect of the device has become a research hotspot in the current industry.

Contents of the invention

Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and a terminal device, which can reduce the current collapse effect of transistors in the semiconductor device.

The present application provides a semiconductor device, which is provided with a transistor; the transistor includes an active layer arranged in an active region; wherein, the active layer includes a stacked channel layer and a barrier layer; in addition, the The transistor also includes a non-active region disposed around the active region and a doped isolation region in the epitaxial portion of the active layer; Doping isolation regions are partially provided (that is, doping isolation is used), so that effective isolation of the active region of the transistor can be realized on the basis of ensuring that no leakage occurs on the sidewall of the active layer.

On this basis, in this semiconductor device, the epitaxial part of the active layer of the transistor is truncated outside the doped isolation region to form a section; in this way, the built-in part of the active layer can be released at the location of the section. Stress can reduce the current collapse effect of transistors, increase the output power of transistors, and improve the performance of semiconductor devices.

In some possible implementation manners, in the semiconductor device, a passivation material may be covered on the section to protect the section.

In some possible implementations, the semiconductor device may include two transistors (a first transistor and a second transistor) arranged adjacently on the same layer, and the cross-sectional area provided on the epitaxial part of the active layer between the two transistors into grooves.

In some possible implementation manners, the groove may be filled with a passivation material to protect the section surrounding the groove.

In some possible implementations, the cross section is located at the outer edge of the doped isolation region (that is, the edge away from the active region); in this case, the size of the transistor can be reduced, thereby expanding the application range of the transistor.

In some possible implementations, the cross section can run through the entire thickness of the epitaxial part of the active layer; in this case, the built-in stress generated by the active layer can be released to the greatest extent, thereby improving the current collapse of the transistor to a greater extent effect.

In some possible implementations, the above-mentioned transistor further includes: a source, a drain, and a gate connected to the surface of the barrier layer; passivation layer, and the first surface passivation layer covers the section. In this case, the first surface passivation layer covers the active area of the transistor and extends to cover the surface of the non-active area and the surface of the section.

Certainly, in the case that the aforementioned semiconductor device includes two transistors arranged adjacently in the same layer, the aforementioned first surface passivation layer may cover the entire surface of the aforementioned groove structure formed between the adjacent two transistors.

In some possible implementations, the transistor also includes a buffer layer; the buffer layer is located on the side of the channel layer away from the barrier layer; the depth of the doped isolation region extends into the buffer layer; to ensure that the doped isolation region is on the potential barrier Effective isolation of the two-dimensional electron gas generated at the heterointerface position of the layer and the channel layer.

In some possible implementations, the semiconductor device further includes: a second surface passivation layer; the second surface passivation layer is located on the surface of the active layer and the epitaxial part of the active layer; the potential is stabilized by the second surface passivation layer The surface state of the barrier layer, thereby improving the current collapse effect of the transistor.

In some possible implementation manners, GaN is used for the channel layer; at least one of AlGaN, AlGaInN, and AlInN is used for the barrier layer.

In some possible implementation manners, N ion implantation may be used in the above-mentioned doped isolation region.

The embodiment of the present application also provides a method for manufacturing a semiconductor device, including:

A buffer layer, a channel film layer, and a barrier film layer are sequentially formed on the substrate.

Ion implantation is performed around the active area of the transistor in the channel film layer and the barrier film layer to form a doped isolation area.

At the position where the doped isolation region close to at least part of the width of the active region remains, the channel film layer and the barrier film layer are etched by mesa to form a cross section.

Using the manufacturing method of the semiconductor device provided by its own embodiment, on the one hand, by setting and forming the doped isolation region (that is, using doped isolation) in the epitaxial part of the integral structure with the active layer, it is possible to ensure that the active layer On the basis of no leakage on the side wall, the effective isolation of the active region of the transistor is realized; on the other hand, the epitaxial part of the integral structure with the active layer is located outside the doped isolation region to form a cross-section through mesa etching, so that The built-in stress generated by the active layer can be released at the cross-section position, thereby reducing the current collapse effect of the transistor, increasing the output power of the transistor, and improving the performance of the semiconductor device.

In some possible implementation manners, the manufacturing method of the above-mentioned semiconductor device further includes:

A second surface passivation layer is formed on the surface of the formed barrier film layer.

In the active region, a source, a drain, and a gate connected to the surface of the barrier film layer are formed on the surface of the passivation layer on the second surface.

A first surface passivation layer is formed on the surfaces of the source electrode, the drain electrode, and the gate electrode, and the first surface passivation layer covers the aforementioned section.

An embodiment of the present application further provides a terminal device, where the terminal device includes the semiconductor device provided in any one of the foregoing possible implementation manners.

Description of drawings

FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

FIG. 4 is a collapse curve of a transistor provided by an embodiment of the present application and a transistor provided by related technologies;

FIG. 5 is a flowchart of a method for manufacturing a transistor provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram during the fabrication process of a transistor provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram during the fabrication process of a transistor provided in an embodiment of the present application;

FIG. 8 is a schematic structural diagram during the fabrication process of a transistor provided in an embodiment of the present application;

FIG. 9 is a schematic structural diagram during the fabrication process of a transistor provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. "At least one (item)" means one or more, and "multiple" means two or more. Words such as "connected" and "connected" are used to express intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which components are placed in the drawings.

The embodiment of the present application provides a terminal device, which can be electronic products such as mobile phones, tablet computers, notebooks, vehicle-mounted computers, smart watches, and smart bracelets; the embodiment of the present application does not specifically limit the specific form of the terminal device .

The above-mentioned terminal equipment is provided with a semiconductor device, such as a power device, a radio frequency device, etc., and the semiconductor device is provided with a high electron mobility transistor (high electron mobility transistor, HEMT) using gallium nitride (GaN) material, that is, a GaN HEMT (hereinafter may be simply referred to as a transistor).

It is understandable that large-size GaN self-supporting substrates are relatively expensive. At present, GaN materials are generally grown on heterogeneous substrates (Si, sapphire, SiC, etc.). Due to the problems of lattice mismatch and thermal mismatch in different materials, As a result, the GaN material is usually a material with a high defect density, and the GaN film layer formed at the same time will have a large built-in stress. These defects and stress will lead to the existence of trap levels in the GaN material, which will then capture the 2DEG (2- Dimension electron gas, two-dimensional electron gas), causing the current collapse effect, resulting in a decrease in the saturation current and output power of the transistor device.

Based on this, the semiconductor device in the terminal device of the embodiment of the present application adopts a transistor, which can reduce (relieve) the built-in stress of the transistor device, improve the current collapse effect, further increase the output power of the transistor, and improve the performance of the semiconductor device.

The arrangement of the transistors in the semiconductor device provided by the embodiment of the present application will be described in detail below.

As shown in FIG. 1 , for a transistor, it can generally be divided into an active area A1 and a non-active area A2 (also called a passive area) located around the active area A1 .

Those skilled in the art can understand that, for the active area A1, it refers to the area that ensures the normal operation of the transistor, such as the source S (source), drain D (drain), and gate G (gate) in the transistor. ) and the conduction area covered by the conductive channel. As for the non-active area A2 around the active area A1, it can isolate the active area A1 of the transistor, so as to ensure the normal operation of the active area A1 of the transistor.

As shown in FIG. 1 , in this transistor, a substrate 1 and a buffer layer 2 (buffer layer) disposed on the substrate 1 are included, and the active region A1 includes trenches sequentially stacked on the buffer layer 2 (buffer layer). Channel layer 3 (channel layer), barrier layer 4 (barrier layer); wherein, channel layer 3 and barrier layer 4 can also be collectively referred to as active layer, hereinafter can be abbreviated as active layer (3 and 4); In addition , the transistor includes an epitaxial portion 3' of the channel layer 3 and an epitaxial portion 4' of the barrier layer 4 in the non-active region A2, that is, the epitaxial portions (3' and 4') of the active layer.

For the above-mentioned active layers (3 and 4) and the epitaxial parts (3' and 4') of the active layer, it can be understood that the active layers (3 and 4) and the epitaxial parts of the active layer (3' and 4') are an integral structure of the same layer and material.

Of course, in some possible implementations, a surface passivation layer 5 (also referred to as a second surface passivation layer) may be provided on the surface of the barrier layer 4, and the surface passivation layer 5 stabilizes the barrier layer 4. surface state, thereby improving the current collapse effect of the transistor; the following embodiments are all schematically illustrated by taking the surface passivation layer 5 disposed in the transistor as an example.

Schematically, the above-mentioned substrate 1 can be a Si substrate, a sapphire substrate, a SiC substrate, etc.; the above-mentioned buffer layer 2 can be made of materials such as AlN, AlGaN with a graded composition, AlGaN/GaN superlattice, and doped GaN; the above-mentioned channel layer 3. AlGaN or GaN with high quality (that is, low impurity content and low dislocation density) can be used; the above-mentioned barrier layer 4 can be at least one of AlGaN, AlGaInN, and AlInN; for example, in some possible implementation methods, The channel layer 3 may be GaN, and the barrier layer 4 may be AlGaN.

On this basis, as shown in FIG. 1, the transistor is located in the non-active region A2 in the epitaxial part (3' and 4') of the active layer, and a doped isolation region C is arranged around the active region A1 (It can also be referred to as an implantation isolation region); the doping depth d of the doping isolation region C should at least penetrate the barrier layer 4 and the channel layer 3, to ensure the heterogeneous interface between the barrier layer 4 and the channel layer 3 The two-dimensional electron gas (2DEG) generated at the position is effectively isolated.

It can be understood that, for the above-mentioned doped isolation region C disposed in the epitaxial part (3' and 4') of the active layer, it means that the doped isolation region C and the epitaxial part (3') of the active layer and 4') are obtained after the body is ion-doped; schematically, in some possible implementations, the doped isolation region C can be the epitaxial part (3' and 4) of the active layer in the non-active region A2 ') obtained after N ion doping.

Of course, in some possible implementations, as shown in FIG. 1, the doping depth of the doped isolation region C can penetrate to the buffer layer 2, that is, the doped isolation region C is doped into the buffer layer 2; the following embodiments All are described with this example.

On this basis, as shown in Figure 1 and Figure 2, in the transistor provided by the embodiment of the present application, the epitaxial parts (3' and 4') of the active layer are truncated outside the doped isolation region C to form a cross-section M; that is, the epitaxial part (3' and 4') of the active layer is truncated on the side of the doped isolation region C away from the active region A1 to form a section M; in this case, the active layer can be released through the section M The built-in stress generated by (3 and 4) can improve the current collapse effect of the transistor.

It should be noted here that, referring to FIG. 1 , in the case where the surface passivation layer 5 is provided in the transistor, the surface passivation layer 5 covers the surface of the barrier layer 4 located in the active region A1, and extends to cover the surface of the non-active region A1. The surface of the epitaxial portion 4' of the barrier layer in the active region A2; in this case, the doped isolation region C can be obtained by ion implantation downward from the surface of the surface passivation layer 5; it should be understood that the doped isolation region The setting of area C is mainly to realize the effective isolation of two-dimensional electron gas (2DEG) in the active layer (3 and 4), and the setting of section M is also for the release of the built-in stress in the active layer (3 and 4), so , the relevant settings of the doped isolation region C and the cross-section M in the embodiment of the present application are mainly schematically illustrated for the active layers (3 and 4) and their epitaxial parts (3' and 4').

In addition, it should be noted that Fig. 1 and Fig. 2 are only schematic illustrations of a single transistor (also called a first transistor) in a semiconductor device, and in some possible implementations, the semiconductor device may Including setting multiple transistors on the same layer, that is, each layer structure in the multiple transistors (such as the aforementioned 2, 3, 4, etc.) is respectively located on the same layer, and each layer structure of the multiple transistors is produced through the same process; here In this case, as shown in FIG. 3, for two adjacent transistors (also referred to as the first transistor Q and the second transistor Q'), the two adjacent transistors (Q and Q') can be The epitaxial part (3' and 4') of the active layer between the two transistors (Q and Q') in the epitaxial part (3' and 4') of the active layer to form the aforementioned section M ; In this case, the cross section M in two adjacent transistors (Q and Q') forms a groove T.

Of course, for semiconductor devices, as shown in Fig. 1, Fig. 2 and Fig. 3, in order to protect the cross-section M to a certain extent, the cross-section M can be covered with a passivation material; For semiconductor devices such as transistors, the groove T may be filled (or covered) with a passivation material. Schematically, the section M (or the groove T) can be covered by a passivation film layer fabricated subsequently (such as the surface passivation layer 6 mentioned below, refer to the relevant description below).

In addition, for the relative position of the doped isolation region C and the section M:

In some possible implementations, as shown in Figure 1, the epitaxial parts (3' and 4') located in the active layer can all be set as doped isolation regions C, and the section M is located in the doped isolation region C away from the active region The edge of one side of A1, that is, the section M is located at the outer edge of the doped isolation region C.

In this case, in the case where multiple transistors are provided in a semiconductor device, as shown in FIG. 3 , the non-active area A2 between the active areas A1 of two adjacent transistors (Q and Q') can be A doped isolation region C is provided as a whole, and a section M is formed by making a groove T in the doped isolation region C.

In some possible implementations, as shown in FIG. 2 , in the epitaxial part (3' and 4') of the active layer, a region with a certain width adjacent to the active region A1 is set as a doped isolation region C, while the doped The side of the heterogeneous isolation region C away from the active region A1 retains a part of the region that has not been ion-doped; in this case, the section M is located in the epitaxial part (3' and 4') of the active layer without ion doping The outer edge of the part (that is, the edge away from the side of the doped isolation region C).

In this case, in the case where a plurality of transistors are provided in a semiconductor device, doped isolation regions C can be respectively provided for two adjacent transistors (Q and Q'), and the two doped isolation regions C remain between part of the region that is not ion-doped, and make a groove T in the part of the region that is not ion-doped to form a section M.

It can be understood that, compared to the part of the doped isolation region C that is far away from the active region A1 shown in FIG. In the case of doped isolation regions C) with the same width, the epitaxial parts (3' and 4') of the active layer shown in Figure 1 are all set as doped isolation regions C, which can reduce the size of the transistor, and thus can expand the transistor scope of application.

In addition, it should be noted that, in Fig. 1, Fig. 2 and Fig. 3, the section M perpendicular to the substrate 1 is schematically illustrated as an example, but the present application is not limited thereto, and the actual section M may also be parallel to the substrate 1. There is a certain inclination angle between them, for example, the section M can be inclined toward the side of the active region A1, or it can be inclined toward the side away from the active region A1; this application is not limited to this, and it can be set according to process requirements in practice That's it.

To sum up, in the transistor used in the semiconductor device provided by the embodiment of the present application, by setting the doped isolation region C in the epitaxial part of the integral structure with the active layer (3 and 4) (that is, using doped isolation) , so that on the basis of ensuring that the sidewalls of the active layers (3 and 4) do not leak, the effective isolation of the active region of the transistor can be realized; and the epitaxial part (3' and 4 ') A section M is cut off outside the doped isolation region C, so that the built-in stress generated by the active layer (3 and 4) can be released at the location of the section M, thereby reducing the current collapse effect of the transistor and improving the transistor's performance. output power, improving the performance of semiconductor devices.

In addition, in the present application, there is no limitation on the depth of the cross-section M located outside the doped isolation region C. For example, in some possible implementations, the section M may not run through the entire thickness of the epitaxial parts (3' and 4') of the active layer. For another example, in some possible implementations, as shown in FIG. 1, FIG. 2, and FIG. 3, the section M can run through the entire thickness of the epitaxial parts (3' and 4') of the active layer, and can even run through to the buffer layer 2 in.

It can be understood that, compared to the fact that the cross-section M does not penetrate through the entire thickness of the epitaxial parts (3' and 4') of the active layer, by setting the cross-section M through the epitaxial parts (3' and 4') of the active layer The entire thickness can release the built-in stress generated by the active layer (3 and 4) to the greatest extent, thereby improving the current collapse effect to a greater extent.

In addition, it can also be understood that, as shown in FIG. 1 and FIG. 2 , the transistor further includes: a source S, a drain D, and a gate G connected to the surface of the barrier layer 4 . Of course, when the surface passivation layer 5 is provided on the surface of the barrier layer 4 , the source S, the drain D, and the gate G can be connected to the surface of the barrier layer 4 through the hollowed-out area on the surface passivation layer 5 . Schematically, the surface of the source S, the drain D and the barrier layer 4 may be in ohmic contact, and the surface of the gate G and the barrier layer 4 may be in Schottky contact.

On this basis, as shown in FIG. 1 and FIG. 2 , in some possible implementations, the semiconductor device also includes surface passivation provided on the side of the source S, drain D, and gate G away from the substrate 1 Layer 6 (also referred to as the first surface passivation layer), the surface passivation layer 6 covers the active region A1 of the transistor, and extends to cover the surface of the non-active region A2 and the surface of the section M; that is to say , for the semiconductor device of the present application, the surface passivation layer 6 not only covers the surface of the active region A1 and the non-active region A2 of the transistor, but also covers the surface of the section M located in the non-active region A2.

For the case where a plurality of transistors are arranged in a semiconductor device, as shown in FIG. 3 , the above-mentioned surface passivation layer 6 can cover the surface of the entire groove T; The passivation layer 6 can fill the body part of the groove T. As shown in FIG.

It should be noted that the surface passivation layer (5, 6) in the present application can use at least one of materials such as silicon nitride (such as SiN), silicon oxide (such as SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc. The present application does not specifically limit this, and it can be set according to actual needs; for illustration, in some possible implementation manners, the surface passivation layer 5 and the surface passivation layer 6 can use SiN.

The transistor provided with the cross-section M provided in the embodiment of the present application to improve the current collapse effect is further verified and described below in conjunction with the transistor without the cross-section M.

Referring to the transistor without section M shown in FIG. 4 (such as the isolation between two adjacent transistors only by the doped isolation region C) and the collapse curve of the transistor with section M in FIG. 3, wherein the curve 1a (dotted line) and curve 1b (solid line) are the pulse output curves of the transistor with cross-section M and the transistor without cross-section M under zero stress respectively. It can be seen that the two curves basically coincide, that is to say, the two transistors have zero The output current (two-dimensional electron gas density) under stress is the same; curve 2a (dotted line) and curve 2b (solid line) are the applied stress of the transistor with section M and the transistor without section M respectively (for example, the electrical stress condition is Vgs=-10V, Vds=100V, the pulse output curve after the stress time is 1ms), it can be seen that the output current of the transistor with cross-section M is significantly reduced compared with the output current of the transistor without cross-section M, thus further It is verified that the setting of the section M can release the built-in stress generated by the active layer (3 and 4), thereby improving the current collapse effect.

In addition, the following table shows three transistors including transistors (A-1, A-2, A-3) without cross-section M and transistors (B-1, B-2, B-3) with cross-section M. The relevant test parameters of output power (Pout), linear gain (linear gain), and drain efficiency (drain efficiency) under the maximum power match (max power match) and maximum efficiency match (max efficiency match) of each device.

It can be seen from the above table that the average output power (46.7dBm) of the transistors with section M set (B-1, B-2, B-3) is significantly higher than that of the transistors without section M (A-1, A-2 , A-3) average output power (46.1dBm), which further verified that the current collapse effect is improved by setting the section M, and the saturation current in the actual operation of the transistor is increased, thereby increasing the output power.

In addition, it can also be seen from the above table that the transistors (A-1, A-2, A-3) without cross-section M and the transistors (B-1, B-2, B-3) with cross-section M, both The average linear gain and the average drain efficiency are similar, which shows that setting the cross-section M does not affect other properties of the transistor.

In addition, the embodiment of the present application also provides a method for manufacturing a semiconductor device (refer to FIG. 1 ), as shown in FIG. 5 , the method may include:

Step 01 , as shown in FIG. 6 , sequentially form a buffer layer 2 , a channel film layer 30 , and a barrier film layer 40 on a substrate 1 .

Schematically, in some possible implementations, as shown in FIG. 6 , after the formation of the barrier film layer 40 in the above step 01, a step 01' may also be included: forming a surface passivation layer on the surface of the barrier film layer 40 5.

Schematically, in some possible implementation manners, the above step 01 may include: referring to FIG. 6, setting the Si substrate (1), and cleaning the surface of the Si substrate (1); A buffer layer 2 (thickness can be about 2 μm) of AlN/GaN material grown on the surface; a channel film layer 30 (thickness can be about 200 nm) of GaN material and a barrier film layer of AlGaN material grown on the surface of the buffer layer 2 40 (thickness may be about 20nm, Al content may be 18%).

After that, a surface passivation layer 5 of SiN material can be formed on the surface of the barrier film layer 40 through step 01'.

Step 02 , referring to FIG. 7 , perform ion implantation around the active region A1 of the transistor where the channel film layer 30 and the barrier film layer 40 are located, to form a doped isolation region C.

It can be understood here that, as shown in FIG. 1 and FIG. 7 , the inner region surrounded by the doped isolation region C constitutes the active region A1 of the transistor, and the channel film layer 30 and the barrier film layer 40 are located in the active region A1. The part of the source region A1 is respectively used as the channel layer 3 and the barrier layer 4 (that is, the active layer) of the transistor, so as to realize the two-dimensional electron gas ( 2DEG) transmission.

Schematically, as shown in FIG. 7 , the above-mentioned step 02 may include: corresponding to the area adjacent to the active area A1 of the transistor in the aforementioned formed surface passivation layer 5 (that is, in the non-active area that is adjacent to the active area) Neighboring regions) are implanted with N ions to form a doped isolation region C at least penetrating through the channel film layer 30 and the barrier film layer 40; wherein, the implantation depth of the ion implantation can be 300 nm.

Step 03, referring to FIG. 8 , at the position where at least part of the width of the doped isolation region C near the side of the active region A1 is reserved, perform mesa etching on the channel film layer 30 and the barrier film layer 40 to form a section M .

It should be noted here that the specific width of the above-mentioned doped isolation region C reserved on the side close to the active region A1 can be set according to the actual needs of the transistor, which is not specifically limited in this application.

Schematically, the above step 03 may include: at the position where the doped isolation region C close to the partial width of the active region A1 is reserved (refer to FIG. 8 ), or at the side of the doped isolation region C away from the active region A1 ( That is, the position of the doped isolation region C) close to the full width of the active region A1 is reserved (refer to FIG. 2), and the surface passivation layer 5, the channel film layer 30, and the barrier film layer 40 are mesa etched, thereby A section M is formed at the edge position where the channel film layer 30 and the potential barrier film layer 40 are located in the non-active region A2; in this way, for the transistor, the channel film layer 30 and the potential barrier film layer 40 can position, the built-in stress generated by the channel layer 3 and the barrier layer 4 (that is, the part of the channel film layer 30 and the barrier film layer 40 located in the active region A1 ) is released, thereby improving the current collapse effect of the transistor.

It should be noted here that, as shown in FIG. 3 , in the case that the manufactured semiconductor device includes a plurality of transistors, a continuous transistor (Q and Q') can be formed between two adjacent transistors (Q and Q') through the above step 02. Doping the isolation region C; and performing mesa etching in the doping isolation region C through step 03 to form a groove T, thereby forming a section M at the edge of the two transistors (Q and Q').

It should also be noted that when performing mesa etching on the surface passivation layer 5 , the channel film layer 30 , and the barrier film layer 40 , the etching depth can be controlled according to actual needs. Schematically, the etching depth can go through the entire thickness of the channel film layer 30 and the barrier film layer 40 , and etch into the buffer layer 2 ; of course, it can also be etched into the substrate 1 .

In addition, it can be understood that on the basis of the above steps 01 to 03, the fabrication of semiconductor devices may also include the fabrication of other components, such as the fabrication of source S, drain D, gate G, etc.; Schematically, the manufacturing method of the semiconductor device may further include:

Step 04 , referring to FIG. 9 , in the active region A1 , a source S, a drain D, and a gate G connected to the barrier film layer 40 are formed on the surface of the previously formed surface passivation layer 5 .

Schematically, in some possible implementation manners, the above step 04 may include: referring to FIG. Said potential barrier layer 4), and form the source electrode S and the drain electrode D of Ti/Al/Ni/Au composite layer structure in this hollowed-out area and form the ohmic contact with the barrier film layer 40 surface, and carry out annealing; , the surface passivation layer 5 is partially etched in the active region A1 to form a hollow area to expose the barrier film layer 40 (also can be said to be a barrier layer 4), and to form a surface similar to that of the barrier film layer 40 in the hollow area. A gate G with a Ni/Pt/Au composite layer structure with a tertiary contact.

It should be noted here that there is no necessary sequence for the formation of the source S and the drain D in the above step 04, the formation of the gate G, and the formation of the doped isolation region C in the aforementioned step 02. The sequence number of the steps used in the application does not represent a necessary production sequence, and the specific production sequence can be selected according to actual needs. For example, in some possible ways of implementation, the fabrication of the source S and the drain D in step 04 can be carried out first, and then the fabrication of the doped isolation region C in step 02 can be performed, and then the fabrication of the gate Very G production.

Step 05 , referring to FIG. 9 to FIG. 1 , form a surface passivation layer 6 on the surfaces of the source S, the drain D, and the gate G, and the surface passivation layer 6 extends to cover the surface of the section M.

Schematically, as shown in FIG. 9 to FIG. 1 , in some possible implementations, the above step 05 may include: forming a surface passivation layer 6 of SiN material on the surfaces of the source S, the drain D, and the gate G, The surface passivation layer 6 is on the surface of the active region A1 and the non-active region A2 of the entire transistor, and extends to cover the surface of the section M.

Regarding other related content in the embodiment of the manufacturing method of the above-mentioned semiconductor device, such as in the case of setting multiple transistors in the semiconductor device, regarding the specific setting and manufacturing of the doped isolation region C and the cross-section M, you can refer to the aforementioned semiconductor device accordingly. The corresponding parts in the embodiments will not be described here; for the relevant structures in the aforementioned semiconductor devices, reference can be made to the corresponding manufacturing method embodiments of the above-mentioned semiconductor devices, or appropriate adjustments can be made in combination with related technologies. Applications are not limited to this.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (12)

1. A semiconductor device comprising a first transistor;

   the first transistor includes: a channel layer and a barrier layer which are stacked;

   a doped isolation region is formed on the epitaxial parts of the channel layer and the barrier layer;

   the epitaxial portions of the channel layer and the barrier layer are interrupted to form a cross section outside the doped isolation region.
2. The semiconductor device of claim 1, wherein the cross section is covered with a passivation material.
3. A semiconductor device according to claim 1 or 2, characterized in that the semiconductor device further comprises a second transistor which is co-layer with and arranged adjacent to the first transistor, the cross-section on the epitaxial part of the channel layer and barrier layer between the first and second transistors enclosing a recess.
4. A semiconductor device according to claim 3, wherein the recess is filled with a passivation material.
5. A semiconductor device according to any one of claims 1 to 4, wherein,

   the section is located at the outer edge of the doped isolation region.
6. A semiconductor device according to any one of claims 1 to 5, wherein,

   the cross section extends through the entire thickness of the epitaxial portions of the channel layer and barrier layer.
7. A semiconductor device according to any one of claims 1 to 6, wherein,

   the first transistor further includes:

   a source electrode, a drain electrode and a gate electrode connected with the surface of the barrier layer;

   the first surface passivation layer is arranged on one side of the source electrode, the drain electrode and the grid electrode, which is away from the substrate, and the first surface passivation layer covers the section.
8. A semiconductor device according to any one of claims 1 to 7, wherein,

   the first transistor further includes a buffer layer; the buffer layer is positioned on one side of the channel layer away from the barrier layer;

   the depth of the doped isolation region extends into the buffer layer.
9. A semiconductor device according to any one of claims 1 to 8, wherein,

   the channel layer adopts GaN;

   the barrier layer adopts at least one of AlGaN, alGaInN, alInN.
10. A method of fabricating a semiconductor device, comprising:

    sequentially forming a buffer layer, a channel film layer and a barrier film layer on a substrate;

    ion implantation is carried out on the periphery of the channel film layer and the periphery of the barrier film layer, which are positioned in the active region of the transistor, so that a doped isolation region is formed;

    and carrying out mesa etching on the channel film layer and the barrier film layer to form a section at a position which is kept close to the doping isolation region with at least partial width of the active region.
11. The method for manufacturing a semiconductor device according to claim 10, characterized in that the method for manufacturing a semiconductor device further comprises:

    forming a second surface passivation layer on the surface of the formed barrier film layer;

    forming a source electrode, a drain electrode and a grid electrode which are connected with the surface of the barrier film layer on the surface of the second surface passivation layer in the active region;

    and forming a first surface passivation layer on the surfaces of the source electrode, the drain electrode and the grid electrode, wherein the first surface passivation layer covers the section.
12. A terminal device, characterized in that the terminal device comprises a semiconductor device according to any of claims 1-9.