CN116632046A - Tunneling field effect transistor based on GaN-GaO-GaN polarization effect and preparation method thereof - Google Patents

Abstract

The invention relates to a tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect and a preparation method thereof; the problem that the existing tunneling field effect transistor is limited in tunneling area and small in on-state current is solved; the transistor comprises a substrate, a source region and Ga which are arranged in sequence ₂ O ₃ A layer, an intrinsic region, and a drain region; the left side and the right side of the intrinsic region are respectively provided with a gate oxide layer and a metal gate from inside to outside in sequence; a drain electrode is arranged above the drain region, and a source electrode is arranged below the source region; the source region and the intrinsic region are made of gallium nitride material, so that the source region and Ga ₂ O ₃ Between layers, ga ₂ O ₃ Layer and intrinsic regionForming a heterojunction between the two; the doping types of the source region, the intrinsic region and the drain region are opposite; a Ga is added between the source region and the intrinsic region ₂ O ₃ The layer makes the P-N junction narrower than the depletion region of the N-I junction, the electric field of the tunneling junction is larger, the energy band bending is steeper, the tunneling probability is increased, and the on-state current is obviously improved, so that better on-off current ratio and smaller subthreshold swing are obtained.

Description

Tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect and its preparation method

technical field

The invention relates to a tunneling field effect transistor and a preparation method thereof, in particular to a tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect and a preparation method thereof.

Background technique

The basic structure of the existing common tunneling field effect transistor is shown in Figure 1. The tunneling field effect transistor is a gate-controlled P-I-N transistor, also known as a lateral tunneling field effect transistor, including substrate 01, side by side from left to right The source region 02, the intrinsic region 03, and the drain region 04 arranged on the substrate 01, and the gate oxide layer 05 and the metal gate 06 arranged on the intrinsic region 03 in order from bottom to top, and a source electrode is arranged on the source region 02, A drain electrode is disposed on the drain region 04 .

The structure of an existing tunneling field effect transistor with a homojunction structure is shown in FIG. 2 , including a substrate 001, a source region 002, an intrinsic region 003, and a drain region 004 arranged sequentially from bottom to top. Below the source region 002, a The source electrode 008, the gate oxide layer 005 and the metal gate 006 are arranged sequentially from the inside to the outside on both sides of the intrinsic region 003, the drain electrode 007 is arranged above the drain region 004, and the source region 002 and the intrinsic region 003 are all made of gallium nitride preparation.

In the above-mentioned existing structure, the tunnel breakdown occurs at the interface between the source region and the intrinsic region, and the surface area controlled by the metal gate has a limited tunneling area, and the on-state current of the device is small, which becomes Therefore, how to overcome the problem of small on-state current has become the focus of research on tunneling field effect transistors.

Contents of the invention

The purpose of the present invention is to solve the problems of limited tunneling area and small on-state current in existing tunneling field effect transistors, and propose a tunneling field effect based on gallium nitride-gallium oxide-gallium nitride polarization effect Transistors and methods of making them.

Design idea of the present invention is:

Gallium oxide (Ga ₂ O ₃ ) is an emerging ultra-wide bandgap (UWBG) semiconductor with a large bandgap of 4.8eV. For comparison, the bandgap of SiC and GaN is 3.3eV, while that of silicon is only 1.1eV. If gallium oxide (Ga ₂ O ₃ ) has higher thermal stability and higher voltage, plus it can be The widely adopted natural substrate makes it possible to develop miniaturized and efficient high-power transistors based on this feature.

ε- _Ga2O3 has a larger spontaneous polarization (P _SP =0.31) than III-nitride semiconductors, and it is possible to obtain a higher concentration of two _- dimensional electron gas (2DEG) through heterojunctions without additional doping .

In the present invention, a single-crystal gallium nitride is used as a substrate, and a layer of P-type gallium nitride is epitaxially grown on it as a source region, and a layer of gallium oxide is grown on the source region as a "Pocket" layer. An N-type gallium nitride layer is grown on the gallium oxide layer as the intrinsic region, that is, GaN/Ga ₂ O ₃ /GaN, using the difference in lattice constant between the two materials of GaN/Ga ₂ O ₃ and the formed The polarization effect to promote the tunneling probability and increase the tunneling current.

For epitaxial growth, the lattice mismatch between the epitaxial layer and the substrate should be small to avoid defect formation due to strain relaxation. It can be seen from Table 1 that the lattice mismatch of ε-Ga ₂ O ₃ is large, and the c-plane GaN is not suitable for the growth of ε-Ga ₂ O ₃ ; ε-Ga ₂ O ₃ has a large P _SP of 0.31C along the z-axis /m ² , which is significantly larger than that of group III nitride semiconductors, and the piezoelectric constant value of ε-Ga ₂ O ₃ is comparable to that of GaN, which means that the ability of ε-Ga ₂ O ₃ to produce _PPE under epitaxial strain is comparable to that of GaN.

Table 1

Material e ₃₁ e ₃₂ e ₃₃ c ₃₁ c ₃₂ c ₃₃ P _SP ε-Ga ₂ O ₃ 0.21 0.34 -0.73 142.44 147.54 284.18 0.31 GaN -0.34 -0.34 0.67 100 100 392 -0.034

Based on above-mentioned design, the technical scheme that the present invention provides is:

A tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect, which is special in that:

Including a substrate, a source region, a Ga ₂ O ₃ layer, an intrinsic region and a drain region arranged sequentially from bottom to top;

The left and right sides of the intrinsic region are sequentially provided with a gate oxide layer and a metal gate from the inside to the outside;

A drain electrode is arranged above the drain region, and a source electrode is arranged below the source region;

Both the source region and the intrinsic region are made of gallium nitride material, so that a heterojunction is formed between the source region and the Ga ₂ O ₃ layer, and between the Ga ₂ O ₃ layer and the intrinsic region;

The doping types of the source region, the intrinsic region and the drain region are opposite.

Further, the source region is P-type doped, and the intrinsic region and drain region are N-type doped.

Further, the metal gate is made of Ni/Au, and the gate oxide layer is made of HfO ₂ .

Further, the length of the metal gate is 0.5-1 nm;

The length of the gate oxide layer is 0.5-1 nm;

The thickness of the source region is 10-20nm;

The thickness of the Ga ₂ O ₃ layer is 1.5-3.5 nm;

The thickness of the intrinsic region is 15-20nm;

The thickness of the drain region is 10-15nm;

The lengths of the source region, the Ga ₂ O ₃ layer, the intrinsic region and the drain region are 4-6 nm.

Further, the doping concentration of the source region is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 , the doping concentration of the drain region is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 ; the intrinsic region The doping concentration is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 .

Further, the work function of the metal gate is 4.515eV.

The present invention also proposes a method for preparing the tunneling field effect transistor based on the gallium nitride-gallium oxide-gallium nitride polarization effect, which is special in that it includes the following steps:

Step 1: Grow a gallium nitride source region, _{a Ga2O3} layer, a gallium nitride intrinsic region and a gallium nitride drain region sequentially from bottom to top on a semiconductor substrate to form a test piece;

Step 2: cleaning and drying the test piece obtained in step 1;

Step 3: Etching and evaporating the source and drain electrodes of the dried test piece respectively to obtain semi-finished devices;

Step 4: Isolate the semi-finished device;

Step 5: Deposit gate oxide layers on the left and right sides of the intrinsic region of the semi-finished device, and form metal gates on the surfaces of the two gate oxide layers by etching and evaporation;

Step 6: Protect and passivate the metal gate to complete the preparation of the tunneling field effect transistor based on the GaN-GaO-GaN polarization effect.

Beneficial effects of the present invention:

In the present invention, a Ga ₂ O ₃ layer ("source-pocket" region) is added between the source region and the intrinsic region, so that the depletion region of the PN junction is narrower than that of the NI junction, and the electric field of the tunnel junction Larger, the band bending is steeper, resulting in a decrease in the tunneling distance, an increase in the tunneling probability, and a significant increase in the on-state current, thereby obtaining a better on-off current ratio and a smaller sub-threshold swing.

Description of drawings

1 is a schematic diagram of the basic structure of an existing tunneling field effect transistor (the source electrode and the drain electrode are not shown);

The reference signs in Fig. 1 are as follows:

01. Substrate; 02. Source region; 03. Intrinsic region; 04. Drain region; 05. Gate oxide layer; 06. Metal gate;

Fig. 2 is a structural schematic diagram of an example of a tunneling field effect transistor with a conventional homojunction structure (the source electrode is arranged below the substrate);

The reference signs in Fig. 2 are as follows:

001, substrate; 002, source region; 003, intrinsic region; 004, drain region; 005, gate oxide layer; 006, metal gate; 007, drain electrode; 008, source electrode;

Fig. 3 is a structural schematic diagram of an embodiment of a tunneling field effect transistor based on the gallium nitride-gallium oxide-gallium nitride polarization effect of the present invention (the source electrode is arranged under the substrate);

The reference signs in Fig. 3 are as follows:

1. Substrate; 2. Source region; 3. Ga ₂ O ₃ layer; 4. Intrinsic region; 5. Drain region; 6. Metal gate; 7. Drain electrode; 8. Source electrode; 9. Gate oxide layer;

Fig. 4 is a diagram of the electric field distribution formed by gallium nitride and gallium oxide under piezoelectric polarization combined with their own spontaneous polarization, where A represents the electric field distribution of gallium oxide, and B represents the electric field distribution of gallium nitride.

Detailed ways

Define the length along the x-axis direction and the thickness along the y-axis direction.

The present invention proposes a tunneling field effect transistor based on gallium nitride-gallium oxide- _gallium nitride polarization effect, including a single crystal GaN substrate 1, a GaN source region 2, a _Ga2O3 layer 3, and a GaN intrinsic region 4. GaN drain region 5, metal gate 6, drain electrode 7, source electrode 8, gate oxide layer 9.

The configuration of each component is as follows:

The source region 2, the _Ga2O3 layer 3, the intrinsic region 4, and the drain region 5 are sequentially arranged on the _single crystal GaN substrate 1 from bottom to top, and the source electrode 8 and the drain electrode 7 are respectively arranged below the source region 2 and Above the drain region 5 , a gate oxide layer 9 and a metal gate 6 are sequentially arranged on the left and right sides of the intrinsic region 4 .

The source region 2 and the drain region 5 are doped with P and N types respectively, the doping concentration of the source region 2 is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 , and the doping concentration of the drain region 5 is 1×10 ¹⁹ - 5×10 ¹⁹ cm ^-3 , the doping concentration of the intrinsic region is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 .

Through the GaN source region 2, _{the Ga2O3} layer 3 and the GaN intrinsic region 4, _{a heterojunction is formed between the GaN source region 2 and the Ga2O3 layer 3, and the Ga2O3 layer 3 and} the GaN intrinsic region A heterojunction is formed between the regions 4, and the difference in lattice constant between the two materials and the formed polarization effect are used to promote the tunneling probability and increase the tunneling current; and make the P ⁺ N ⁺ junction Compared with the narrower depletion region of the N ⁺ I junction, the electric field of the tunneling junction is larger, and the energy band bending is steeper, resulting in a decrease in the tunneling distance, an increase in the tunneling probability, and a significant increase in the on-state current.

The metal gate 6 is made of Ni/Au, and the length of the metal gate 6 is 0.5-1 nm; the gate oxide layer 9 is made of HfO ₂ , and the length of the gate oxide layer 9 is 0.5-1 nm; the thickness of the source region 2 is 10-20 nm; Ga ₂ The thickness of O ₃ layer 3 is 1.5-3.5nm; the thickness of intrinsic region 4 is 15-20nm; the thickness of drain region 5 is 10-15nm, source region 2, Ga ₂ O ₃ layer 3, intrinsic region 4, drain region The length of 5 is 4-6nm, and the work function of metal gate 6 is 4.515eV.

As shown in Figure 4, it is the electric field distribution diagram formed by the piezoelectric polarization of gallium nitride and gallium oxide combined with their own spontaneous polarization. The abscissa is the thickness of the tunneling field effect transistor in μm, and the ordinate is the electric field strength in V/cm. There is a lattice difference between gallium nitride and gallium oxide, gallium oxide is subject to piezoelectric polarization, combined with its own spontaneous polarization, the two heterojunction interfaces generate electrically opposite polarized surface charges, resulting in a high-level built-in electric field , making the tunnel junction electric field stronger.

Based on the above structure, the present invention also proposes a method for preparing a tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect, by growing a P-type gallium nitride layer on the substrate 1 as the source region 2 , grow a 1.5-3.5nm Ga ₂ O ₃ layer 3 on the source region 2; grow an N-type gallium nitride intrinsic region 4 on the Ga ₂ O ₃ layer 3, around the N-type gallium nitride intrinsic region 4 Deposit a dielectric layer on both sides of the surface, and then use an etching process to etch the gate oxide layer 9 on the left and right sides of the N-type GaN intrinsic region 4; Deposit metal gold as the metal gate 6 to jointly form the metal gate electrode; use deposition and etching processes to generate metal electrodes on the sides of the source region 2 and the drain region 5, respectively, as the source electrode 8 and the drain electrode 7;

specific:

Step 1: grow a GaN source region 2 on a single-crystal GaN substrate 1 by molecular beam epitaxy (MBE), grow a _Ga2O3 layer 3 on _the GaN source region 2 by metal-organic chemical vapor deposition (MOCVD), and continue to GaN intrinsic region 4 and GaN drain region 5 are grown on the _Ga2O3 layer 3 by molecular beam epitaxy (MBE) to form a _test piece;

Step 2: Clean and dry the surface of the test piece in step 1

Put the grown test piece into the acetone solution for about 2 minutes for ultrasonic cleaning to remove organic residues on the surface of the sample, then cook in the positive glue stripping solution, and then perform ultrasonic cleaning on the test piece in acetone and ethanol in turn, Then use deionized water to wash away the remaining acetone and ethanol, and further wash with hydrofluoric acid solution to effectively remove the stains caused by carbon and hydrocarbons on the surface of the test piece. Finally, use deionized water to clean it again and blow it with pure nitrogen. Dry;

Step 3: Source and drain ohmic contacts

Etch the epitaxial layer outside the test piece after step 2 by dry etching, and use an electron beam evaporation machine to evaporate Au metal layer on the two areas of the gallium nitride source region 2 and the gallium nitride drain region 5 surface , placed in a rapid annealer after evaporation, so that the Au metal layer forms ohmic contact with the corresponding evaporated gallium nitride source region 2 and gallium nitride drain region 5, forming a source electrode 8 and a drain electrode 7, and obtaining a semi-finished device;

Step 4: Device Isolation

Apply inductively coupled plasma etching (ICP) to etch the semi-finished device that has completed step 3 with glue to realize the isolation of the semi-finished device, and then perform annealing treatment;

Step 5: Oxide dielectric layer and gate formation

Deposit the gate oxide layer 9 directly on the two surfaces of the gallium nitride layer in the intrinsic region 4 by dry etching, and anneal after deposition; use the over-etching method to etch the groove gate, and then evaporate the gate metal, using electron beams In the evaporation process, the evaporated metal structure is a Ni/Au alloy to form the metal grid 6 .

Step 6: Interconnection

Since the metal gate 6 needs to be protected and passivated after the metal gate 6 is deposited, the entire wafer is covered by the passivation layer, so before the electrode is drawn out, the passivation film above the position of the electrode is firstly etched for interconnection openings. After the etching of the opening is completed, the interconnection metal is evaporated, and the fabrication of the transistor is completed.

Claims (7)

1. A tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect, characterized in that: It includes a substrate (1), a source region (2), _{a Ga2O3 layer} (3), an intrinsic region (4) and a drain region (5) arranged sequentially from bottom to top; A gate oxide layer (9) and a metal gate (6) are sequentially arranged on the left and right sides of the intrinsic region (4) from inside to outside; A drain electrode (7) is arranged above the drain region (5), and a source electrode (8) is arranged below the source region (2); Both the source region (2) and the intrinsic region (4) are made of gallium nitride material, so that between the source region (2) and the Ga ₂ O ₃ layer (3), the Ga ₂ O ₃ layer (3) and the intrinsic A heterojunction is formed between the regions (4); The doping types of the source region (2), the intrinsic region (4), and the drain region (5) are opposite. 2. The Tunneling Field Effect Transistor based on GaN-GaO-GaN polarization effect according to claim 1, characterized in that: the source region (2) is P-type doped, and the The levy region (4) and the drain region (5) are N-type doped. 3. The tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect according to claim 2, characterized in that: The metal grid (6) is made of Ni/Au, and the gate oxide layer (9) is made of _HfO2 . 4. The gallium nitride-gallium oxide-gallium nitride polarization effect-based tunneling field effect transistor according to any one of claims 1-3, characterized in that: The length of the metal grid (6) is 0.5-1nm; The gate oxide layer (9) has a length of 0.5-1 nm; The thickness of the source region (2) is 10-20nm; The thickness of the Ga ₂ O ₃ layer (3) is 1.5-3.5 nm; The thickness of the intrinsic region (4) is 15-20nm; The thickness of the drain region (5) is 10-15nm; The length of the source region (2), _Ga2O3 layer (3), intrinsic region (4 ₎ and drain region (5) is 4-6nm. 5. The tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect according to claim 4, characterized in that: The doping concentration of the source region (2) is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 , and the doping concentration of the drain region (5) is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 ; the The doping concentration of the intrinsic region (4) is 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 . 6. The tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect according to claim 5, characterized in that: The work function of the metal grid (6) is 4.515eV. 7. A method for preparing a tunneling field effect transistor based on gallium nitride-gallium oxide-gallium nitride polarization effect according to any one of claims 1-6, characterized in that it comprises the following steps: Step 1: growing GaN source region (2), Ga ₂ O ₃ layer (3), GaN intrinsic region (4) and GaN drain region ( 5), forming a test piece; Step 2: cleaning and drying the test piece obtained in step 1; Step 3: Etching and evaporating the source electrode (8) and drain electrode (7) on the dried test piece source region (2) and drain region (5) respectively to obtain a semi-finished device; Step 4: Isolate the semi-finished device; Step 5: Deposit gate oxide layers (9) on the left and right sides of the intrinsic region (4) of the semi-finished device, and form metal gates (6) on the surfaces of the two gate oxide layers (9) by etching and evaporating. ); Step 6: Protect and passivate the metal gate (6), and complete the preparation of the tunneling field effect transistor based on the polarization effect of gallium nitride-gallium oxide-gallium nitride.