CN116631472B

CN116631472B - Semiconductor device, method for manufacturing the same, and method for optimizing parameters

Info

Publication number: CN116631472B
Application number: CN202310880691.8A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2023-07-18
Filing date: 2023-07-18
Publication date: 2023-10-20
Anticipated expiration: 2043-07-18
Also published as: CN116631472A

Abstract

The present disclosure relates to a semiconductor device, a method of manufacturing the same, and a parameter optimization method. The semiconductor device includes a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell comprising: a first inverter and a second inverter, the inputs and outputs of which are cross-coupled to form a first storage node and a second storage node for storing data and a first pair of transmission transistors and a second pair of transmission transistors. The first transfer transistor includes a first halo region on a first storage node side and a second halo region on a bit line side of the first storage node in a first bit line pair, an impurity implantation concentration of the first halo region being smaller than an impurity implantation concentration of the second halo region, and the fourth transfer transistor includes a third halo region on the second storage node side and a fourth halo region on a bit line side of the second storage node in the second bit line pair, an impurity implantation concentration of the third halo region being smaller than an impurity implantation concentration of the fourth halo region.

Description

Semiconductor device, method for manufacturing the same, and method for optimizing parameters

Technical Field

Embodiments of the present disclosure relate generally to the field of semiconductor devices, and more particularly, to semiconductor devices including dual port static random access memories, methods of manufacturing the same, and methods of optimizing parameters.

Background

Static Random Access Memory (SRAM) plays an important role in caches such as portable mobile electronic devices and system on a chip (SOC) due to the characteristics of fast read-write speed, stable operation and the like. With the rise of 5G, artificial intelligence, etc., intelligent chips face more complex computational load, which requires increasing the access speed of SRAM to obtain higher-speed caches.

In some areas, high bandwidth and high throughput dual port SRAM (DP-SRAM) is commonly employed for the buffering process. Due to chip area limitations, in conventional DP-SRAM layout designs, there are situations where the same word line controlled transistor pair is interconnected using different electrical connection materials in the circuit. This layout design can lead to asymmetry in the current path through the transistor, which in turn can degrade the performance of the SRAM. The symmetry of the current path can be improved by optimizing the electrical connection material through the high-k metal gate process. However, such schemes have limited effectiveness and require optimization of different interfaces for transistors of different conductivity types, which results in a manufacturing process and complexity thereof.

Disclosure of Invention

In view of the above, embodiments of the present disclosure aim to provide a solution to improve the performance of dual port static random access memories.

According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell comprising: a first inverter and a second inverter whose inputs and outputs are cross-coupled to form a first storage node and a second storage node for storing data, the first storage node storing a state opposite to a state stored by the second storage node; a first pair of transfer transistors including a first transfer transistor and a second transfer transistor and configured to couple the first bit line to the first storage node and the second storage node, respectively, for reading and writing data; a second pair of transfer transistors including a third transfer transistor and a fourth transfer transistor and configured to couple the second bit line to the first storage node and the second storage node, respectively, for reading and writing data. The first transfer transistor includes a first halo region on a first storage node side and a second halo region on a bit line side of the first storage node in a first bit line pair, an impurity implantation concentration of the first halo region being smaller than an impurity implantation concentration of the second halo region, and the fourth transfer transistor includes a third halo region on the second storage node side and a fourth halo region on a bit line side of the second storage node in the second bit line pair, an impurity implantation concentration of the third halo region being smaller than an impurity implantation concentration of the fourth halo region.

In some embodiments, the second transfer transistor includes a fifth halo region on the second storage node side, and a sixth halo region in the first bit line pair corresponding to the bit line side of the second storage node, an impurity implantation concentration of the fifth halo region being equal to an impurity implantation concentration of the sixth halo region.

In some embodiments, the third transfer transistor includes a seventh halo region on the first storage node side, and an eighth halo region in the second bit line pair corresponding to the bit line side of the first storage node, an impurity implantation concentration of the seventh halo region being equal to an impurity implantation concentration of the eighth halo region.

In some embodiments, the impurity implantation concentrations of the second halo region, the fourth halo region, the fifth halo region, the sixth halo region, the seventh halo region, and the eighth halo region are equal to each other.

In some embodiments, the impurity implantation concentration of the first halo region is equal to the impurity implantation concentration of the third halo region.

In some embodiments, the first through fourth pass transistors each include a lightly doped extension region having the first conductivity type.

In some embodiments, the first through eighth halo regions are formed below respective lightly doped extension regions of respective pass transistors, respectively, and have a second conductivity type opposite the first conductivity type.

According to a second aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The semiconductor device includes a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell including a first bit line pair and a second bit line pair, a cross-coupled inverter pair having a first storage node and a second storage node for storing data, and first and second pair of transmission transistors selectively coupling the cross-coupled inverter pair to the first and second bit line pairs, respectively. The method comprises the following steps: forming a first element forming region and a second element forming region in a semiconductor substrate, a plurality of first element NMOS having a first conductivity type N being formed in the first element forming region and a plurality of second element PMOS having a second conductivity type P being formed in the second element forming region, the plurality of first elements and the plurality of second elements constituting a DP-SRAM cell, the plurality of first elements including a first pair of transfer transistors and a second pair of transfer transistors; implanting impurity ions of the first conductivity type at corresponding positions in the first element forming regions by using the first mask to form a plurality of lightly doped extension regions of the first element having the first conductivity type; and implanting impurity ions of a second conductivity type under the lightly doped extension region of the first conductivity type using the first mask and the second mask to form a halo region of the second conductivity type such that an implantation concentration of a halo region of a transfer transistor of the first pair of transfer transistors on a side near the bit line is smaller than an implantation concentration of a halo region of the transfer transistor on a side near the first storage node, and such that an implantation concentration of a halo region of a transfer transistor of the second pair of transfer transistors on a side near the bit line is smaller than an implantation concentration of a halo region of the transfer transistor on a side near the second storage node.

In some embodiments, the method further comprises: the implantation concentrations of the halo region on the bit line side and the halo region on the second storage node side of the transfer transistors corresponding to the second storage node in the first pair of transfer transistors are formed to be equal to each other.

In some embodiments, the method further comprises: the implantation concentrations of the halo region on the bit line side and the halo region on the second storage node side of the transfer transistors corresponding to the first storage node in the second pair of transfer transistors are formed to be equal to each other.

In a third aspect of the present disclosure, a method for optimizing parameters of a semiconductor device is provided. The semiconductor device includes a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell including a bit line pair, a cross-coupled inverter pair having a storage node for storing data, and a pass transistor pair selectively coupling the cross-coupled inverter pair to the bit line pair. The method comprises the following steps: forming a first element forming region and a second element forming region in a semiconductor substrate, a plurality of first elements having a first conductivity type being formed in the first element forming region and a plurality of second elements having a second conductivity type being formed in the second element forming region, the plurality of first elements and the plurality of second elements constituting a DP-SRAM cell, the plurality of first elements including a pair of pass transistors; implanting impurity ions of the first conductivity type at corresponding positions in the first element forming regions by using the first mask to form a plurality of lightly doped extension regions of the first element having the first conductivity type; implanting impurity ions of a second conductivity type under the lightly doped extension region of the first conductivity type using the first mask and the second mask to form a halo region of the second conductivity type such that the halo region of one of the pair of transfer transistors on a bit line side has a first implantation concentration and the halo region of the transfer transistor on a storage node side has a second implantation concentration greater than the first implantation concentration; measuring a threshold voltage of each pass transistor in a pair of pass transistors at different current directions to obtain a threshold voltage difference indicative of asymmetry of the pass transistors; and minimizing a difference between the threshold voltage differences of each pass transistor in the pair of pass transistors by adjusting the first implant concentration and the second implant concentration.

In some embodiments, measuring the threshold voltage comprises: the current-voltage IV characteristics of each pass transistor in the pass transistor pair at different current directions are measured.

In some embodiments, the method further comprises: the halo region of the other transfer transistor of the pair on the side close to the bit line is formed to have an implantation concentration equal to that of the halo region of the transfer transistor on the side close to the storage node.

In some embodiments, wherein the parameters include one or more of Static Noise Margin (SNM), write Margin (WM), roll-over voltage, and power consumption.

According to the embodiment of the disclosure, the asymmetry of the device caused by the DP-SRAM layout design can be balanced under the condition that the overall layout design is not changed, and the parameter performance of the device is improved at the same time so as to further expand the yield window. On the other hand, modification of the layout is avoided in the flow sheet process, so that the optimization period can be shortened in the optimization parameter flow, and instant process adjustment is realized.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 shows a circuit diagram of a DP-SRAM cell under ideal conditions;

FIG. 2 illustrates a layout design for the DP-SRAM cell shown in FIG. 1;

FIG. 3 shows a circuit diagram of a DP-SRAM cell under actual processing;

fig. 4A shows a simplified process flow for a semiconductor device;

FIG. 4B shows the region corresponding to the light doping process in the layout of the DP-SRAM cell;

FIG. 5 illustrates a layout design of a DP-SRAM cell showing regions corresponding to improved lightly doped processes in accordance with an embodiment of the present disclosure;

FIG. 6 illustrates a method flow diagram for fabricating a DP-SRAM cell in accordance with an embodiment of the present disclosure;

fig. 7A illustrates a schematic structure of a pass transistor with an asymmetric halo region in accordance with an embodiment of the present disclosure;

fig. 7B shows a source drain current versus gate voltage plot for a device having an asymmetric halo region in accordance with an embodiment of the present disclosure;

FIGS. 8A and 8B illustrate performance simulation results of a DP-SRAM cell in accordance with an embodiment of the present disclosure;

FIG. 9 illustrates a layout design of a test structure for performance parameter optimization in accordance with an embodiment of the present disclosure;

FIG. 10 illustrates a method flow diagram for performance parameter optimization in accordance with an embodiment of the present disclosure;

FIG. 11A illustrates a conventional optimization flow chart for parameter optimization of a semiconductor device;

fig. 11B illustrates an optimization flow diagram for parameter optimization of a semiconductor device in accordance with an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Directional terms (such as "top", "bottom", "above", "below", "front", "rear", "head", "tail", "over", "under", etc.) may be used with reference to the described figures and/or directions of elements. Because embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. In some instances, directional terms may be exchanged with equivalent directional terms based on the orientation of the embodiments, so long as the general directional relationship between the elements and their general purpose are maintained.

In this disclosure, expressions (such as "first", "second", etc.) including sequence numbers may modify various elements. However, these elements are not limited to the above expression. For example, the foregoing does not limit the order and/or importance of the elements. The above description is only intended to distinguish one element from another element.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar fashion (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.).

In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intermediate elements) may also be implemented by indirect connection or coupling (i.e., connection or coupling with one or more additional intermediate elements), and vice versa, so long as the general purpose of the connection or coupling is substantially maintained.

As described above, in conventional DP-SRAM layout designs, there are cases where transistor pairs of the same port are interconnected using different electrical connection materials in the circuit. This layout design can lead to asymmetry in the current path through the transistor, which in turn can degrade the performance of the SRAM.

Before describing the layout design of a DP-SRAM, a circuit diagram of a DP-SRAM cell under ideal conditions will be described with reference to FIG. 1. DP-SRAM cells typically employ 8-transistor dual port storage, with read and write operations completed in one cycle in a time-sharing manner.

As shown in fig. 1, the DP-SRAM cell 100 includes transistors M1 to M4 constituting a first inverter 101 and a second inverter 102, a first pair of transmission transistors PGA, pga_b, and a second pair of transmission transistors PGB, pgb_b. The inputs and outputs of the first inverter 101 and the second inverter 102 are cross-coupled to form the body structure 100 of the DP-DRAM cell, i.e. the output of the first inverter 101 is coupled to the input of the second inverter 102 and the input of the first inverter 101 is coupled to the output of the second inverter 102. This enables the locking and saving of the output states of the first inverter 101 and the second inverter 102, which together constitute 1 bit of stored data. The cross-coupled first inverter 101 and second inverter 102 have a first storage node NL and a second storage node NR, respectively, for storing their output states. The state stored by the first storage node NL is opposite to the state stored by the second storage node NR.

The first inverter 101 and the second inverter are formed by connecting one PMOS transistor and one NMOS transistor in series, respectively. The drains of the NMOS transistors are electrically connected to a common ground terminal VSS, and the sources of the PMOS transistors are electrically connected to a common power terminal VDD.

The first pair of transmission transistors PGA, pga_b are coupled to the first storage node NL and the second storage node NR, respectively, for controlling the turning on and off of the body structure 100 storing data to the first bit line pair bl_a and blb_a for reading and writing. Likewise, a second pair of transfer transistors PGB, pgb_b are coupled to the first storage node NL and the second storage node NR, respectively, for controlling the turning on and off of the body structure 100 for storing data to the second bit line pair bl_a and blb_a for reading and writing. Two pairs of transmission transistors and two pairs of bit lines may provide two paths to the body structure 100 to perform read and write operations of the DP-SRAM.

The DP-SRAM cell also includes a pair of word lines WL_A and WL_B for selecting the corresponding pair of pass transistors to be on or off, respectively. When the word line wl_a or wl_b is at a high potential, the corresponding pass transistor pair is on, and then the triggered body structure is read or written through the corresponding bit line pair. When either word line wl_a or wl_b is at a low potential, the corresponding pass transistor is off, isolating the body structure from the bit line pair, such that data is stored in the body structure.

FIG. 2 shows a layout design for the DP-SRAM cell shown in FIG. 1. The thick dashed area in fig. 2 corresponds to the circuitry of the DP-SRAM cell of fig. 1. In layout design, SRAM cells are also referred to as SRAM bits. Specifically, the main body structure 200 of the DP-SRAM shown in fig. 1 is centrally located within a thin dashed area of the layout, including PMOS transistors located in the N-type well area 201 and NMOS transistors located in the active area 202, and the power supply terminal VDD, the ground terminal VSS, and the first and second storage nodes NL and NR as shown in the figure.

Referring to fig. 2, word lines WLA and WLB are connected to gates of first and second pass transistor pairs PGA, pga_b and pgb_b, respectively, through electrical contacts 203 and are controlled to be on or off. The first bit line pair BL_A and BLB_A are electrically connected to the sources of the first pass transistor pair PGA, PGA_B, respectively, for reading and writing operations to the body structure 200.

Similarly, the second bit line pair BL_A and BLB_A are electrically connected to the sources of the second pair of transmission transistors PGB, PGB_B, respectively, for reading and writing operations to the body structure 200. The first bit line pair BL_A and BLB_A and the second bit line pair BL_A and BLB_A can simultaneously perform read and/or write operations on the main structure via different transmission transistor pairs, thereby greatly improving the access speed of the SRAM.

In fig. 2, reference is made to the uppermost pass transistor pga_b, the source terminal of which is connected to the bit line blb_a, the drain terminal being connected via an electrical contact 204 to the gates of the PMOS and NMOS transistors in the first inverter 101 and in turn to the second storage node NR. With reference to pass transistor PGA, its source terminal is connected to bit line bl_a, its drain terminal is connected directly to first storage node NL via electrical contact 205, and then to the gates of the PMOS and NMOS transistors in second inverter 102 via a portion of electrical contact 204.

In some embodiments, electrical contacts 203-204 may be made of polysilicon material and electrical contact 205 may be formed of a metal wire. In another embodiment, the electrical contacts 203-204 may also be made of a metallic material. In some cases, the metallic material may be Tungsten (tunesten), titanium (Titanium), cobalt (Cobalt), nickel (Nickel), or an alloy with polysilicon. It should be understood that the electrical contacts 203-204 as gates may be made of other conductive materials and the disclosure is not limited herein.

For the first pass transistor pair PGA, pga_b, the current path of pass transistor pga_b passes through electrical contact 204, which is entirely made of polysilicon material, while the current path of pass transistor PGA passes partially through the metal line and partially through the polysilicon material. Since the contact resistance of polysilicon is larger than that of the metal line, this results in an asymmetric current path of the first pass transistor pair PGA, pga_b. In this case, such layout design may lead to performance degradation of the DP-SRAM device. The asymmetry of the DP-SRAM device caused by a defect in the layout design is described below with reference to fig. 3 using an equivalent circuit diagram.

Fig. 3 shows a circuit diagram of a DP-SRAM cell under actual process. As described above, since the contact circuit of the polysilicon is larger than the metal line, it is equivalent to connecting an additional resistor 301 in series in the current path of the pass transistor PGA in the first pass transistor pair. Likewise, an additional resistor 302 is also connected in series in the current path of pass transistor pgb_b in the second pass transistor pair.

Specifically, for the transfer transistor pgb_b to which the resistor 302 is connected in series, the source drain current-gate voltage IV characteristic (Ids-Vg characteristic) of the reverse current direction (flowing from the bit line terminal to the storage node terminal) and the forward current direction (flowing from the storage node terminal to the bit line terminal) are not uniform. In some embodiments, the IV characteristic inconsistency manifests as a difference in threshold voltages in the forward current direction and the reverse current direction, i.e., a difference in threshold voltages. The introduction of resistors 301-302 results in an asymmetric current path for the pass transistor controlled by the same word line in a conventional DP-DRAM layout, which results in degradation of the DP-SRAM device and loss of cell performance.

For such degradation of cell performance, conventionally employed processing methods are, for example, resizing the pga_b device of the independent active region, increasing the pga_b/pgb_b device width, and the like. However, this method is limited by process window and design rules, cannot be adjusted without limitation, and is also limited by the sensitivity responsivity of device performance to size. The way in which conventional approaches improve is therefore very limited. And under different process conditions, the asymmetry condition is not used as a qualitative standard.

According to the embodiment of the disclosure, a method for manufacturing a semiconductor device comprising a DP-SRAM unit is provided, performance degradation caused by device asymmetry caused by layout design is improved, and an optimization period can be shortened in an optimization parameter flow, so that instant process adjustment is realized. Various embodiments of the disclosure are described in detail below with reference to the accompanying drawings. It should be understood that this is for illustrative purposes only and is not intended to limit the scope of the present invention in any way.

Fig. 4A shows a brief process flow for a semiconductor device, and fig. 4B shows a region corresponding to a light doping process in the layout of a DP-SRAM cell. As shown by the rectangular box in fig. 4A, the lightly doped process (LDD Loop) is another ion implantation process subsequent to the source drain doping (S/D Loop). In the LDD doping process, the layout of the DP-SRAM cell shown in fig. 4B is divided into an implantation region NLDD of N-type impurity ions and an implantation region PLDD of P-type impurity ions. The LDD doping process is described later in detail with reference to fig. 5.

FIG. 5 illustrates a layout design of a DP-SRAM cell in accordance with an embodiment of the present disclosure. A method of fabricating a DP-SRAM cell according to an embodiment of the present disclosure is described with reference to fig. 6. FIG. 6 illustrates a flow chart of a method of fabricating a DP-SRAM cell in accordance with an embodiment of the present disclosure.

In block 602, referring to fig. 5, a first element forming region 501 and a second element forming region 502, i.e., a PLDD region and an NLDD region (as shown in fig. 4) to which a light doping process is subsequently performed, are formed in a semiconductor substrate (not shown). A plurality of PMOS transistors having a P-type conductivity are formed in the first element forming region 501, and a plurality of NMOS transistors having an N-type conductivity are formed in the second element forming region 502, the plurality of NMOS transistors and the plurality of second element PMOS transistors constituting a DP-SRAM cell.

At block 604, P-type impurity ions are implanted at corresponding locations in the first element forming region 501 using a first mask to form P-type lightly doped extension regions of the PMOS transistor.

At block 606, N-type impurity ions are implanted into corresponding locations in the second element forming region 502 using a second mask to form N-type lightly doped extension regions of the NMOS transistor. In some embodiments, the first mask is formed by overlaying photoresist at the locations of the NLDD regions and the second mask is formed by overlaying photoresist at the locations of the PLDD regions. It should be understood that embodiments of the present disclosure may also take other mask forms, which the present disclosure is not limited to.

In block 608, impurity ions of P-type conductivity are implanted under the lightly doped extension region of N-type conductivity in the second element forming region 502 using the second mask and the third mask to form a halo region of P-type conductivity. As shown in fig. 5, a position covered photoresist shown in a small dotted line box in the NLDD region serves as a third Mask to implant P-type impurity ions to positions not covered by the third Mask. The position of the third Mask corresponds to the contact ends of bl_a and bl_b in the circuit diagram. In other words, for the transfer transistors PGA and PGB, the ion implantation concentration of the halo region on one side of the bit line contact is smaller than that of the halo region on the other side. The formation of halo regions is described in detail below with respect to fig. 7A.

Fig. 7A shows a schematic structure of a pass transistor 700 with asymmetric halo regions in accordance with an embodiment of the present disclosure. The pass transistor 700 includes a source 701, a drain 702, a gate 703 formed in the active region between the source 701 and the drain 702, and isolation structures 708, 709. Isolation structures 708, 709 are shallow trench isolation structures STI formed on opposite sides of the source 701 and drain 702, respectively, to electrically isolate device structures formed in the active region from each other.

The source 701 and the drain 702 have the same conductivity type, for example, n+ type. Lightly doped extension regions 704, 705 are formed at the junction of the source 701, drain 702 and channel (not shown) for reducing peak electric fields near the source drain as described above in block 606. Lightly doped extension regions 704, 705 have the same conductivity type, e.g., n-type. It should be appreciated that the ion implantation concentrations of the source drain region and the lightly doped extension region are different for different processes, different process nodes. The present disclosure is not limited in this regard.

By means of a third Mask shown in fig. 5, halo regions 706, 707 with different ion implantation concentrations are formed below the lightly doped extension regions 704, 705. Halo region 706 has a lesser ion implantation concentration than halo region 707. In other words, the injection concentration of the halo region of the transfer transistor 700 on the side close to the bit line is smaller than the injection concentration of the halo region of the transfer transistor on the side close to the storage node. In some embodiments, the difference between the implantation concentration of the halo region near the bit line side and the implantation concentration of the halo region near the storage node side may be 1×10 ¹² cm ^-3 Up to 5X 10 ¹³ cm ^-3 Within a range between. It should be appreciated that the difference in implantation concentration of halo regions is dependent on the process and recipe The nodes, and the disclosure is not limited in this regard.

For the transfer transistor 700, when the ion implantation concentrations of the halo region thereof are different on the bit line side and the storage node side, the IV characteristic (Ids-Vg characteristic) in the forward and reverse current directions of the transfer transistor 700 also has a significant difference, as shown in fig. 7B. Referring to fig. 7A, the current flowing from the storage node side to the bit line side is a forward current, and the current flowing from the bit line side to the storage node side is a reverse current. As can be seen from fig. 7B, the threshold voltage of pass transistor 700 is less for the forward current direction than for the reverse current direction.

Referring to fig. 2, in this case, the transmission transistor PGA formed to have an asymmetric halo region has substantially the same IV characteristics as the transmission transistor pga_b. In some embodiments, substantially the same IV characteristic means that the difference between the threshold voltage difference of the pass transistor PGA in the forward and reverse current directions and the threshold voltage difference of the pass transistor pga_b is minimal. In some embodiments, the difference is in a range between 5% and 20%. In another embodiment, the difference may be other values, which the present disclosure does not limit. It should be appreciated that other electrical parameters besides threshold voltage may be employed to indicate asymmetry of the pass transistor.

As described above, in the device operation, the current paths of the first pass transistor pair PGA, pga_b become symmetrical. Likewise, the transfer transistor PGB formed to have an asymmetric halo region has substantially the same IV characteristics as the transfer transistor pgb_b. This causes the current paths of the second pass transistor pair PGB, pgb_b to become symmetrical during device operation. Performance enhancement of the DP-SRAM according to the embodiment of the present disclosure will be described below with reference to fig. 8.

Fig. 8A and 8B illustrate performance simulation results of a DP-SRAM cell according to an embodiment of the present disclosure. Before describing the performance parameters of the DP-SRAM cell in detail, the read and write operations of the SRAM device will be described. The read and write operations are described below with one port in DP-SRAM (e.g., via one bit line pair) as an example. Referring to fig. 1, the sram read operation reads a signal according to a voltage signal difference of the bit line pair bl_a and blb_a. It is assumed that the SRAM cell stores data "0", i.e. the first storage node NL stores a state of low potential and the second storage node NR stores a state of high potential.

BL_A and BLB_A are precharged at the time of reading, so that BL_A and BLB_A are both set to high, and word line WL_A is set to high. Under such conditions, as shown in the following diagram, the first storage node NL is at a low potential, the second storage node NR is at a high potential, the transistor M1 is turned off, M2 is turned on, M3 is turned on, and M4 is turned off. The right blb_a will remain high, but after M2 is turned on, current will flow from bl_a to VSS at low, resulting in a drop in the potential of bl_a. At the beginning, BL_A and BLB_A are both at high potential, after BL_A potential is reduced, BL_A and BLB_A will have voltage difference, and the signal is amplified by an amplifying circuit and then output. At this time, the memory data reading of the SRAM is completed.

The write operation is to invert the potentials of the first storage node NL and the second storage node NR in the SRAM, so as to achieve the purpose of writing. Still assuming that the SRAM cell stores data "0", i.e. the first storage node NL stores a state of low potential and the second storage node NR stores a state of high potential.

BL_A and BLB_A are precharged at the time of writing, with BL_A set high and BLB_A set low, and word line WL_A set high. Since blb_a is low, the potential of the second storage node NR gradually drops, which in turn causes the transistor M1 to turn on and M2 to turn off, so that the potential of the first storage node is pulled up to 1 by VDD. At this time, the transistor M3 is turned off, the transistor M4 is turned on, and the potential of the second storage node NR is pulled down to VSS. To this end, the data "1" writing is completed.

One important performance indicator for DP-SRAM cells is Static Noise Margin (SNM). SNM is an important parameter that measures the stability of a memory cell and refers to the maximum noise that an SRAM cell can tolerate before the state of the storage node is flipped. When static noise margin testing is performed, the word line pair and bit line pair are both set to low levels. A noise source is connected between the first inverter 101 and the second inverter 102 to simulate the actual noise voltage that can flip the storage state.

The first storage Node NL is placed at a low potential and the second storage Node NR is placed at a high potential, then the input of the second inverter 102 is noisy with circuit emulation software while the voltages of the storage nodes NL and NR (e.g., node_l and node_r in fig. 8A) are measured for changes. In some embodiments, the analog noise disturbance may utilize a voltage source to begin a voltage sweep from 0 at the input of inverter 102. The present disclosure is not limited to the analog form of noise.

When the voltage source scans to a certain voltage value, the potential of the first storage node NL is inverted and becomes a high voltage. Likewise, the above procedure may be reversed, e.g. with the first storage node NL being placed high and the second storage node NR being placed low, scanning from 0 with the voltage source, perturbing the input of the second inverter 102. When the voltage source scans to a certain voltage value, the potential of the first storage node NL is inverted and changed to a low voltage. Thus, a curve as shown in fig. 8A can be plotted.

In FIG. 8A, curve 801 is the SNM simulation curve of a DP-SRAM cell under actual process. It will be appreciated that the specific value of the switching voltage of the transistors in the inverter, whether simulated or actually measured, is determined after the transistor size is determined. Ideally, the more stable the SRAM cell will be when the noise margin is greater than the flip voltage of the transistors in the inverter during noise disturbance. In fig. 8A, the inscribed square of the two closed figures enclosed by the curve 801 can be used as an index for evaluating the static noise margin. The side length of the square is the SNM noise tolerance value, and the larger the square is, the larger the noise tolerance of the SRAM unit is, and the better the stability of the SRAM unit is.

Curve 802 is an SNM simulated curve for a DP-SRAM cell according to an embodiment of the present disclosure. As can be seen in fig. 8A, the square enclosed by curve 802 is larger than curve 801. This shows that when the impurity ion implantation concentration of the transfer transistor PGA/PGB in the halo region near the bit line side is set smaller than that in the halo region near the storage node side, the static noise margin of the SRAM can be increased, thereby overcoming the problem of asymmetry due to layout design.

FIG. 8B shows another important performance parameter Write Margin (WM) for an SRAM cell. With continued reference to fig. 1, as described above, if the data stored before writing "1" is "0", bl_a (as in BL in fig. 8B) is set to a high potential, and at this time, bit line bl_a charges first storage Node NL, so that the voltage at Node NL (as in Node in fig. 8B) gradually rises. If the voltage of the first storage node NL is lower than the flip voltage of the inverter before the word line is turned off, the data "1" write fails. In this way, to improve the writing stability, the voltage after the first storage node NL is charged is much greater than the switching voltage of the transistor of the inverter before the word line is turned off. This voltage difference is the write margin.

It can be seen that the relation between the performance parameters SNM and WM of SRAM is balanced. The SNM has a strong correlation with the threshold voltage of the transfer transistor, and by increasing the ion implantation concentration of the halo region on the storage node side of the transfer transistor, the higher the threshold voltage of the transfer transistor, the higher the SNM. There is also a gain to WM when the saturation current Idsat of the pass transistor is effectively increased. Both SNM and WM are not available because the threshold voltage and saturation current would result in both SNM and WM being balanced without changing device performance.

However, as can be seen from FIGS. 8A and 8B, both SNM and WM have significant performance improvements. By means of ion implantation, the original SNM curve 801 is optimized to the result shown by the curve 802, the original asymmetric butterfly curve (butterfly curve) is optimized to be symmetric, and the SNM value is higher. While increasing SNM, WM does not degrade with increasing SNM, curve 803 shown in fig. 8B shifts to the left as compared to curve 804, i.e., WM is also improved correspondingly while SNM is optimally increased.

As described above, by adjusting ion implantation concentrations of the halo region on the bit line side and the halo region on the storage node side of the corresponding transfer transistor, cell asymmetry is optimized, while improving static noise margin and write margin, further expanding the yield window.

FIG. 9 illustrates a layout design of a test structure for performance parameter optimization in accordance with an embodiment of the present disclosure.

In fig. 9, two pins Pin 901, 902, pin1 903 and Pin2 904 are shown. Referring to the DP-SRAM layout of fig. 2, pin 901 and pin 902 correspond to the contact terminals of word line wl_a and bit line blb_a, respectively, pin 903 corresponds to the source location of pga_b, and pin 904 corresponds to the second storage node NR. The parameter optimization flow using the test structure of fig. 9 is described below with reference to fig. 10.

FIG. 10 illustrates a method flow diagram for performance parameter optimization in accordance with an embodiment of the present disclosure.

At block 1002, first element formation region 501 and second element formation region 502, i.e., a PLDD region and an NLDD region (as shown in fig. 4) that are subsequently subjected to a light doping process, are formed in a semiconductor substrate (not shown). A plurality of PMOS transistors having a P-type conductivity are formed in the first element forming region 501, and a plurality of NMOS transistors having an N-type conductivity are formed in the second element forming region 502, the plurality of NMOS transistors and the plurality of second element PMOS transistors constituting a DP-SRAM cell.

At block 1004, P-type impurity ions are implanted at corresponding locations in the first element forming region 501 using a first mask to form P-type lightly doped extension regions of the PMOS transistor.

At block 1006, N-type impurity ions are implanted into corresponding locations in the second element forming region 502 using a second mask to form N-type lightly doped extension regions of the NMOS transistor. In some embodiments, the first mask is formed by overlaying photoresist at the locations of the NLDD regions and the second mask is formed by overlaying photoresist at the locations of the PLDD regions. It should be understood that embodiments of the present disclosure may also take other mask forms, which the present disclosure is not limited to.

In block 1008, impurity ions of P-type conductivity type are implanted under the lightly doped extension region of N-type conductivity type in the second element forming region 502 using the second mask and the third mask to form a halo region having a first implantation concentration and a halo region having a second implantation concentration. Referring to fig. 2, for the transfer transistors PGA and PGB, the halo region on the bit line contact side thereof has a first implantation concentration, the halo region on the storage node side thereof has a second implantation concentration, and the first implantation concentration is smaller than the second implantation concentration.

In block 1010, the current-voltage IV characteristics of both pass transistors in a pass transistor pair are measured. Referring to FIG. 9, first, test port selection is identified as pins 901, 902 and 903 for IV testing; second, test port selection is identified as pins 901, 902 and pin 904 for IV testing. Thus, the performance difference of the transmission transistor PGA_B caused by the layout design can be tested. In some embodiments, the IV characteristics of the pass transistor PGA with asymmetric halo regions formed in block 1008 are measured by introducing additional test ports.

In block 1012, the IV characteristics of the two pass transistors of the pass transistor pair are made substantially the same by adjusting the first implant concentration and the second implant concentration. In some embodiments, substantially the same IV characteristic means that the difference between the threshold voltage difference of the pass transistor PGA in the forward and reverse current directions and the threshold voltage difference of the pass transistor pga_b is minimal. As described with respect to fig. 7, this difference is in the range between 5% and 20%. In another embodiment, the difference may be other values, which the present disclosure does not limit.

As shown in fig. 5, P-type impurity ions are implanted through the second Mask and the third Mask at the corresponding positions of the region other than the Mask identification position, i.e., at the halo region of the transfer transistor on the side close to the storage node, so that the second implantation concentration increases. In this case, the above-described process of measuring IV characteristics is continued.

In some embodiments, the implant concentration thereof, i.e., the second implant concentration, may be adjusted only for halo regions near the storage node side. In another embodiment, the implantation concentrations of the halo regions on both the bit line side and the storage node side may be first adjusted using a second mask. Then, the third mask is used to adjust the implantation concentration of only the halo region on the storage node side. The present disclosure is not limited in this form.

Fig. 11A shows a conventional optimization flow chart for parameter optimization of a semiconductor device. Fig. 11B illustrates an optimization flow diagram for parameter optimization of a semiconductor device in accordance with an embodiment of the present disclosure. As can be seen from fig. 11A, for the conventional optimization method, the performance of the SRAM cell was tested after reticle fabrication via the tape-out and WAT electrical tests. At this time, if asymmetry of the SRAM cell is found, the physical layout GDS needs to be modified. However, this is a complete set of slice work, which is time consuming and costly.

Fig. 11B greatly shortens the optimization process. In some embodiments, low cost simulations may be performed using TCAD tools to arrive at optimized process conditions. In another embodiment, the optimized process conditions may also be obtained by actual flow sheet. In the actual flow sheet testing process, the actual effect is easier to test feedback in time, and the optimized process conditions can be fed back by 1-2 alternate sheets. Moreover, the optimization process according to embodiments of the present disclosure does not increase the cost of the photomask nor affect the development process.

Furthermore, embodiments of the present disclosure are not limited to 28nm polysilicon gate-silicon oxynitride Poly-SION processes. In some embodiments, a lower node such as a 40nm/55nm/65nm fabrication process may be employed to obtain a performance enhanced DP-SRAM cell.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

1. A semiconductor device comprising a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell comprising:

a first inverter and a second inverter, the inputs and outputs of which are cross-coupled to form a first storage node and a second storage node for storing data, the first storage node storing a state opposite to a state stored by the second storage node;

a first pair of transfer transistors including a first transfer transistor and a second transfer transistor and configured to couple a first bit line to the first storage node and the second storage node, respectively, for reading and writing the data;

a second pair of transfer transistors including a third transfer transistor and a fourth transfer transistor and configured to couple a second bit line to the first storage node and the second storage node, respectively, for reading and writing the data;

Wherein the first transfer transistor includes a first halo region on the first storage node side, and a second halo region in the first bit line pair corresponding to the bit line side of the first storage node, the second halo region having an impurity implantation concentration smaller than that of the first halo region;

wherein the fourth transfer transistor includes a third halo region on the second storage node side and a fourth halo region in the second bit line pair corresponding to the bit line side of the second storage node, the fourth halo region having an impurity implantation concentration smaller than that of the third halo region,

wherein the second transfer transistor includes a fifth halo region on the second storage node side and a sixth halo region on the bit line side corresponding to the second storage node in the first bit line pair, the fifth halo region having an impurity implantation concentration equal to that of the sixth halo region, and

wherein the third transfer transistor includes a seventh halo region on the first storage node side and an eighth halo region in the second bit line pair corresponding to the bit line side of the first storage node, an impurity implantation concentration of the seventh halo region being equal to an impurity implantation concentration of the eighth halo region.

2. The semiconductor device of claim 1, wherein impurity implantation concentrations of the second, fourth, fifth, sixth, seventh, and eighth halo regions are the same.

3. The semiconductor device of claim 1, wherein an impurity implantation concentration of the first halo region is the same as an impurity implantation concentration of the third halo region.

4. A semiconductor device according to any one of claims 2 to 3, wherein the first to fourth transfer transistors each comprise a lightly doped extension region having a first conductivity type.

5. The semiconductor device of claim 4, wherein the first through eighth halo regions are formed respectively under respective lightly doped extension regions of respective pass transistors and have a second conductivity type opposite the first conductivity type.

6. A method of manufacturing a semiconductor device comprising a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell comprising a first bit line pair and a second bit line pair, a cross-coupled inverter pair having a first storage node and a second storage node for storing data, and a first pair of transfer transistors and a second pair of transfer transistors selectively coupling the cross-coupled inverter pair to the first bit line pair and the second bit line pair, respectively, the method comprising:

Forming a first element forming region and a second element forming region in a semiconductor substrate, a plurality of first elements having a first conductivity type being formed in the first element forming region and a plurality of second elements having a second conductivity type being formed in the second element forming region, the plurality of first elements and the plurality of second elements constituting the DP-SRAM cell, the plurality of first elements including the first pair of transfer transistors and the second pair of transfer transistors;

implanting impurity ions of the first conductivity type at corresponding positions in the first element forming regions to form lightly doped extension regions of the first conductivity type of the plurality of first elements; and

implanting impurity ions of the second conductivity type under the lightly doped extension region of the first conductivity type to form a halo region of the second conductivity type such that an implantation concentration of a halo region of the first pair of transfer transistors on a bit line side of the transfer transistor corresponding to the first storage node is smaller than an implantation concentration of a halo region of the transfer transistor on a first storage node side, and such that an implantation concentration of a halo region of the second pair of transfer transistors on a bit line side of the transfer transistor corresponding to the second storage node is smaller than an implantation concentration of a halo region of the transfer transistor on a second storage node side,

Wherein the injection concentrations of the halo region on the bit line side and the halo region on the second storage node side of the transfer transistors corresponding to the second storage node in the first pair of transfer transistors are formed to be equal to each other, and

wherein the implantation concentrations of the halo region on the bit line side and the halo region on the second storage node side of the transfer transistors corresponding to the first storage node in the second pair of transfer transistors are formed to be equal to each other.

7. A method for optimizing parameters of a semiconductor device, the semiconductor device comprising a dual port static random access memory, DP-SRAM, array having a plurality of DP-SRAM cells, each DP-SRAM cell comprising a bit line pair, a cross-coupled inverter pair having a storage node for storing data, and a pass transistor pair selectively coupling the cross-coupled inverter pair to the bit line pair, the method comprising:

forming a first element forming region and a second element forming region in a semiconductor substrate, a plurality of first elements having a first conductivity type being formed in the first element forming region and a plurality of second elements having a second conductivity type being formed in the second element forming region, the plurality of first elements and the plurality of second elements constituting the DP-SRAM cell, the plurality of first elements including the pair of pass transistors;

Implanting impurity ions of the first conductivity type at corresponding positions in the first element forming regions to form lightly doped extension regions of the first conductivity type of the plurality of first elements;

implanting impurity ions of the second conductivity type under the lightly doped extension region of the first conductivity type to form a halo region of the second conductivity type such that a halo region of one of the pair of transfer transistors on a bit line side has a first implantation concentration and a halo region of the transfer transistor on the storage node side has a second implantation concentration greater than the first implantation concentration;

measuring a threshold voltage of each pass transistor of the pair of pass transistors at different current directions to obtain a threshold voltage difference indicative of asymmetry of the pass transistors; and

minimizing a difference between the threshold voltage differences of each pass transistor of the pair of pass transistors by adjusting the first implant concentration and the second implant concentration,

wherein a halo region of the other transfer transistor of the pair on a side close to the bit line is formed to have an implantation concentration equal to that of the halo region of the transfer transistor on a side close to the storage node.

8. The method of claim 7, wherein measuring the threshold voltage comprises: the current-voltage IV characteristics of each pass transistor in the pair of pass transistors at different current directions are measured.

9. The method of claim 7, the parameters comprising one or more of Static Noise Margin (SNM), write Margin (WM), roll-over voltage, and power consumption.