CN116631336B

CN116631336B - Display panel and display device

Info

Publication number: CN116631336B
Application number: CN202310603504.1A
Authority: CN
Inventors: 张文帅; 张典
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-05-25
Filing date: 2023-05-25
Publication date: 2026-01-20
Anticipated expiration: 2043-05-25
Also published as: CN116631336A

Abstract

This application discloses a display panel and a display device, relating to the field of display technology. The display panel includes multiple pixel circuit arrays, each pixel circuit array comprising at least two pixel circuit columns. Each pixel circuit column is connected to two signal lines. Each signal line transmits a data signal and a bias signal to the pixel circuits in the pixel circuit column in a time-division multiplexing manner. The two pixel circuit columns of the pixel circuit array are connected to the same first signal terminal and the same second signal terminal. The first signal terminal provides the data signal, and the second signal terminal provides the bias signal. According to the embodiments of this application, while achieving periodic reset of the first or second pole of the driving module of the dual data line circuit, it is beneficial for pixel arrangement design.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the continuous update of display panel technology, display panels are gradually developing towards light and thin, high screen occupation ratio and ultra-narrow frame.

In the related art, the single data line circuit can periodically reset the first pole or the second pole of the driving module by adding a bias circuit controlled by a bias signal in the pixel circuit, so as to improve the offset or hysteresis of the characteristics of the driving module after long-term operation. However, for a Dual Data Line (DDL) circuit in the related art, if a bias circuit controlled by a bias signal is added, a signal line is further added, which is not beneficial to design of pixel layout (layout).

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which are beneficial to pixel arrangement design while realizing the periodic reset of a first pole or a second pole of a driving module of a double-data-line circuit.

In a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a plurality of pixel circuit column groups, where the pixel circuit column groups include at least two pixel circuit columns, one pixel circuit column is connected to two signal lines, each signal line transmits a data signal and a bias signal to a pixel circuit in the pixel circuit column in a time-sharing manner, and the two pixel circuit columns of the pixel circuit column groups are connected to a same first signal end and a same second signal end, where the first signal end is used to provide a data signal, and the second signal end is used to provide a bias signal.

Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display device including the display panel as in the first aspect.

According to the display panel and the display device provided by the embodiment of the application, two signal lines are connected through one pixel circuit column, each signal line can transmit data signals and bias signals to the pixel circuits in the pixel circuit column in a time-sharing manner, no additional signal line is needed, the first pole or the second pole of the driving module can be reset periodically, and the display panel and the display device are beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module after long-term working and are also beneficial to pixel arrangement design.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar features, and in which the figures are not to scale.

Fig. 1 is a schematic view showing a structure of a display panel in the related art;

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 3 is a schematic diagram showing another structure of a display panel according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application;

Fig. 5 shows a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 7 shows a further operation timing diagram of the display panel according to the embodiment of the present application;

fig. 8 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 9 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 10 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

Fig. 11 is a schematic structural view of a display panel according to an embodiment of the present application;

fig. 12 is a schematic view showing another structure of a display panel according to an embodiment of the present application;

fig. 13 shows a further operation timing diagram of the display panel according to the embodiment of the present application;

fig. 14 is a schematic view showing another structure of a display panel according to an embodiment of the present application;

fig. 15 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

Fig. 16 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 17 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

Fig. 18 is a schematic view showing another structure of a display panel according to an embodiment of the present application;

Fig. 19 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 20 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 21 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 22 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 23 shows still another operation timing diagram of the display panel according to the embodiment of the present application;

fig. 24 is a schematic view showing another structure of a display panel according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises the element.

In embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application firstly specifically describes the problems existing in the related art:

an Organic LIGHT EMITTING Diode (OLED) display panel has many advantages of self-luminescence, fast response, high brightness, light weight, and the like, and has become a mainstream of the display field.

The inventor researches that, as shown in fig. 1, the related art adds an eighth transistor T8 based on the existing 7T1C pixel circuit, and controls the eighth transistor T8 to be turned on by controlling the control signal SP to be an on level, so that a signal on the DVH signal line is written into the N2 node, so as to realize periodic reset of the N2 node. By adjusting the potential applied to the N2 node, the driving transistor T3 can be placed in different on-bias (OBS) states, thereby improving the offset or hysteresis of the characteristics of the driving transistor T3 after long-term operation.

However, for the dual data line circuit, if a new DVH signal is to be added, the pixel arrangement (layout) design is not favored.

In order to solve the above-mentioned problems in the related art, embodiments of the present application provide a display panel and a display device, which are beneficial to pixel arrangement while realizing the periodic reset of the first pole or the second pole of the driving module of the dual data line circuit.

The following first describes a display panel provided by an embodiment of the present application.

As shown in fig. 2, the display panel 1000 may include a plurality of pixel circuit column groups 100, and the pixel circuit column groups 100 may include at least two pixel circuit columns. Each pixel circuit column may be arranged in the row direction X, and each pixel circuit column may include a plurality of pixel circuits 10 arranged in the column direction Y.

In fig. 2 and fig. 3, an example is taken in which one pixel circuit column group 100 includes two pixel circuit columns, but the number of the pixel circuit columns included in the pixel circuit column group 100 is not limited thereto, and may be set according to practical situations, and is not limited thereto. For example, one pixel circuit column group 100 may include three pixel circuit columns, four pixel circuit columns, and the like.

One pixel circuit column may be connected to two signal lines, that is, two signal lines may be connected to each pixel circuit column in the pixel circuit column group 100. Each signal line time-sharing transmits a data signal and a bias signal to the pixel circuits 10 in the pixel circuit columns, and two pixel circuit columns of the pixel circuit column group 100 may be connected to the same first signal terminal source and the same second signal terminal DVH, where the first signal terminal source may be used to provide the data signal and the second signal terminal DVH may be used to provide the bias signal.

Illustratively, at a first moment, the data signal of the first signal terminal source may be transmitted to the pixel circuits 10 in the pixel circuit columns through one of the two signal lines, and the bias signal of the second signal terminal DVH may be transmitted to the pixel circuits 10 in the pixel circuit columns through the other of the two signal lines. At the second moment, the bias signal of the second signal terminal DVH may be transmitted to the pixel circuits 10 in the pixel circuit columns through one of the two signal lines, and the data signal of the first signal terminal source may be transmitted to the pixel circuits 10 in the pixel circuit columns through the other of the two signal lines. Wherein the first time and the second time are different times.

Therefore, the application can periodically reset the first pole or the second pole of the driving module 11 without adding an additional signal wire, thereby being beneficial to improving the offset and hysteresis of the characteristics of the driving module 11 after long-term working and being beneficial to the design of pixel arrangement.

In some alternative embodiments, the display panel 1000 may further include a first gate circuit 200 and a second gate circuit 300, and at least two pixel circuit columns may include a first pixel circuit column 110 and a second pixel circuit column 120.

Two signal lines connected to the first pixel circuit column 110 are connected to the first signal terminal source through the first gate circuit 200, and two signal lines connected to the first pixel circuit column 110 are connected to the second signal terminal DVH through the second gate circuit 300.

That is, a first end of each of the two signal lines connected to the first pixel circuit column 110 may be connected to the first signal terminal source through the first gate circuit 200 to receive the data signal of the first signal terminal source. A second end of each of the two signal lines connected to the first pixel circuit column 110 may be connected to the second signal terminal DVH through the second gate circuit 300 to receive the bias signal of the second signal terminal DVH.

The two signal lines connected to the second pixel circuit column 120 are connected to the first signal terminal source through the first gate circuit 200, and the two signal lines connected to the second pixel circuit column 120 are connected to the second signal terminal DVH through the second gate circuit 300.

That is, a first end of each of the two signal lines connected to the second pixel circuit column 120 may be connected to the first signal terminal source through the first gate circuit 200 to receive the data signal of the first signal terminal source. A second end of each of the two signal lines connected to the second pixel circuit column 120 may be connected to the second signal terminal DVH through the second gate circuit 300 to receive the bias signal of the second signal terminal DVH.

The first strobe circuit 200 may be used to transmit the data signal provided by the first signal source to the four signal lines of the pixel circuit column group 100 in a time-sharing manner. That is, the first gate circuit 200 may be used to time-share the data signal provided by the first signal terminal source to the two signal lines connected to the first pixel circuit column 110 and the two signal lines connected to the second pixel circuit column 120.

The second gating circuit 300 may be configured to transmit the bias signal provided by the second signal terminal DVH to four signal lines of the pixel circuit column group 100 in a time-sharing manner. That is, the second gate circuit 300 may be used to transmit the bias signal provided by the second signal terminal DVH to the two signal lines connected to the first pixel circuit column 110 and the two signal lines connected to the second pixel circuit column 120 in a time-sharing manner.

In this embodiment, by providing the first gating circuit 200 between the first signal terminal source and the pixel circuit column group 100 and providing the second gating circuit 300 between the second signal terminal DVH and the pixel circuit column group 100, the data signal and the bias signal can be transmitted to the pixel circuits 10 in the pixel circuit column group 100 in a time-sharing manner by controlling the on/off states of the first gating circuit 200 and the second gating circuit 300.

In some alternative embodiments, two signal lines connected to the first pixel circuit column 110 may include a first signal line data1 and a third signal line data3, and two signal lines connected to the second pixel circuit column 120 may include a second signal line data2 and a fourth signal line data4.

The first gating circuit 200 may include a first switching element K1, a second switching element K2, a third switching element K3, and a fourth switching element K4, wherein a first end of the first switching element K1, a first end of the second switching element K2, a first end of the third switching element K3, and a first end of the fourth switching element K4 are all connected to the first signal terminal source, a second end of the first switching element K1 is connected to the first signal line data1, a second end of the third switching element K3 is connected to the third signal line data3, a second end of the fourth switching element K4 is connected to the fourth signal line data4, and a second end of the second switching element K2 is connected to the second signal line data 2.

Illustratively, the first switching element K1 may include a first transistor M1, the second switching element K2 may include a second transistor M2, the third switching element K3 may include a third transistor M3, and the fourth switching element K4 may include a fourth transistor M4. The first terminal of the first switching element K1 may be a first pole of the first transistor M1, and the second terminal of the first switching element K1 may be a second pole of the first transistor M1. The first terminal of the second switching element K2 may be a first pole of the second transistor M2, and the second terminal of the second switching element K2 may be a second pole of the second transistor M2. The first terminal of the third switching element K3 may be a first pole of the third transistor M3, and the second terminal of the third switching element K3 may be a second pole of the third transistor M3. The first terminal of the fourth switching element K4 may be a first pole of the fourth transistor M4, and the second terminal of the fourth switching element K4 may be a second pole of the fourth transistor M4.

In the present application, the first pole of each transistor may be one of the source or the drain, and the second pole of each transistor may be the other of the source or the drain.

The second gating circuit 300 includes a fifth switching element K5, a sixth switching element K6, a seventh switching element K7, and an eighth switching element K8, wherein a first end of the fifth switching element K5, a first end of the sixth switching element K6, a first end of the seventh switching element K7, and a first end of the eighth switching element K8 are all connected to the second signal terminal DVH, a second end of the fifth switching element K5 is connected to the first signal line data1, a second end of the sixth switching element K6 is connected to the third signal line data3, a second end of the seventh switching element K7 is connected to the fourth signal line data4, and a second end of the eighth switching element K8 is connected to the second signal line data 2.

Illustratively, the fifth switching element K5 may include a fifth transistor M5, the sixth switching element K6 may include a sixth transistor M6, the seventh switching element K7 may include a seventh transistor M7, and the eighth switching element K8 may include an eighth transistor M8. The first terminal of the fifth switching element K5 may be a first pole of the fifth transistor M5, and the second terminal of the fifth switching element K5 may be a second pole of the fifth transistor M5. The first terminal of the sixth switching element K6 may be a first pole of the sixth transistor M6, and the second terminal of the sixth switching element K6 may be a second pole of the sixth transistor M6. The first terminal of the seventh switching element K7 may be a first pole of the seventh transistor M7, and the second terminal of the seventh switching element K7 may be a second pole of the seventh transistor M7. The first terminal of the eighth switching element K8 may be a first pole of the eighth transistor M8, and the second terminal of the eighth switching element K8 may be a second pole of the eighth transistor M8.

The first switching element K1 and the sixth switching element K6 are turned on or off under the control of the first control signal line mux1, the second switching element K2 and the seventh switching element K7 are turned on or off under the control of the second control signal line mux2, the third switching element K3 and the fifth switching element K5 are turned on or off under the control of the third control signal line mux3, and the fourth switching element K4 and the eighth switching element K8 are turned on or off under the control of the fourth control signal line mux 4.

The first control signal on the first control signal line mux1, the second control signal on the second control signal line mux2, the third control signal on the third control signal line mux3, and the fourth control signal on the fourth control signal line mux4 are all different.

In the present embodiment, by providing a plurality of switching elements in each of the first gate circuit 200 and the second gate circuit 300, the on/off of each of the switching elements can be controlled to control the on/off of the first gate circuit 200 and/or the second gate circuit 300, and thus the data signal and the bias signal can be transmitted to the pixel circuits 10 in the pixel circuit column group 100 in a time-sharing manner.

Further, since the first switching element K1 and the sixth switching element K6 are simultaneously turned on or simultaneously turned off, the second switching element K2 and the seventh switching element K7 are simultaneously turned on or simultaneously turned off, the third switching element K3 and the fifth switching element K5 are simultaneously turned on or simultaneously turned off, and the fourth switching element K4 and the eighth switching element K8 are simultaneously turned on or simultaneously turned off, the data signal writing period and the bias signal writing period are equal for the same pixel circuit 10.

In other alternative embodiments, as shown in fig. 4, two signal lines connected to the first pixel circuit column 110 include a first signal line data1 and a third signal line data3, and two signal lines connected to the second pixel circuit column 120 include a second signal line data2 and a fourth signal line data4.

The first gating circuit 200 includes a first switching element K1, a second switching element K2, a third switching element K3, and a fourth switching element K4, wherein a first end of the first switching element K1, a first end of the second switching element K2, a first end of the third switching element K3, and a first end of the fourth switching element K4 are all connected to the first signal terminal source, a second end of the first switching element K1 is connected to the first signal line data1, a second end of the second switching element K2 is connected to the second signal line data2, a second end of the third switching element K3 is connected to the third signal line data3, and a second end of the fourth switching element K4 is connected to the fourth signal line data 4.

The first switching element K1 is turned on or off under the control of the first control signal line mux1, the second switching element K2, the sixth switching element K6 and the seventh switching element K7 are all turned on or off under the control of the second control signal line mux2, the third switching element K3 is turned on or off under the control of the third control signal line mux3, and the fourth switching element K4, the fifth switching element K5 and the eighth switching element K8 are all turned on or off under the control of the fourth control signal line mux 4.

In this embodiment, the first switching element K1 is turned on or off under the control of the first control signal line mux1, the second switching element K2, the sixth switching element K6 and the seventh switching element K7 are turned on or off under the control of the second control signal line mux2, the third switching element K3 is turned on or off under the control of the third control signal line mux3, and the fourth switching element K4, the fifth switching element K5 and the eighth switching element K8 are turned on or off under the control of the fourth control signal line mux4, so that the duration of the output data signal can be increased, which is beneficial to improving the effect of threshold compensation, improving the uniformity of the display panel 1000 and improving the ghost phenomenon. For example, since the first switching element K1 is turned on or off under the control of the first control signal line mux1, the fifth switching element K5 is turned on or off under the control of the fourth control signal line mux4, for the first signal line data1, when the first control signal on the first control signal line mux1 is at the on level, the data signal is written, and when the fourth control signal on the fourth control signal line mux4 is at the on level, the data signal is stopped to be written, and the writing of the bias signal is started, and the duration of the data signal is further longer than the duration of the output bias signal, which is beneficial to improving the effect of threshold compensation, improving the uniformity of the display panel 1000 and improving the ghost phenomenon.

In some alternative embodiments, each pixel circuit 10 in the first pixel circuit column 110 may be connected to both the first signal line data1 and the third signal line data 3. That is, the first end of each pixel circuit 10 in the first pixel circuit column 110 can be connected to the first signal line data1, and the second end of each pixel circuit 10 in the first pixel circuit column 110 can be connected to the third signal line data 3. In this way, each pixel circuit 10 in the first pixel circuit column 110 can receive the data signal of the first signal source and the bias signal of the second signal DVH.

For convenience of explanation, the first pixel circuit column 110 may include a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2, as shown in fig. 3, 4, 11, and 14. The first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2 and the second blue pixel circuit B2 are all connected with the first signal line data1, and the first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2 and the second blue pixel circuit B2 are all connected with the third signal line data 3.

Each pixel circuit 10 in the second pixel circuit column 120 is connected to the second signal line data2 and the fourth signal line data 4. That is, the first end of each pixel circuit 10 in the second pixel circuit column 120 can be connected to the second signal line data2, and the second end of each pixel circuit 10 in the second pixel circuit column 120 can be connected to the fourth signal line data 4. In this way, each pixel circuit 10 in the second pixel circuit column 120 can receive the data signal of the source of the first signal terminal and the bias signal of the DVH of the second signal terminal.

Illustratively, as shown in fig. 3, the second pixel circuit column 120 may include a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The first, second, third, and fourth green pixel circuits G1, G2, G3, and G4 may be all connected to the second signal line data2, and the first, second, third, and fourth green pixel circuits G1, G2, G3, and G4 may be all connected to the fourth signal line data 4.

In some alternative embodiments, as shown in fig. 5, the pixel circuit 10 may include a driving module 11, a data writing module 12, and a biasing module 13, the data writing module 12 may be used to transmit a data signal to the driving module 11, and the biasing module 13 may be used to transmit a biasing signal to the driving module 11.

The data writing block 12 of the odd-numbered row pixel circuits 10 in the first pixel circuit column 110 may be connected to the first signal line data1, and the bias block 13 of the odd-numbered row pixel circuits 10 in the first pixel circuit column 110 is connected to the third signal line data 3.

The data writing block 12 of the even row pixel circuits 10 in the first pixel circuit column 110 may be connected to the third signal line data3, and the bias block 13 of the even row pixel circuits 10 in the first pixel circuit column 110 is connected to the first signal line data 1.

In this embodiment, since the data writing module 12 of the odd-numbered row pixel circuits 10 and the data writing module 12 of the even-numbered row pixel circuits 10 in the first pixel circuit column 110 are connected to different signal lines, the writing duration of the data signal of each pixel circuit 10 in the first pixel circuit column 110 may be longer than the scanning duration of one row of pixel circuits 10, so that the threshold compensation effect of each pixel circuit 10 in the first pixel circuit column 110 is advantageously improved, the uniformity of the display panel 1000 is improved, and the afterimage problem of the display panel 1000 is improved.

Alternatively, the data writing module 12 may be electrically connected between one of two signal lines connected to the pixel circuit columns and the control terminal of the driving module 11, and the control terminal of the data writing module 12 may be electrically connected to the first scan signal line scan 1. The bias module 13 may be electrically connected between the other of the two signal lines connected to the pixel circuit columns and the first end of the driving module 11, and the control end of the bias module 13 may be electrically connected with the second scan signal.

For example, as shown in fig. 3, the first pixel circuit column 110 includes a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The data writing block 12 of the first red pixel circuit R1 and the data writing block 12 of the second red pixel circuit R2 may be connected to the first signal line data1, and the bias block 13 of the first red pixel circuit R1 and the bias block 13 of the second red pixel circuit R2 may be connected to the third signal line data 3. The data writing module 12 of the first blue pixel circuit B1 and the data writing module 12 of the second blue pixel circuit B2 may be connected to the third signal line data3, and the bias module 13 of the first blue pixel circuit B1 and the bias module 13 of the second blue pixel circuit B2 may be connected to the first signal line data 1.

Since the data writing module 12 of the first red pixel circuit R1 is connected to the first signal line data1, the data writing module 12 of the first blue pixel circuit B1 is connected to the second signal line data2, and the data writing module 12 of the second red pixel circuit R2 is connected to the first signal line data1, the data signal writing duration of the first red pixel circuit R1 may be longer than the line scanning duration of the line of the first red pixel circuit R1, and only the first red pixel circuit R1 needs to stop writing the data signal before the data signal of the second red pixel circuit R2 is written.

The data writing module 12 of the odd-row pixel circuits 10 in the second pixel circuit column 120 is connected to the second signal line data2, and the bias module 13 of the odd-row pixel circuits 10 in the second pixel circuit column 120 is connected to the fourth signal line data 4;

the data writing block 12 of the even-row pixel circuits 10 in the second pixel circuit column 120 is connected to the fourth signal line data4, and the bias block 13 of the even-row pixel circuits 10 in the second pixel circuit column 120 is connected to the second signal line data 2.

In this embodiment, since the data writing module 12 of the odd-numbered row pixel circuits 10 and the data writing module 12 of the even-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected to different signal lines, the writing duration of the data signal of each pixel circuit 10 in the second pixel circuit column 120 may be longer than the scanning duration of one row of pixel circuits 10, so that the threshold compensation effect of each pixel circuit 10 in the second pixel circuit column 120 is advantageously improved, the uniformity of the display panel 1000 is improved, and the afterimage problem of the display panel 1000 is improved.

Illustratively, as shown in fig. 3, the second pixel circuit column 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The data writing module 12 of the first green pixel circuit G1 and the data writing module 12 of the third green pixel circuit G3 may be connected to the second signal line data2, and the bias module 13 of the first green pixel circuit G1 and the bias module 13 of the third green pixel circuit G3 may be connected to the fourth signal line data 4. The data writing module 12 of the second green pixel circuit G2 and the data writing module 12 of the fourth green pixel circuit G4 may be connected to the fourth signal line data4, and the bias module 13 of the second green pixel circuit G2 and the bias module 13 of the fourth green pixel circuit G4 may be connected to the second signal line data 2.

Since the data writing module 12 of the first green pixel circuit G1 is connected to the second signal line data2, the data writing module 12 of the second green pixel circuit G2 is connected to the fourth signal line data4, and the data writing module 12 of the third green pixel circuit G3 is connected to the second signal line data2, the data signal writing duration of the first green pixel circuit G1 may be longer than the line scanning duration of the first green pixel circuit G1, and only the first green pixel circuit G1 needs to stop writing the data signal before the data signal of the third green pixel circuit G3 is written.

Alternatively, as shown in fig. 5, the display panel 1000 may further include a light emitting module 20, and the pixel circuit 10 may further include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light emitting control module 17, and a storage module 18. The first reset module 14 may be electrically connected between the first reset signal line and the control terminal of the driving module 11, and may be used to write the first reset signal on the first reset signal line to the control terminal of the driving module 11 to reset the control terminal of the driving module 11. The second reset module 15 may be electrically connected between the second reset signal line and the first end of the light emitting module 20, and may be used to write a second reset signal on the second reset signal line to the first end of the light emitting module 20 to reset the first end of the light emitting module 20. The threshold compensation module 16 may be electrically connected between the control terminal of the driving module 11 and the second terminal of the driving module 11, and may be used to compensate the threshold voltage of the driving module 11. The light-emitting control module 17 may be connected in series with the light-emitting module 20 between the first power line PVDD and the second power line PVEE, and may be used to control the light-emitting module 20 to enter a light-emitting phase. The memory module 18 may be electrically connected between the first power line PVDD and the control terminal of the driving module 11, and may be used to maintain the potential of the control terminal of the driving module 11. The light emission control module 17 may include a first light emission control module 171 and a second light emission control module 172, the first light emission control module 171 may be electrically connected between the first power line PVDD and the first end of the driving module 11, and the second light emission control module 172 may be electrically connected between the second end of the driving module 11 and the first end of the light emitting module 20.

Illustratively, as shown in fig. 6, the driving module 11 may include a ninth transistor M9, the data writing module 12 may include a tenth transistor M10, the biasing module 13 may include an eleventh transistor M11, the first reset module 14 may include a twelfth transistor M12, the second reset module 15 may include a thirteenth transistor M13, the threshold compensation module 16 may include a fourteenth transistor M14, the first light emitting control module 171 may include a fifteenth transistor M15, the second light emitting control module 172 may include a sixteenth transistor M16, and the storage module 18 may include a first capacitor. The light emitting module 20 may include a light emitting element D. The twelfth transistor M12 and the fourteenth transistor M14 may each be a double gate transistor.

The control terminal of the driving module 11 may be the gate of the ninth transistor M9, the first terminal of the driving module 11 may be one of the source and the drain of the ninth transistor M9, and the second terminal of the driving module 11 may be the other of the source and the drain of the ninth transistor M9. The first end of the light emitting module 20 may be a first pole of the light emitting element D, and the second end of the light emitting module 20 may be a second pole of the light emitting element D. The first pole of the light emitting element D may be an anode and the second pole of the light emitting element D may be a cathode.

In some alternative embodiments, as shown in fig. 7 and 8, the display panel 1000 may include a plurality of rows of pixel circuits 10, the operation of each row of pixel circuits 10 may include a data writing stage during a display time of one frame, the data writing stage may include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage may be preceded by the first bias sub-stage, the driving module 11 of the pixel circuit 10 may write a data signal during the data writing sub-stage, the driving module 11 of the pixel circuit 10 may write a bias signal during the first bias sub-stage, and the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 may be sequentially on levels.

In order to facilitate distinguishing the first bias sub-stage of the different rows of pixel circuits 10, in fig. 7 and 8, the data writing sub-stage d (i) and the first bias sub-stage c (i) correspond to the i-th row of pixel circuits 10, and the data writing sub-stage d (i+1) and the first bias sub-stage c (i+1) correspond to the i+1-th row of pixel circuits 10.

The data writing sub-stage of the i+2 row of pixel circuits 10 may at least partially overlap the first biasing sub-stage of the i row of pixel circuits 10, the data writing sub-stages of any two rows of pixel circuits 10 may not overlap, and the first biasing sub-stages of any two rows of pixel circuits 10 may not overlap, wherein i is a positive integer.

Illustratively, the data writing sub-stage d (1) of the 3 rd row of pixel circuits 10 may at least partially overlap the first biasing sub-stage of the 1 st row of pixel circuits 10, the data writing sub-stage of the 1 st row of pixel circuits 10 and the data writing sub-stage of the 2 nd row of pixel circuits 10 do not overlap, and the first biasing sub-stage of the 1 st row of pixel circuits 10 and the first biasing sub-stage of the 2 nd row of pixel circuits 10 do not overlap.

In this embodiment, the data writing sub-stage of the i+2 row pixel circuit 10 at least partially overlaps the first bias sub-stage of the i+2 row pixel circuit 10, that is, when the driving module 11 of the i+2 row pixel circuit 10 writes the data signal, the driving module 11 of the i row pixel circuit 10 writes the bias signal, and the data signal and the bias signal are transmitted to the same pixel circuit 10 in a time sharing manner through different signal lines, without adding additional signal lines, so that the first pole or the second pole of the driving module 11 in the pixel circuit 10 can be periodically reset, which is beneficial to improving the offset and hysteresis of the characteristics of the driving module 11 after long-term operation, and is beneficial to the design of pixel arrangement.

As an example, referring to fig. 3, 6 and 7 together, for two adjacent rows of pixel circuits 10, the process of changing the control signals on the first control signal line mux1 to the fourth control signal line mux4 may include the following steps a1 to a4, and the operation of the display panel 1000 may be as follows:

In the first sub-stage of the stage a1, the control signal on the first control signal line mux1 may be on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 may be off level, the first transistor M1 and the sixth transistor M6 are both on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are both off, the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the ith row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the first red pixel circuit R1 of the ith row through the third signal line data3 and the sixth transistor M6.

Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the i-th row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the i+1th row pixel circuit 10 are both off-levels, neither the i-th row pixel circuit 10 nor the i+1th row pixel circuit 10 writes the data signal nor the bias signal.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6, and the eighth transistor M8 are all off, the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the ith row through the second signal line data2 and the second transistor M2, the ninth transistor M9 in the first green pixel circuit G1 is written, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 of the first green pixel circuit G1 of the ith row through the fourth signal line data4 and the seventh transistor M7.

In the data writing sub-stage d (i), the first scan signal on the first scan signal line scan1 connected to the i-th row pixel circuit 10 is at an on level, the data writing module 12 of the i-th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source is transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the i+1th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 of the i+1th row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-levels, the control signal on the fourth control signal line mux4 is on-levels, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the i+1th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 through the second signal line data2 and the eighth transistor M8.

In the data writing sub-stage d (i+1), the second scanning signal on the first scanning signal line scan1 of the i+1 th row is at an on level, the data writing module 12 of the i+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 and the sixth transistor M6 are both on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are both off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the i+2 row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second red pixel circuit R2 of the i+2 row through the third signal line data3 and the sixth transistor M6.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the first scanning signal on the first scanning signal line scan1 of the first row is at an off level, the second transistor M2 and the seventh transistor M7 are both on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be written into the ninth transistor M9 in the third green pixel circuit G3 through the second signal line data2 and the tenth transistor M10 in the second green pixel circuit G3 of the i+2 row, and the bias signal of the second signal terminal DVH can be transmitted to the drain electrode 11 of the third green pixel circuit G3 of the eleventh row through the fourth signal line data4 and the seventh transistor M7.

In the first bias sub-stage c (i), the second scan signal on the second scan signal line scan of the i-th row is at an on level, the bias block 13 of the i-th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the bias signal is written into both the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off, the control signal on the third control signal line mux3 is on, the control signal on the fourth control signal line mux4 is off, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the i+3 row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second blue pixel circuit B2 of the i+3 row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-levels, the control signal on the fourth control signal line mux4 is on-levels, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the i+3 row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the fourth green pixel circuit G4 through the second signal line data2 and the eighth transistor M8.

In the first bias sub-stage c (i+1), the second scan signal on the second scan signal line scan of the i+1 th row is at an on level, the bias block 13 of the i+1 th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2.

And so on.

Illustratively, i may be 1.

As another example, referring to fig. 4, 6 and 8, for two adjacent rows of pixel circuits 10, the process of changing the control signals on the first control signal line mux1 to the fourth control signal line mux4 may include the following steps a1 to a4, and the operation of the display panel 1000 may be as follows:

in the first sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the ith row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3, the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the ith row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 of the ith row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the first signal terminal source or drain of the eleventh transistor M11 in the ith row can be transmitted to the source or drain of the eleventh transistor M3 through the second signal line data2 and the seventh transistor M3.

In the first sub-stage of the data writing sub-stage d (i), the first scanning signal on the first scanning signal line scan1 connected to the i-th row pixel circuit 10 is at an on level, the data writing module 12 of the i-th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal terminal source is transmitted to the source of the tenth transistor M10 in the first blue pixel circuit B1 of the i+1th row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the data writing sub-stage d (i), the first scanning signal on the first scanning signal line scan1 connected to the i-th row pixel circuit 10 is at an on level, the data writing module 12 of the i-th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the control signal on the fourth control signal line mux4 is on-level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the i+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 through the second signal line data2 and the eighth transistor M8, and the bias signal terminal DVH can be further transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G1 through the second signal line data2 and the eighth transistor M8.

In the first sub-stage of the data writing sub-stage d (i+1), the first scan signal on the first scan signal line scan1 of the i+1 th row is at an on level, the data writing module 12 of the i+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 is on, the second transistor M2 to the eighth transistor M8 are off, and the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the i+2th row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the data writing sub-stage d (i+1), the first scan signal on the first scan signal line scan1 of the i+1 th row is at an on level, the data writing module 12 of the i+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G3 of the i+2 row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 of the i+2 row through the fourth signal line data4 and the seventh transistor M7, and the data signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 of the i+2 row through the second signal line data2 and the seventh signal terminal DVH.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the i+3rd row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the control signal on the fourth control signal line mux4 is on-level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 through the fourth signal line data4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the fourth green pixel circuit G4 through the second signal line data2 and the eighth transistor M8, and the data signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the fourth green pixel circuit G4 through the second signal line data2 and the fifth transistor M5.

And so on.

Illustratively, i may be 1.

Fig. 7 is different from fig. 8 in that the duration of the data writing sub-phase of each row of the pixel circuits 10 in fig. 7 is equal to the duration of the first bias sub-phase, and the duration of the data writing sub-phase of each row of the pixel circuits 10 in fig. 8 is longer than the duration of the first bias sub-phase. Since the data writing sub-stage of each row of the pixel circuits 10 in fig. 8 has a longer time period than the first bias sub-stage, the effect of threshold compensation is advantageously improved, the uniformity of display of the display panel 1000 is improved, and the afterimage phenomenon is improved.

In other alternative embodiments, as shown in fig. 9 and 10, the display panel 1000 may include a plurality of rows of pixel circuits 10, and during a display time of one frame, an operation process of each row of pixel circuits 10 may include a data writing stage, and the data writing stage may include a data writing sub-stage and a first bias sub-stage after the first bias sub-stage, and during the data writing sub-stage, the driving module 11 of the pixel circuit 10 may write a data signal, and during the first bias sub-stage, the driving module 11 of the pixel circuit 10 may write a bias signal;

The data writing sub-stage of the j-th row of pixel circuits 10 may at least partially overlap the first biasing sub-stage of the j+2-th row of pixel circuits 10, the data writing sub-stages of any two rows of pixel circuits 10 may not overlap, and the first biasing sub-stages of any two rows of pixel circuits 10 may not overlap;

wherein j is a positive integer.

In this embodiment, the data writing sub-stage of the jth row of pixel circuits 10 may at least partially overlap the first bias sub-stage of the jth+2 row of pixel circuits 10, that is, when the driving module 11 of the jth row of pixel circuits 10 writes data signals, the driving module 11 of the jth+2 row of pixel circuits 10 writes bias signals, and the data signals and bias signals are transmitted to the same pixel circuit 10 in a time sharing manner through different signal lines, without adding additional signal lines, so that the first pole or the second pole of the driving module 11 in the pixel circuit 10 can be periodically reset, which is beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module 11 after long-term operation, and is also beneficial to the design of pixel arrangement.

Fig. 9 differs from fig. 7 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 7 is before the first biasing sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 9 is after the first biasing sub-stage. The implementation principle corresponding to fig. 9 is similar to that corresponding to fig. 7, and will not be described again here.

Fig. 10 differs from fig. 8 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 8 is before the first biasing sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 10 is after the first biasing sub-stage. The implementation principle corresponding to fig. 10 is similar to that corresponding to fig. 8, and will not be described again here.

In some alternative embodiments, as shown in fig. 11, the odd-numbered row pixel circuits 10 in the first pixel circuit column 110 may be connected to the first signal line data1, and the even-numbered row pixel circuits 10 in the first pixel circuit column 110 may be connected to the third signal line data 3.

Illustratively, the first pixel circuit column 110 includes a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The first red pixel circuit R1 and the second red pixel circuit R2 are each connected to the first signal line data1, and the first blue pixel circuit B1 and the second blue pixel circuit B2 are each connected to the third signal line data 3.

The odd-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected to the second signal line data2, and the even-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected to the fourth signal line data 4.

Illustratively, the second pixel circuit column 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The first green pixel circuit G1 and the third green pixel circuit G3 are each connected to the second signal line data2, and the second green pixel circuit G2 and the fourth green pixel circuit G4 are each connected to the fourth signal line data 4.

That is, the data signal and the bias signal are time-divisionally transmitted to each pixel circuit 10 of the first pixel circuit column 110 and each pixel circuit 10 of the second pixel circuit column 120 through the same signal line. For example, the data signal and the bias signal are time-divisionally transferred to the first red pixel circuit R1 through the first signal line data 1.

In this embodiment, the odd-numbered pixel circuits 10 in the first pixel circuit column 110 are connected to the first signal line data1, the even-numbered pixel circuits 10 in the first pixel circuit column 110 are connected to the third signal line data3, the odd-numbered pixel circuits 10 in the second pixel circuit column 120 are connected to the second signal line data2, the even-numbered pixel circuits 10 in the second pixel circuit column 120 are connected to the fourth signal line data4, each signal line can time-divisionally transmit a data signal and a bias signal to the pixel circuits 10 in the pixel circuit column, no additional signal line is required to be added, the first pole or the second pole of the driving module 11 can be periodically reset, and the design of pixel arrangement is facilitated while the offset and hysteresis of the characteristics of the driving module 11 after long-term operation are improved.

In some alternative embodiments, as shown in fig. 14, the pixel circuit 10 may include a driving module 11, a data writing module 12, and a bias module 13, the data writing module 12 may be used to transmit a data signal to the driving module 11, the bias module 13 may be used to transmit a bias signal to the driving module 11, and the data signal and the bias signal may be the same.

The data writing blocks 12 and the bias blocks 13 of the odd-numbered pixel circuits 10 in the first pixel circuit column 110 are connected to the first signal line data1, respectively, and the data writing blocks 12 and the bias blocks 13 of the even-numbered pixel circuits 10 in the first pixel circuit column 110 are connected to the third signal line data3, respectively.

Illustratively, the first pixel circuit column 110 includes a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The data writing block 12 of the first red pixel circuit R1 and the bias block 13 of the first red pixel circuit R1 may be connected to the first signal line data1, respectively, and the data writing block 12 of the first blue pixel circuit B1 and the bias block 13 of the first blue pixel circuit B1 may be connected to the third signal line data3, respectively.

The data writing blocks 12 and the bias blocks 13 of the odd-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected to the second signal line data2, respectively, and the data writing blocks 12 and the bias blocks 13 of the even-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected to the fourth signal line data4, respectively.

Illustratively, the second pixel circuit column 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The data writing module 12 of the first green pixel circuit G1 and the bias module 13 of the first green pixel circuit G1 may be connected to the second signal line data2, respectively, and the data writing module 12 of the second green pixel circuit G2 and the bias module 13 of the second green pixel circuit G2 may be connected to the fourth signal line data4, respectively.

In this embodiment, the data writing module 12 and the bias module 13 are connected to the same signal line for the same pixel circuit 10, so that the number of signal lines in the same pixel circuit 10 can be reduced, and in addition, the data signal and the bias signal are identical, so that the signal crosstalk problem caused by different data signals and bias signals can be avoided.

Alternatively, as shown in fig. 12, the display panel 1000 may further include a light emitting module 20, and the pixel circuit 10 may further include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light emitting control module, and a storage module 18. The display panel 1000 in fig. 12 is different from the display panel 1000 in fig. 5 and 6 in that the Data writing module 12 and the bias module 13 in fig. 5 and 6 are connected to different signal lines, respectively, and the Data writing module 12 and the bias module 13 in fig. 12 are connected to the same signal line Data or Data. Wherein, signal line Data may be connected to first signal line Data1 or third signal line Data3, and signal line Data may be connected to second signal line Data2 or fourth signal line Data 4. The specific circuit structure of the display panel 1000 in fig. 12 is similar to that in fig. 5 and 6, and will not be described again.

In some alternative embodiments, as shown in fig. 13 and 15, the display panel 1000 may include a plurality of rows of pixel circuits 10, and during a display time of one frame of the display panel, the operation of each row of pixel circuits 10 may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage being preceded by the first bias sub-stage, in which the driving module 11 of the pixel circuit 10 writes a data signal, and in which the driving module 11 of the pixel circuit 10 writes a bias signal, the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 being sequentially on levels;

the data writing sub-stage of the n+1th row pixel circuit 10 may at least partially overlap the first bias sub-stage of the n-th row pixel circuit 10, the data writing sub-stages of any two rows of pixel circuits 10 may not overlap, and the first bias sub-stages of any two rows of pixel circuits 10 may not overlap;

Wherein n is a positive integer.

In this embodiment, the data writing sub-stage of the n+1 row pixel circuit 10 may at least partially overlap with the first biasing sub-stage of the n+1 row pixel circuit 10, that is, when the driving module 11 of the n+1 row pixel circuit 10 writes the data signal, the driving module 11 of the n row pixel circuit 10 writes the biasing signal, and the data signal and the biasing signal are transmitted to the same pixel circuit 10 in a time sharing manner through the same signal line, so that the first pole or the second pole of the driving module 11 in the pixel circuit 10 can be periodically reset without adding an additional signal line, which is beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module 11 after long-term operation, and is also beneficial to the pixel arrangement design.

As an example, referring to fig. 11, 12 and 13, the operation of the display panel 1000 may be as follows:

In the first sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 and the sixth transistor M6 are all on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the nth row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 of the (n+1) th row through the third signal line data3 and the sixth transistor M6.

Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the n-th row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the n+1th row pixel circuit 10 are both off-levels, the n-th row pixel circuit 10 and the n+1th row pixel circuit 10 do not write the data signal and the bias signal.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the nth row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the second green pixel circuit G2 of the (n+1) through the fourth signal line data4 and the seventh transistor M7.

In the data writing sub-stage d (n), the first scan signal on the first scan signal line scan1 connected to the nth row of pixel circuits 10 is at an on level, the data writing module 12 of the nth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the n+1th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first red pixel circuit R1 of the n+1th row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the n+1th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 through the second signal line data2, the eighth transistor M8, and the eleventh transistor M11 of the first green pixel circuit G1.

In the first bias sub-stage c (n), the second scan signal on the second scan signal line scan connected to the n-th row pixel circuit 10 is at an on level, and the bias block 13 of the n-th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1.

In the data writing sub-stage d (n+1), the first scan signal on the first scan signal line scan1 of the n+1 th row is at an on level, the data writing module 12 of the n+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 and the sixth transistor M6 are both on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are both off, the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the n+2 row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 of the n+1 row through the third signal line data3 and the sixth transistor M6.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the n+2 row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 of the n+1 row through the fourth signal line data4 and the seventh transistor M7.

In the first bias sub-stage c (n+1), the second scan signal on the second scan signal line scan of the n+1 th row is at an on level, the bias block 13 of the n+1 th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the n+3th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the second red pixel circuit R2 of the n+2row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-levels, the control signal on the fourth control signal line mux4 is on-levels, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the n+3 row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8.

And so on.

Illustratively, j may be 1.

As another example, referring to fig. 12, 14 and 15, the operation of the display panel 1000 may be as follows:

In the first sub-stage of the stage a1, the control signal on the first control signal line mux1 is on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all off level, the first transistor M1 is on, the second transistor M2 to the eighth transistor M8 are all off, and the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the first row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is turned off, the control signal on the second control signal line mux2 is turned on, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are turned off, the first scanning signal on the first scanning signal line scan1 of the first row is turned on, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the nth row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second row through the fourth signal line data4 and the seventh transistor M7, and the data signal of the first signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second row through the second signal line data2 and the fifth transistor M3 and the drain of the eleventh transistor M11.

In the first sub-stage of the data writing sub-stage d (n), the first scan signal on the first scan signal line scan1 connected to the nth row of pixel circuits 10 is on level, the data writing module 12 of the nth row of pixel circuits 10 is on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the n+1th row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the data writing sub-stage d (n), the first scanning signal on the first scanning signal line scan1 connected to the nth row of pixel circuits 10 is on level, the data writing module 12 of the nth row of pixel circuits 10 is on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the control signal on the fourth control signal line mux4 is on-level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the n+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8, and the data signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M1.

In the first bias sub-stage c (n), the second scan signal on the second scan signal line scan of the nth row is at an on level, the bias block 13 of the pixel circuit 10 of the nth row is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the bias signal is written into both the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1.

In the first sub-stage of the data writing sub-stage d (n+1), the first scan signal on the first scan signal line scan1 of the n+1 th row is at an on level, the data writing module 12 of the n+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 is on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the n+2th row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the data writing sub-stage d (n+1), the first scan signal on the first scan signal line scan1 of the n+1 th row is at an on level, the data writing module 12 of the n+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the n+3 row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 of the n+1 through the fourth signal line data4 and the seventh transistor M7, and the bias signal terminal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 of the n+1 row through the second signal line data2 and the fifth transistor M3.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the n+3rd row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the control signal on the fourth control signal line mux4 is on-level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the n+3 row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8, and the data signal of the second signal terminal DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 through the second signal line data2 and the fifth signal line DVH.

And so on.

Illustratively, j may be 1.

In other alternative embodiments, as shown in fig. 16 and 17, the display panel 1000 may include a plurality of rows of pixel circuits 10, and during a display time of one frame, the operation of each row of pixel circuits 10 may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage may be followed by the data writing sub-stage, in which the driving module 11 of the pixel circuit 10 writes a data signal, and in which the driving module 11 of the pixel circuit 10 writes a bias signal, the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 are sequentially on levels;

the data writing sub-stage of the mth row of pixel circuits 10 at least partially overlaps the first biasing sub-stage of the m+1th row of pixel circuits 10, the data writing sub-stages of any two rows of pixel circuits 10 do not overlap, and the first biasing sub-stages of any two rows of pixel circuits 10 do not overlap;

Wherein m is a positive integer.

In this embodiment, the data writing sub-stage of the mth row of pixel circuits 10 at least partially overlaps the first bias sub-stage of the m+1th row of pixel circuits 10, that is, when the driving module 11 of the mth row of pixel circuits 10 writes the data signal, the driving module 11 of the m+1th row of pixel circuits 10 writes the bias signal, and the data signal and the bias signal are transmitted to the same pixel circuit 10 in a time sharing manner through the same signal line, so that the first pole or the second pole of the driving module 11 in the pixel circuit 10 can be periodically reset without adding additional signal lines, which is beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module 11 after long-term operation, and is beneficial to the design of pixel arrangement.

Fig. 16 differs from fig. 13 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 13 is before the first biasing sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 16 is after the first biasing sub-stage. The implementation principle corresponding to fig. 13 is similar to that corresponding to fig. 16, and will not be described again here.

Fig. 17 differs from fig. 15 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 16 is before the first bias sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 18 is after the first bias sub-stage. The implementation principle corresponding to fig. 17 is similar to that corresponding to fig. 15, and will not be described again here.

In some alternative embodiments, as shown in fig. 18, the pixel circuit 10 may include a driving module 11 and a data writing module 12, and the data writing module 12 may be used to time-share data signals and bias signals to the driving module 11.

The data writing block 12 of the odd-numbered row pixel circuits 10 in the first pixel circuit column 110 may be connected to the first signal line data1, and the data writing block 12 of the even-numbered row pixel circuits 10 in the first pixel circuit column 110 may be connected to the third signal line data 3.

Illustratively, the first pixel circuit column 110 includes a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The data writing module 12 of the first red pixel circuit R1 and the data writing module 12 of the second red pixel circuit R2 may be both connected to the first signal line data 1. The data writing module 12 of the first blue pixel circuit B1 and the data writing module 12 of the second blue pixel circuit B2 may be both connected to the third signal line data 3.

The data writing modules 12 of the odd-numbered row pixel circuits 10 in the second pixel circuit column 120 may be connected to the second signal line data2, and the data writing modules 12 of the even-numbered row pixel circuits 10 in the second pixel circuit column 120 may be connected to the fourth signal line data 4.

Illustratively, the second pixel circuit column 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The data writing module 12 of the first green pixel circuit G1 and the data writing module 12 of the third green pixel circuit G3 may be both connected to the second signal line data2, and the data writing module 12 of the second green pixel circuit G2 and the data writing module 12 of the fourth green pixel circuit G4 may be both connected to the fourth signal line data 4.

That is, the data writing module 12 is multiplexed into the bias module 13, and the data signal and the bias signal are transmitted to the odd-numbered row pixel circuits 10 or the even-numbered row pixel circuits 10 in a time-sharing manner through the same signal line, so that the first pole or the second pole of the driving module 11 can be periodically reset without adding an additional bias module 13 and an additional signal line, which is beneficial to improving the offset and hysteresis of the characteristics of the driving module 11 after long-term operation and is also beneficial to the design of pixel arrangement.

Alternatively, as shown in fig. 18, the display panel 1000 may further include a light emitting module 20, and the pixel circuit 10 may further include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light emitting control module, and a storage module 18. The display panel 1000 in fig. 18 is different from the display panel 1000 in fig. 12 in that the display panel 1000 in fig. 12 includes the bias module 13, and the display panel 1000 in fig. 18 does not include the bias module 13. The specific circuit structure of the display panel 1000 in fig. 18 is similar to that in fig. 12, and will not be described again.

In some alternative embodiments, as shown in fig. 19 and 20, the display panel 1000 may include a plurality of rows of pixel circuits 10, and during a display time of one frame, an operation process of each row of pixel circuits 10 may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage may be preceded by the first bias sub-stage, in which a data signal may be written by the driving module 11 of the pixel circuit 10, and in which a bias signal may be written by the driving module 11 of the pixel circuit 10;

The data writing sub-stage of the (k+1) -th row pixel circuit 10 at least partially overlaps the first bias sub-stage of the (k) -th row pixel circuit 10, the data writing sub-stages of any two rows of pixel circuits 10 do not overlap, and the first bias sub-stages of any two rows of pixel circuits 10 do not overlap;

wherein k is a positive integer.

In this embodiment, the data writing sub-stage of the k+1 row pixel circuit 10 at least partially overlaps the first bias sub-stage of the k row pixel circuit 10, that is, when the driving module 11 of the k+1 row pixel circuit 10 writes the data signal, the driving module 11 of the k row pixel circuit 10 writes the bias signal, and the data signal and the bias signal are transmitted to the same pixel circuit 10 in a time sharing manner through the same signal line, so that the first pole or the second pole of the driving module 11 in the pixel circuit 10 can be periodically reset without adding an additional signal line, which is beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module 11 after long-term operation, and is beneficial to the design of pixel arrangement.

As an example, referring to fig. 14, 18 and 19, the operation of the display panel 1000 may be as follows:

In the first sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 and the sixth transistor M6 are all on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source of the tenth transistor M10 in the first red pixel circuit R1 of the kth row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH is transmitted to the source of the tenth transistor M10 in the first blue pixel circuit B1 of the kth+1 row through the third signal line data3 and the sixth transistor M6.

Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the kth line pixel circuit 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the kth+1 line pixel circuit 10 are both off-levels, neither the kth line pixel circuit 10 nor the kth+1 line pixel circuit 10 writes the data signal nor the bias signal.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux 2is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the k-th row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the seventh transistor M7.

In the data writing sub-stage d (k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the kth row of pixel circuits 10 are both on levels, the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the k+1th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the k+1th row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-levels, the control signal on the fourth control signal line mux4 is on-levels, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 of the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8.

In the first bias sub-stage c (k), the second scan signal on the second scan signal line scan connected to the kth row of pixel circuits 10 is at an on level, and the bias block 13 of the kth row of pixel circuits 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1.

In the data writing sub-stage d (k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan of the k+1 th row are both on levels, the data writing module 12 of the k+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 and the sixth transistor M6 are both on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are both off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the k+2 row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the k+1 row through the third signal line data3 and the sixth transistor M6.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the k+2 row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 through the fourth signal line data4 and the seventh transistor M7.

In the first bias sub-stage c (k+1), the second scan signal on the second scan signal line scan of the k+1 row is at an on level, the bias block 13 of the k+1 row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off, the control signal on the third control signal line mux3 is on, the control signal on the fourth control signal line mux4 is off, the third transistor M3 and the fifth transistor M5 are both on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the k+3 row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the k+2 row through the first signal line data1 and the fifth transistor M5.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-levels, the control signal on the fourth control signal line mux4 is on-levels, the fourth transistor M4 and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the k+3 row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8.

And so on.

Illustratively, k may be 1.

As another example, referring to fig. 14, 18 and 20, the operation of the display panel 1000 may be as follows:

In the first sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal source can be transmitted to the source or the drain of the tenth transistor M10 in the first red pixel circuit R1 of the kth row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the kth row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the kth+1row through the fourth signal line data4 and the seventh transistor M7, and the data signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the kth+1row through the second signal line data2 and the seventh transistor M3.

In the first sub-stage of the data writing sub-stage d (k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the kth row of pixel circuits 10 are both on levels, the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a2, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the k+1th row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the data writing sub-stage d (k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan connected to the kth row of pixel circuits 10 are both on levels, the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a2, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all turned off, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all turned off, the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 through the first data line and the fifth transistor M5.

In the first bias sub-stage c (k), the second scan signal on the second scan signal line scan of the kth row is at an on level, the bias block 13 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the bias signal is written into both the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1.

In the first sub-stage of the data writing sub-stage d (k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan of the k+1 th row are both on levels, the data writing module 12 of the k+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is on level, the control signal on the second control signal line mux2, the control signal on the third control signal line mux3 and the control signal on the fourth control signal line mux4 are off level, the first transistor M1 is on, the eighth transistor M8 of the second transistor M2 is off, and the data signal of the first signal source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the k+2 row through the first signal line data1 and the first transistor M1.

In the second sub-stage of the data writing sub-stage d (k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan of the k+1 th row are both on levels, the data writing module 12 of the k+1 th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 are both writing data signals.

In the second sub-stage of the stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the k+2 row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal terminal DVH can be further transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 and the tenth transistor M1 through the fourth signal line data4 and the seventh transistor M7.

In the first bias sub-stage c (k+1), the second scan signal on the second scan signal line scan of the k+1 row is at an on level, the bias block 13 of the k+1 row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G2 are both turned on, and the bias signal is written to both the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2.

In the first sub-stage of the stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both off-level, the control signal on the third control signal line mux3 is on-level, the control signal on the fourth control signal line mux4 is off-level, the third transistor M3 is on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off, and the data signal of the first signal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the k+3rd row through the third signal line data3 and the third transistor M3.

In the second sub-stage of the stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all off-level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the k+3 row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the tenth transistor M10 of the third green pixel circuit G3 through the first signal line data1 and the fifth transistor M5.

And so on.

Illustratively, k may be 1.

In other alternative embodiments, as shown in fig. 21 and 22, the display panel 1000 may include a plurality of rows of pixel circuits 10, and during a display time of one frame, the operation of each row of pixel circuits 10 may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage, after the first bias sub-stage, the data writing sub-stage writes a data signal to the driving module 11 of the pixel circuit 10, and during the first bias sub-stage, the driving module 11 of the pixel circuit 10 writes a bias signal, and the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 may be sequentially on levels;

The data writing sub-stage of the p-th row of pixel circuits 10 may at least partially overlap the first bias sub-stage of the p+1th row of pixel circuits 10, the data writing sub-stages of any two rows of pixel circuits 10 may not overlap, and the first bias sub-stages of any two rows of pixel circuits 10 may not overlap;

wherein p is a positive integer.

In this embodiment, the data writing sub-stage of the p-th row of pixel circuits 10 may at least partially overlap with the first bias sub-stage of the p+1-th row of pixel circuits 10, that is, when the driving module 11 of the p-th row of pixel circuits 10 writes data signals, the driving module 11 of the p+1-th row of pixel circuits 10 writes bias signals, and the data signals and bias signals are transmitted to the same pixel circuits 10 in a time sharing manner through the same signal line, so that the first pole or the second pole of the driving module 11 in the pixel circuits 10 can be periodically reset without adding additional signal lines, which is beneficial to improving the offset and hysteresis phenomena of the characteristics of the driving module 11 after long-term operation, and is also beneficial to the design of pixel arrangement.

Fig. 21 differs from fig. 19 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 19 is before the first biasing sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 20 is after the first biasing sub-stage. The implementation principle corresponding to fig. 21 is similar to that corresponding to fig. 19, and will not be described again here.

Fig. 22 differs from fig. 20 in that the data writing sub-stage of each row of pixel circuits 10 in fig. 20 is before the first biasing sub-stage, whereas the data writing sub-stage of each row of pixel circuits 10 in fig. 22 is after the first biasing sub-stage. The implementation principle corresponding to fig. 22 is similar to that corresponding to fig. 20, and will not be described again here.

In some alternative embodiments, as shown in fig. 23, the operation of each row of the pixel circuits 10 may further include a data holding stage, at least one of the data holding stages may include a second bias sub-stage, in which the driving module 11 of the pixel circuit 10 may write the bias signal, and the first signal terminal source may be in a floating state or used to provide the bias signal.

In this embodiment, the operation of each row of pixel circuits 10 may further include a data holding stage, where the data holding stage may include at least a second bias sub-stage, and in the second bias sub-stage, the driving module 11 of the pixel circuit 10 may write a bias signal, so as to facilitate the low frequency display of the display panel 1000. In addition, when the first signal terminal source is used to provide the bias signal, it is advantageous to prevent the display panel 1000 from shorting.

In order to facilitate distinguishing the bias sub-stages of the different rows of pixel circuits 10, in fig. 23, a second bias sub-stage e (i) corresponds to the i-th row of pixel circuits 10, and a second bias sub-stage e (i+1) corresponds to the i+1th row of pixel circuits 10.

As an example, in the case where the display panel 1000 includes both the first signal terminal source and the second signal terminal DVH, the first signal terminal source may be used to provide the data signal and the second signal terminal DVH may be used to provide the bias signal during the data writing stage. During the data retention phase, the data signal terminal may be in a floating state or used to provide a bias signal.

As another example, in the case where the first signal terminal source of the display panel 1000 may be used to time-divisionally supply the data signal and the bias signal, the first signal terminal source may time-divisionally supply the data signal and the bias signal in the data holding stage, and the first signal terminal source may continuously supply the bias signal in the data holding stage.

In fig. 23, the data writing sub-stage of the same row of pixel circuits 10 in the data writing sub-stage is taken as an example before the first bias sub-stage, but not limited thereto, and in other embodiments, the data writing sub-stage of the same row of pixel circuits 10 in the data writing sub-stage may be after the first bias sub-stage.

In the embodiment of the present application, the values of i, j, n, m, k and p may be equal or unequal, which is not limited herein. For example, i=j=n=m=k=p=100, or i=98, j=99, n=100, m=101, k=102, p=103, or the like.

It should be noted that, in each timing chart provided in the embodiment of the present application, the signal on the third scan signal line scan2 is not shown, and it is understood that, for the pixel circuits 10 in the same row, the off-level duration of the emission control signal line emit should cover the on-level duration of the third scan signal line scan 2. For example, taking fig. 7 as an example, the on level of the third scan signal line scan2 may precede the on level of the first scan signal line scan1, and the off-level duration of the emission control signal line emit should cover the duration of the on level of the first scan signal line scan1, the duration of the on level of the second scan signal line scan, and the duration of the on level of the third scan signal line scan2 for the same row of the pixel circuits 10 in the data writing sub-stage.

Alternatively, as shown in fig. 24, the display panel 1000 may include a display area AA and a non-display area NA at least partially surrounding the display area AA. The non-display area NA may include a first non-display area NA1 and a second non-display area NA2 opposite in the column direction Y, the first non-display area NA1 and the second non-display area NA2 being spaced apart from the display area AA. The first non-display area NA1 may include a binding area BA, which may be used to bind the driving chip.

As one example, the first and second gate circuits 200 and 300 may be disposed at the first non-display area NA1.

As another example, one of the first and second gating circuits 200 and 300 may be located in the first non-display area NA1 and the other may be located in the second non-display area NA2. For example, the first gating circuit 200 may be located in the first non-display area NA1, and the second gating circuit 300 may be located in the second non-display area NA2.

In some alternative embodiments, the first signal terminal source and the second signal terminal DVH may be located at both ends of the pixel circuit column. The signal line connected to the second signal terminal DVH may be located in the non-display area NA of the display panel 1000 or may be located in the display area AA of the display panel 1000. Since the signal line connected to the second signal terminal DVH is larger, it is better to dispose the signal line connected to the second signal terminal DVH in the non-display area NA. For example, as shown in fig. 3 and 4, the first signal terminal source may be located at a lower end of the pixel circuit column, and the second signal terminal DVH may be located at an upper end of the pixel circuit column. In other embodiments, the first signal source may be located at a lower end of the pixel circuit column, and the second signal DVH may be located at an upper end of the pixel circuit column, which is not limited herein.

In other alternative embodiments, the first signal terminal source and the second signal terminal DVH may be both located at the same end of the pixel circuit column. The signal line connected to the second signal terminal DVH may be located in the non-display area NA of the display panel 1000. For example, as shown in fig. 11 and 14, the first signal terminal source and the second signal terminal DVH may be both located at the lower end of the pixel circuit column. In other embodiments, the first signal terminal source and the second signal terminal DVH may be both located at an upper end of the pixel circuit column.

The application also provides a display device comprising the display panel 1000 provided by the application. Referring to fig. 25, fig. 25 is a schematic structural diagram of a display device according to an embodiment of the application. Fig. 25 provides a display device 10000 including a display panel 1000 according to any of the above embodiments of the present application. The embodiment of fig. 25 is only an example of a mobile phone, and the display device 10000 is described, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, which is not particularly limited in the present application. The display device provided by the embodiment of the present application has the beneficial effects of the display panel 1000 provided by the embodiment of the present application, and the specific description of the display panel 1000 with reference to the above embodiments may be referred to, and this embodiment is not repeated here.

These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A display panel, characterized in that it comprises a plurality of pixel circuit arrays, the pixel circuit arrays comprising at least two pixel circuit arrays, one pixel circuit array being connected to two signal lines, each signal line transmitting a data signal and a bias signal to the pixel circuits in the pixel circuit array in a time-division multiplexing manner, and the two pixel circuit arrays of the pixel circuit array being connected to the same first signal terminal and the same second signal terminal, the first signal terminal being used to provide the data signal, and the second signal terminal being used to provide the bias signal;

The display panel further includes a first gating circuit and a second gating circuit, and the at least two pixel circuit columns include a first pixel circuit column and a second pixel circuit column;

The two signal lines connected to the first pixel circuit column are connected to the first signal terminal through the first gating circuit, and the two signal lines connected to the first pixel circuit column are connected to the second signal terminal through the second gating circuit.

The two signal lines connected to the second pixel circuit column are connected to the first signal terminal through the first gating circuit, and the two signal lines connected to the second pixel circuit column are connected to the second signal terminal through the second gating circuit.

The first gating circuit is used to transmit the data signal provided by the first signal terminal to the four signal lines of the pixel circuit array in a time-division manner, and the second gating circuit is used to transmit the bias signal provided by the second signal terminal to the four signal lines of the pixel circuit array in a time-division manner.

The first pixel circuit column is connected to two signal lines, including a first signal line and a third signal line; the second pixel circuit column is connected to two signal lines, including a second signal line and a fourth signal line.

The first gating circuit includes a first switching element, a second switching element, a third switching element, and a fourth switching element. The first end of the first switching element, the first end of the second switching element, the first end of the third switching element, and the first end of the fourth switching element are all connected to the first signal terminal. The second end of the first switching element is connected to the first signal line. The second end of the third switching element is connected to the third signal line. The second end of the fourth switching element is connected to the fourth signal line. The second end of the second switching element is connected to the second signal line.

The second gating circuit includes a fifth switching element, a sixth switching element, a seventh switching element, and an eighth switching element. The first ends of the fifth switching element, the sixth switching element, the seventh switching element, and the eighth switching element are all connected to the second signal terminal. The second end of the fifth switching element is connected to the first signal line. The second end of the sixth switching element is connected to the third signal line. The second end of the seventh switching element is connected to the fourth signal line. The second end of the eighth switching element is connected to the second signal line.

The first switching element is turned on or off under the control of the first control signal line; the second and seventh switching elements are turned on or off under the control of the second control signal line; the third switching element is turned on or off under the control of the third control signal line; and the fourth and eighth switching elements are turned on or off under the control of the fourth control signal line.

The sixth switching element is turned on or off under the control of the first control signal line, and the fifth switching element is turned on or off under the control of the third control signal line.

or,

The sixth switching element is turned on or off under the control of the second control signal line, and the fifth switching element is turned on or off under the control of the fourth control signal line.

2. The display panel according to claim 1, characterized in that,

Each pixel circuit in the first pixel circuit column is connected to both the first signal line and the third signal line.

Each pixel circuit in the second pixel circuit column is connected to both the second signal line and the fourth signal line.

3. The display panel according to claim 2, wherein the pixel circuit comprises a driving module, a data writing module, and a bias module, the data writing module being used to transmit the data signal to the driving module, and the bias module being used to transmit the bias signal to the driving module;

The data writing module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the first signal line, and the bias module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the third signal line.

The data writing module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the third signal line, and the bias module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the first signal line.

The data writing module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the second signal line, and the bias module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the fourth signal line;

The data writing module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the fourth signal line, and the bias module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the second signal line.

4. The display panel according to claim 3, characterized in that the display panel includes multiple rows of pixel circuits, and the working process of each row of pixel circuits includes a data writing stage during the display time of one frame. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage occurs before the first bias sub-stage. During the data writing sub-stage, the driving module of the pixel circuit writes the data signal. During the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on-level.

The data writing sub-stage of the pixel circuit in the (i+2)th row overlaps at least partially with the first bias sub-stage of the pixel circuit in the ith row, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit.

Where i is a positive integer.

5. The display panel according to claim 3, characterized in that the display panel includes multiple rows of pixel circuits, and the working process of each row of pixel circuits includes a data writing stage during the display time of one frame. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is after the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level.

The data writing sub-stage of the pixel circuit in row j overlaps at least partially with the first bias sub-stage of the pixel circuit in row j+2, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit.

Where j is a positive integer.

6. The display panel according to claim 1, characterized in that,

In the first pixel circuit column, the pixel circuits in the odd-numbered rows are connected to the first signal line, and the pixel circuits in the even-numbered rows are connected to the third signal line.

The pixel circuits in the odd-numbered rows of the second pixel circuit column are connected to the second signal line, and the pixel circuits in the even-numbered rows of the second pixel circuit column are connected to the fourth signal line.

7. The display panel according to claim 6, wherein the pixel circuit comprises a driving module, a data writing module, and a bias module, the data writing module being used to transmit the data signal to the driving module, the bias module being used to transmit the bias signal to the driving module, and the data signal and the bias signal being the same;

In the first pixel circuit column, the data writing module and the bias module of the pixel circuit in the odd-numbered rows are respectively connected to the first signal line, and the data writing module and the bias module of the pixel circuit in the even-numbered rows are respectively connected to the third signal line.

In the second pixel circuit column, the data writing module and the bias module of the pixel circuit in the odd-numbered rows are respectively connected to the second signal line, and the data writing module and the bias module of the pixel circuit in the even-numbered rows are respectively connected to the fourth signal line.

8. The display panel according to claim 7, characterized in that the display panel includes multiple rows of pixel circuits, and the working process of each row of pixel circuits includes a data writing stage during the display time of one frame. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage occurs before the first bias sub-stage. During the data writing sub-stage, the driving module of the pixel circuit writes the data signal. During the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on-level.

The data writing sub-stage of the pixel circuit in row (n+1) overlaps at least partially with the first bias sub-stage of the pixel circuit in row (n). The data writing sub-stages of any two rows of pixel circuits do not overlap, and the first bias sub-stages of any two rows of pixel circuits do not overlap.

Where n is a positive integer.

9. The display panel according to claim 7, wherein the display panel comprises a multi-row pixel circuit;

During the display time of one frame, the operation of each row of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage follows the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level.

The data writing sub-stage of the pixel circuit in row m overlaps at least partially with the first bias sub-stage of the pixel circuit in row m+1, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit.

Where m is a positive integer.

10. The display panel according to claim 7, wherein the pixel circuit comprises a driving module and a data writing module, the data writing module being used to transmit the data signal and the bias signal to the driving module in a time-division multiplexing manner;

The data writing module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the first signal line, and the data writing module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the third signal line.

The data writing module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the second signal line, and the data writing module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the fourth signal line.

11. The display panel according to claim 10, characterized in that the display panel includes multiple rows of pixel circuits, and the working process of each row of pixel circuits includes a data writing stage during the display time of one frame. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage occurs before the first bias sub-stage. During the data writing sub-stage, the driving module of the pixel circuit writes the data signal. During the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level.

The data writing sub-stage of the pixel circuit in row (k+1) at least partially overlaps with the first bias sub-stage of the pixel circuit in row (k), the data writing sub-stages of any two rows of pixel circuits do not overlap, and the first bias sub-stages of any two rows of pixel circuits do not overlap; where k is a positive integer.

12. The display panel according to claim 10, characterized in that the display panel includes multiple rows of pixel circuits, and the working process of each row of pixel circuits includes a data writing stage during the display time of one frame. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage occurs after the first bias sub-stage. During the data writing sub-stage, the driving module of the pixel circuit writes the data signal. During the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on-level.

The data writing sub-stage of the pixel circuit in row p overlaps at least partially with the first bias sub-stage of the pixel circuit in row p+1, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit.

Where p is a positive integer.

13. The display panel according to claim 4, 5, 8, 9, 11, or 12, wherein at least one of the data holding stages includes a second bias sub-stage, in which the driving module of the pixel circuit writes the bias signal, and the first signal terminal is in a floating state or used to provide the bias signal.

14. A display device comprising a display panel according to any one of claims 1 to 13.