CN116627894A - A medium access control layer, communication method and system - Google Patents

Abstract

The application relates to a medium access control layer, a communication method and a system, wherein the medium access control layer comprises the following components: a data link protocol bridge module for establishing a logical data link between the on-chip communication interface and the inter-chip communication interface; the medium access controller module is used for encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface and transmitting the frame data to the inter-chip communication interface; and the configuration module is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface. The application solves the problem that the medium access control layer cannot be compatible with various chip communication interfaces with different specifications on the market, and cannot be reused.

Description

A medium access control layer, communication method and system

technical field

The present application relates to the technical field of integrated circuits, in particular to a medium access control layer, a communication method and a system.

Background technique

In order to deal with the problem of large chip manufacturing, Chiplet technology came into being. Chiplet, also known as "small chip" or "core particle", is a functional circuit block. Chiplet technology divides the chip into smaller functional blocks for manufacturing, and then realizes the interconnection between functional blocks through the Chiplet interface protocol and advanced packaging technology, thereby avoiding the manufacturability problem of large chips and reducing the number of application-specific integrated circuits (ASICs). Specific Integrated Circuit, ASIC) design problems of high cost and long construction period. Chiplet technology has become a hot technology.

In addition, many-core architectures have become more and more widely used in recent years. The core of many-core design is to fully develop on-chip high-performance computing power, which is also an inevitable development trend of high-performance computing. Today's many-core processors contain a large number of independent cores and tightly coupled memory, which are interconnected by a high-speed Network on Chip (NoC) infrastructure. From the perspective of Open System Interconnect (OSI), the inter-chip interface protocol belongs to the physical layer protocol, while the internal communication network of the chip belongs to the network layer components. The two layers require data in the model. Link layer as an intermediary, such a component needs to provide a media access control layer (MediaAccessControl, MAC).

MAC belongs to a sublayer in the data link layer in OSI, but it has the characteristics of coupling with the physical layer. Different physical media correspond to completely different MAC protocols and circuit module designs. Existing MAC modules used in other scenarios (such as Ethernet MAC defined by IEEE-802. 3) can hardly be directly used in inter-chip communication scenarios. At the same time, there are various inter-chip communication interfaces with different specifications on the market. The bit width, communication rate and clock frequency of these interfaces are very different, and these communication interfaces located around the chip are generally in the same position as the internal circuits of the chip. For different clock domains, the currently provided media access control layer cannot be compatible with various inter-chip communication interfaces of different specifications on the market, and the media access control layer cannot be reused.

In the related technology, the medium access control layer is not compatible with various inter-chip communication interfaces of different specifications on the market, resulting in the problem of inability to be reused, and no effective solution has been proposed yet.

Contents of the invention

Based on this, it is necessary to provide a media access control layer, a communication method and a system for the above technical problems.

In the first aspect, the embodiment of the present application provides a media access control layer, the media access control layer is connected between the on-chip communication interface and the inter-chip communication interface of the chip, and the media access control layer includes:

A data link protocol bridge module, configured to establish a logical data link between the on-chip communication interface and the inter-chip communication interface;

A media access controller module connected to the data link protocol bridge module, configured to receive the on-chip communication interface data transmitted by the data link protocol bridge module, and encode the on-chip communication interface data into the inter-chip Frame data corresponding to the specification of the communication interface, and transmitting the frame data to the inter-chip communication interface;

A configuration module connected to the data link protocol bridge module is used to receive and parse the configuration packet transmitted by the data link protocol bridge module to configure the inter-chip communication interface.

In one of the embodiments, the media access controller module includes a first frame encoder, configured to encode the on-chip communication interface data into the Frame data corresponding to the specification of the inter-chip communication interface.

In one of the embodiments, the media access controller module further includes a first arbiter, configured to select the subnet priority corresponding to the on-chip communication interface data and the data link corresponding to the on-chip communication interface data. The priority of the protocol bridge module arbitrates the data of the on-chip communication interface.

In one of the embodiments, the data link protocol bridge module includes:

A first data processing module, configured to receive and process the on-chip communication interface data, and transmit the processed on-chip communication interface data to the media access controller module;

The second arbiter is configured to arbitrate the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data holds downstream credits and the subnet priority corresponding to the on-chip communication interface data.

In one of the embodiments, the data processing module includes:

The first memory is used to store the on-chip communication interface data;

a multiplexer, configured to output corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter;

The second frame encoder is configured to encode the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface.

In one of the embodiments, the data link protocol bridge module further includes a second data processing module, configured to receive and process the inter-chip communication interface data transmitted by the media access controller module, and process the processed The inter-chip communication interface data is transmitted to the on-chip communication interface.

In one of the embodiments, the second data processing module includes: a frame decoder, a demultiplexer, a second memory, the frame decoder, an inter-chip for transmitting the media access controller module The communication interface data is decoded; the demultiplexer is configured to input the inter-chip communication interface data into the second memory for storage according to the source of the inter-chip interface data.

In the second aspect, the embodiment of the present application also provides a medium access control layer-based communication method, the method including:

receiving the on-chip communication interface data transmitted by the data link protocol bridge module;

Encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface;

transmitting the frame data to the inter-chip communication interface.

In one embodiment, the method also includes:

receiving the inter-chip communication interface data transmitted by the media access control module;

The inter-chip communication interface data is decoded and transmitted to the on-chip communication interface according to the source corresponding to the inter-chip communication interface data.

In a third aspect, the embodiment of the present application further provides an inter-chip communication system, including a first media access control layer and a second media access control layer, the first media access control layer and the second media access control layer A communication connection: the first media access control layer and/or the second media access control layer implements the method described in the second aspect above.

The above media access control layer, communication method and system are used to establish a logical data link between the intra-chip communication interface and the inter-chip communication interface through the data link protocol bridge module; and the data link protocol The media access controller module connected to the bridge module is used to receive the on-chip communication interface data transmitted by the data link protocol bridge module, and encode the on-chip communication interface data into the specification corresponding to the inter-chip communication interface. frame data, and transmit the frame data to the inter-chip communication interface; the configuration module connected to the data link protocol bridge module is used to receive and analyze the configuration packet transmitted by the data link protocol bridge module, to configure the inter-chip communication interface. It solves the problem that the media access control layer cannot be compatible with various inter-chip communication interfaces of different specifications on the market, resulting in the problem that the media access control layer cannot be reused.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below, so as to make other features, objects, and advantages of the application more comprehensible.

Description of drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the attached picture:

FIG. 1 is a structural diagram of a media access control layer according to an embodiment of the present application;

FIG. 2 is a structural diagram of a media access control layer according to another embodiment of the present application;

FIG. 3 is a structural diagram of a media access controller module according to an embodiment of the present application;

4 is a schematic diagram of a frame format corresponding to an inter-chip communication interface according to an embodiment of the present application;

FIG. 5 is a structural diagram of a media access controller module according to another embodiment of the present application;

6 is a structural diagram of a data link protocol bridge module according to an embodiment of the present application;

FIG. 7 is a structural diagram of a first data processing module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a frame format corresponding to an intra-chip communication interface according to an embodiment of the present application;

FIG. 9 is a structural diagram of a data link protocol bridge according to an embodiment of the present application;

FIG. 10 is a schematic flowchart of a communication method based on a media access control layer according to an embodiment of the present application;

FIG. 11 is a structural diagram of an inter-chip communication system according to an embodiment of the present application.

Among them, 11. Data link protocol bridge module; 12. Media access controller module; 13. Configuration module; 1110, Data link protocol bridge; 1210, First frame encoder; 1220, First arbiter; 21, The first A data processing module; 22, a second arbiter; 31, a first memory; 32, a multiplexer; 33, a second frame encoder; 23, a second data processing module; 34, a frame decoder; 35, demultiplexing 36, the second memory; 51, the first media access control layer; 52, the second media access control layer.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application, and those skilled in the art can also apply the present application to other similar scenarios. In addition, it can also be understood that although such development efforts may be complex and lengthy, for those of ordinary skill in the art relevant to the content disclosed in this application, the technology disclosed in this application Some design, manufacturing or production changes based on the content are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

Reference in this application to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

Unless otherwise defined, the technical terms or scientific terms involved in the application shall have the usual meanings understood by those with ordinary skill in the technical field to which the application belongs. Words such as "a", "an", "an" and "the" involved in this application do not indicate a limitation on quantity, and may indicate singular or plural numbers. The terms "comprising", "comprising", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or process that includes a series of steps or modules (units). The apparatus is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to the process, method, product or apparatus. The words "connected", "connected", "coupled" and similar words mentioned in this application are not limited to physical or mechanical connection, but may include electrical connection, no matter it is direct or indirect. The "plurality" involved in this application refers to two or more than two. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships. For example, "A and/or B" may indicate: A exists alone, A and B exist simultaneously, and B exists independently. The character "/" generally indicates that the contextual objects are an "or" relationship. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects, and do not represent a specific ordering of objects.

This embodiment provides a media access control layer. As shown in FIG. 1, the media access control layer is connected between the on-chip communication interface and the inter-chip communication interface of the chip, and the media access control layer includes:

A data link protocol bridge module 11, configured to establish a logical data link between the on-chip communication interface and the inter-chip communication interface;

The media access controller module 12 connected with the data link protocol bridge module 11 is used to receive the on-chip communication interface data transmitted by the data link protocol bridge module 11, and encode the on-chip communication interface data into the frame data corresponding to the specifications of the inter-chip communication interface, and transmit the frame data to the inter-chip communication interface;

The configuration module 13 connected to the data link protocol bridge module 11 is configured to receive and parse the configuration packet transmitted by the data link protocol bridge module 11 to configure the inter-chip communication interface.

The data link protocol bridge module 11, as shown in Figure 2, bridges two kinds of data link protocols, one is an on-chip link protocol for interconnecting with on-chip components, and the other is one side MAC to another The data link protocol of the MAC on one side. In the OSI model, the Chiplet inter-chip communication interface belongs to the physical layer, and the media access controller module 12 belongs to the media access control sublayer of the data link protocol bridge module 11, and the logical link control sublayer of the data link protocol bridge module 11 The layer is implemented by the data link protocol bridge 1110 to establish a logical link from the MAC on one side to the MAC on the other side.

The on-chip link protocol uses the credit-based flow control method commonly used in the NoC field. Credit-based flow control is an effective way to realize the flow control of each virtual circuit in each link. Before sending data through the connection, the sender needs to receive The credit value sent by the receiving end through the virtual circuit. In different periods, the receiving end sends the credit amount to the sending end, indicating the buffer size available at the receiving end. When the credit amount is received, the sending end sends data to the receiving end according to the credit amount. Each time the sending end sends data, the corresponding credit amount decreases, which can effectively reduce network congestion caused by failed retransmissions. As shown in Table 1, a set of on-chip communication interfaces has the following signals:

Among them, the data_in, valid_in, and credit_in signals are used for the data and related flow control received by the MAC from the on-chip communication interface; the data_out, valid_out, and credit_out signals are used for the data and related flow control sent by the MAC to the on-chip communication interface. For each intra-chip link protocol marked in FIG. 2, there may be more than one set of the above-mentioned interfaces, wherein each set of interfaces is used to serve a physical subnet or an abstract priority. In this embodiment, the bit width N of each group of data lines (in a single direction) on the on-chip link protocol side is set to 128.

In order to enable the inter-chip communication interface to be used in various occasions and improve the flexibility of the interface design, configurable options are added to the interface, and the interface is configured according to the design requirements before it works normally. The entire configuration process is divided into two steps. The first step is to analyze the configuration package transmitted from the chip, and the second step is to configure the registers according to the resolved configuration address and configuration data.

The configuration package in this embodiment has a proprietary format, as shown in Table 2. The configuration package consists of several consecutive flits, and the bit width of each flit is 128 bits. The first flit is the packet header of the data packet, through which the value of msgtype can confirm that this data packet is a configuration packet.

Configuration module 13 by reading the data of data link protocol bridge module 11 and judging that it is currently a configuration packet, the whole MAC circuit is transferred to the configuration state, the current data of data link protocol bridge module 11 and several pieces of data thereafter (by the first The value of packetSize in a flit identifies the quantity) flows into the configuration module instead of flowing through the media access controller module 12 as in the normal mode.

For the first two flits of the configuration package, the configuration module extracts haddr, adX and dataX signals (X is 0, 1, 2, 3, and the number of times is identified by size). The complete address is obtained by splicing haddr and adX, so as to obtain the information required for one write: (register address _X, register data _X). This type of data can be written through any commonly used configuration interface. The specific interface used depends on the configuration interface provided by the chiplet inter-chip communication interface. For each subsequent flit, a maximum of 3 pieces of configuration information can be loaded, and the processing method is the same as the above method. After the configuration process is completed, the MAC returns to the normal state for data transmission. The configuration module in this embodiment is a state machine circuit.

In this embodiment, a data link protocol bridge module is used to establish a logical data link between the on-chip communication interface and the inter-chip communication interface; a media access controller connected to the data link protocol bridge module A module, configured to receive the on-chip communication interface data transmitted by the data link protocol bridge module, encode the on-chip communication interface data into frame data corresponding to the specifications of the inter-chip communication interface, and encode the frame data into The data is transmitted to the inter-chip communication interface; the configuration module connected to the data link protocol bridge module is used to receive and analyze the configuration packet transmitted by the data link protocol bridge module to configure the inter-chip communication interface . It solves the problem that the media access control layer cannot be compatible with various inter-chip communication interfaces of different specifications on the market, resulting in the problem that the media access control layer cannot be reused.

In one embodiment, as shown in FIG. 3 , the media access controller module 12 includes a first frame encoder 1210, configured to convert the slices to The internal communication interface data is encoded as frame data corresponding to the specification of the inter-chip communication interface.

The inter-chip transmission bandwidth provided by the inter-chip communication interface under different specifications is always the same, but due to various reasons such as process limitations, the interfaces provided to the chip have different clock frequencies and bit widths. In this embodiment, the chip The bit width of each group of data lines (in a single direction) on the inner link protocol side is 128. The number of subnets supported by the MAC is 2, and the inter-chip communication interface corresponds to the following three specifications:

(1) 4X specification

The MAC module 12 under this specification is designed for large bit width and low clock frequency. The bit width provided by the inter-chip communication interface is 640 bits. MAC regards this bit width as four groups of 160-bit data bits. Each group of 160 bits can accommodate 128-bit wide data and some additional data from the on-chip interface.

(2) 2X specification

The bit width provided by the inter-chip communication interface under this specification is 320 bits. MAC regards this bit width as two sets of 160-bit data bit width. Each set of 160 bits can accommodate 128-bit wide data from the on-chip interface and some Additional data. The clock frequency is twice that of the 4X specification.

(3) 1X specification

Media access controllers under this specification are designed for small bit width and high clock frequency. The inter-chip communication interface provides a bit width of 160 bits. MAC regards this bit width as a set of 160-bit data bit width, which can only accommodate a 128-bit data and several additional information. The clock frequency is four times that of the 4X specification.

The data bit width provided under different specifications is different. The bit width of the 1X specification is 160 bits. The frame format is shown in Figure 4. The sel bit indicates which subnet route the data comes from, the val bit indicates whether the data segment data is valid, and the dat bit indicates the transmission In the data segment, QID identifies which data link protocol bridge 1110 the arbitrated data comes from, and yms identifies flow control information. For the frames encoded by the 2X specification and the 4X specification, they have 320 bits and 640 bits respectively, of which 319~160 bits, 639~480 bits, and 479~320 bits are defined to be consistent with the lower 160 bits, but there is no need to fill in any stream Control information (the position of offset 23~16 in the segment is 0).

In one of the embodiments, as shown in FIG. 5 , the media access controller module 12 further includes a first arbiter 1220, configured to use the subnet priority corresponding to the on-chip communication interface data and the on-chip The priority of the data link protocol bridge module corresponding to the communication interface data arbitrates the on-chip communication interface data. The first arbiter 1220 is responsible for arbitrating the data to be arbitrated from the data link protocol bridge 1110 . For each group of data interfaces to be arbitrated, as shown in Table 3, there are the following signals:

The first arbitrator 1220 in the media access controller module 12 has the following arbitration rules: for the data to be arbitrated from the data link protocol bridge module 11, the arbitration is preferentially performed according to the subnet priority corresponding to the on-chip communication interface data, and the arbitration The rule is that the priority of the response subnet is always higher than that of the request subnet. For data to be arbitrated with the same priority, the priority of the data link protocol bridge module 11 corresponding to the on-chip communication interface data is used, specifically the data link protocol bridge 1110 priority for arbitration. For example, in this embodiment, the data link protocol bridge module 11 has four data link protocol bridges 1110, the corresponding IDs are 0, 1, 2, and 3, and the fixed priorities can be 0, 1, and 2 from high to low. , 3.

According to the specifications corresponding to the inter-chip communication interface, four data link protocol bridges 1110 are taken as an example in the embodiment, and the first arbiter 1220 performs the following arbitration: For the 4X specification, no arbitration is required, and the data of the four data link protocol bridges 1110 are all used as output data; for 2X specification, the first arbiter 1220 arbitrates two data from the four data link protocol bridges 1110 as output data; One of the data of the bridge 1110 is arbitrated as the output data.

For chips with many-core architecture, NoC is often used as the on-chip interconnection system. In some cases, in order to avoid protocol-level deadlocks, different NoC physical subnets are often configured according to the different stages of the upper-layer protocol transactions carried by the NoC. These physical NoC subnets are generally identical in topology and routing aspects, but carry different packets. For example, it is divided into a request subnet and a response subnet, which only transmit request packets and response packets respectively. In this way, different priorities are physically separated and deadlocks are avoided.

The media access control layer in this embodiment supports multiple physical subnets with different priorities inside the chip to communicate using the inter-chip communication interface, and ensures that multiple physical subnets share the same Chiplet inter-chip interface at the same time. The priority relationship between physical subnets is maintained, so that the nature of deadlock avoidance is extended to the entire chip interconnection system through the media access control layer.

In one of the embodiments, as shown in FIG. 6, the data link protocol bridge module 11 includes:

The first data processing module 21 is configured to receive and process the on-chip communication interface data, and transmit the processed on-chip communication interface data to the media access controller module 12;

The second arbiter 22 is configured to arbitrate the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data holds downstream credits and the subnet priority corresponding to the on-chip communication interface data .

After the first data processing module 21 receives data from the chip, the data makes a request to the second arbiter 22, and the arbitrator decides whether the data is qualified to send according to whether the subnet corresponding to the data holds downstream credit. The credit sent by the MAC on one side and received by the MAC on this side obtains the arbitration result from all the data with sending request and sending qualification according to the subnet priority, and the first data processing module 21 processes and transmits the data according to the arbitration result to the media access controller module 12.

In one of the embodiments, as shown in FIG. 7, the first data processing module 21 includes:

The first memory 31 is used to store the on-chip communication interface data;

A multiplexer 32, configured to output corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter 22;

The second frame encoder 33 is configured to encode the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface.

The first memory 31 in this embodiment is FIFO (First In First Out), and FIFO is a first-in-first-out data buffer. Adjacent to the on-chip interface, FIFO is used to temporarily store interface data for flow control. And divide the on-chip clock domain and the MAC clock domain. After the data received from the chip is stored in the memory, the second arbiter 22 performs arbitration to determine which FIFO the data stored in can pass through. Each non-empty FIFO can submit a request to the arbiter, and the second arbiter 22 determines whether the FIFO has the sending qualification according to whether the subnet corresponding to the FIFO holds downstream credit. The multiplexer 32 is configured to output corresponding data according to the arbitration result obtained by the second arbiter 22 .

The second frame encoder 33 encodes the output data into a data link frame corresponding to the specification of the inter-chip communication interface, which is used to carry 128-bit data and additional information from the chip as an example. The frame format is as shown in FIG. 8 Show.

Among them, the subnet bit identifies which physical NoC subnet the data comes from, the vaild bit indicates whether the data segment is valid, the dat bit indicates the transmission data segment, and ym1 and ym0 are the flow control credits that need to be transmitted to the peer MAC (referred to as credit_in or credit_out signal line) signal. In the transmission between the data link protocol bridge 1110 and the media access controller module 12, regardless of input and output, the frame format is the same.

The data link protocol bridge module 11 also includes a second data processing module 23, configured to receive and process the inter-chip communication interface data transmitted by the media access controller module, and process the inter-chip communication interface data transmitted to the on-chip communication interface. FIG. 9 shows the structure of the data link protocol bridge 1110 in the case that there are two physical NoC subnets in the chip. Solid lines indicate data flow, and dashed lines indicate control flow. The second data processing module 23 includes a frame decoder 34, a demultiplexer 35, and a second memory 36. The frame decoder 34 is used to decode and demultiplex the inter-chip communication interface data transmitted by the media access controller module 12. The device 35 is used to store the data in the second memory 36 according to the source of the data, and the second memory in this embodiment is also a FIFO.

The embodiment of the present application also provides a communication method based on the media access control layer, as shown in FIG. 10 , the method includes the following steps:

Step S401, receiving the on-chip communication interface data transmitted by the data link protocol bridge module;

Step S402, encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface;

Step S403, transmitting the frame data to the inter-chip communication interface.

In this embodiment, by receiving the on-chip communication interface data transmitted by the data link protocol bridge module; encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface; encoding the frame Data is transmitted to the inter-chip communication interface. It solves the problem that the media access control layer cannot be compatible with various inter-chip communication interfaces of different specifications on the market, resulting in the problem that the media access control layer cannot be reused.

In one embodiment, the method also includes the following steps:

Step 1, receiving the inter-chip communication interface data transmitted by the media access control module;

Step 2, decoding the inter-chip communication interface data and transmitting it to the on-chip communication interface according to the source corresponding to the inter-chip communication interface data.

The embodiment of the present application also provides an inter-chip communication system, as shown in FIG. 11 , the system includes a first media access control layer 51 and a second media access control layer 52, and the first media access control layer 51 and The second media access control layer 52 is connected in communication; the first media access control layer 51 and/or the second media access control layer 52 implement the communication method based on the above media access control layer.

When the entire system is powered on and reset, the first media access control layer 51 and the second media access control layer 52 need to receive configuration data packets from the chip, configure the inter-chip communication interface accordingly, and wait for the inter-chip communication interface to be established and communicate with the opposite chip. The connection between the communication interfaces can then be put into normal use. After the configuration phase is completed, it enters the normal phase, where cross-chip communication can be performed. The following uses specific examples to illustrate the data transmission process on the entire data path.

First, the data from the chip is transmitted to the first medium access control layer 51 on-chip interface protocol, and through the inter-chip communication interface, the data is received and written into the FIFO corresponding to the subnet of the data link bridge. Once data is stored in the FIFO, a request can be made to the second arbiter 22, and the second arbiter 22 obtains an arbitration result from all FIFOs that have the sending request and sending qualification according to the priority of the subnetwork. Then construct a data link frame according to the data of the winning requester in this step of arbitration, and submit an arbitration request to the media access controller module 12 to compete with requests from other data link bridges. The media access controller module 12 selects different data according to different specifications, constructs a new data frame, and sends it to the inter-chip communication interface. The inter-chip communication interface transmits the data to the corresponding inter-chip communication interface of the opposite second media access control layer 52 and submits the data to the second media access control layer 52 for processing.

The second medium access control layer 52 regards each 160-bit bit width of the received data as a part and processes them respectively. And take out all flow control signals in the lowest 160 bits of data. The second media access control layer 52 assigns the data to the corresponding data link bridge according to the QID number in the data segment. Flow control signals are also dispatched to the data link bridge.

After receiving the data frame, each data link bridge assigns it to the corresponding subnet FIFO according to the subnet number (subnet number or sel number) in the data frame. Then the data is delivered to the on-chip components through the on-chip interface protocol. The above is the process of completing an end-to-end transmission.

The chip-to-chip communication system in this embodiment, through the first media access control layer 51 and the second media access control layer 52, can realize the chip-to-chip communication system specially used in the chip-to-chip communication scenario, and solve the problem of medium access The control layer cannot be compatible with various inter-chip communication interfaces of different specifications on the market, resulting in the problem that the media access control layer cannot be reused.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only represent several implementation modes of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims (10)

1. A media access control layer, the media access control layer is connected between the intra-chip communication interface and the inter-chip communication interface of the chip, it is characterized in that the media access control layer includes: A data link protocol bridge module, configured to establish a logical data link between the on-chip communication interface and the inter-chip communication interface; A media access controller module connected to the data link protocol bridge module, configured to receive the on-chip communication interface data transmitted by the data link protocol bridge module, and encode the on-chip communication interface data into the inter-chip Frame data corresponding to the specification of the communication interface, and transmitting the frame data to the inter-chip communication interface; A configuration module connected to the data link protocol bridge module is used to receive and parse the configuration packet transmitted by the data link protocol bridge module to configure the inter-chip communication interface. 2. The media access control layer according to claim 1, wherein the media access controller module includes a first frame encoder, configured to convert the bit width and clock frequency corresponding to the inter-chip communication interface to The intra-chip communication interface data is encoded as frame data corresponding to the specification of the inter-chip communication interface. 3. The medium access control layer according to claim 1, wherein the medium access controller module further comprises a first arbiter, which is used for according to the subnet priority corresponding to the on-chip communication interface data and the Arbitrate the on-chip communication interface data according to the priority of the data link protocol bridge module corresponding to the on-chip communication interface data. 4. The medium access control layer according to claim 2, wherein the data link protocol bridge module comprises: A first data processing module, configured to receive and process the on-chip communication interface data, and transmit the processed on-chip communication interface data to the media access controller module; The second arbiter is configured to arbitrate the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data holds downstream credits and the subnet priority corresponding to the on-chip communication interface data. 5. The medium access control layer according to claim 4, wherein the first data processing module comprises: The first memory is used to store the on-chip communication interface data; a multiplexer, configured to output corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter; The second frame encoder is configured to encode the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface. 6. The media access control layer according to claim 4, wherein the data link protocol bridge module further includes a second data processing module, configured to receive and process the inter-chip data transmitted by the media access controller module. communication interface data, and transmit the processed inter-chip communication interface data to the on-chip communication interface. 7. The medium access control layer according to claim 6, wherein the second data processing module comprises: a frame decoder, a demultiplexer and a second memory, The frame decoder is configured to decode the inter-chip communication interface data transmitted by the media access controller module; The demultiplexer is configured to input the inter-chip communication interface data into the second memory for storage according to the source of the inter-chip communication interface data. 8. A communication method based on a media access control layer, characterized in that the method comprises: Receive the on-chip communication interface data transmitted by the data link protocol bridge module; Encoding the on-chip communication interface data into frame data corresponding to the specifications of the inter-chip communication interface; transmitting the frame data to the inter-chip communication interface. 9. The communication method based on the media access control layer according to claim 8, wherein the method further comprises: receiving inter-chip communication interface data transmitted by the media access controller module; The inter-chip communication interface data is decoded and transmitted to the on-chip communication interface according to the source corresponding to the inter-chip communication interface data. 10. An inter-chip communication system, characterized by comprising a first media access control layer and a second media access control layer, the first media access control layer is communicatively connected to the second media access control layer; The first media access control layer and/or the second media access control layer implements the method as claimed in claim 8 .