CN116613152A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The invention discloses a semiconductor device, comprising: a semiconductor component; and a silicon-based passive component stacked on the semiconductor component along the thickness direction of the semiconductor component. In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

Description

Semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a power supply system.

Background technique

Conventional semiconductor devices include MLCC (Multi-layer Ceramic Capacitor, multilayer ceramic capacitor) and chips. MLCCs have a single capacitor structure comprising two electrodes. Generally, a chip and an MLCC are arranged side by side on a substrate, and such a configuration results in a larger size of the semiconductor device.

Contents of the invention

In view of this, the present invention provides a semiconductor device to solve the above problems.

According to a first aspect of the present invention, a semiconductor device for powering an electronic device is disclosed, comprising:

semiconductor components; and

A silicon-based passive component is stacked on the semiconductor component along the thickness direction of the semiconductor component.

According to a third aspect of the present invention, a semiconductor device is disclosed, comprising:

semiconductor components; and

The silicon-based passive component is stacked on the semiconductor component and includes a plurality of passive structures.

The semiconductor device of the present invention includes: a semiconductor component; and a silicon-based passive component, which are stacked on the semiconductor component along the thickness direction of the semiconductor component. In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

Description of drawings

FIG. 1A is a schematic top view of a semiconductor device according to an embodiment of the present invention;

1B is a schematic cross-sectional view of a semiconductor device in the direction 1B-1B';

2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

6 shows a schematic diagram of a cross-sectional view of a semiconductor device according to another embodiment;

7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

8 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

9 is a schematic cross-sectional view of a silicon-based passive component according to another embodiment of the present invention;

10 is a schematic cross-sectional view of a silicon-based passive component according to another embodiment of the present invention;

11 is a schematic cross-sectional view of a silicon-based passive component according to another embodiment of the present invention;

12 is a schematic cross-sectional view of a silicon-based passive component according to another embodiment of the present invention;

13 shows a schematic diagram of a cross-sectional view of a semiconductor device according to another embodiment;

14 shows a schematic diagram of a cross-sectional view of a semiconductor device according to another embodiment;

FIG. 15 is a schematic cross-sectional view of a semiconductor device according to another embodiment of this embodiment;

FIG. 16 shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present embodiment; and

FIG. 17 shows a schematic cross-sectional view of a semiconductor device according to another embodiment of this embodiment.

Detailed ways

In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustrations certain preferred embodiments in which the invention may be practiced . These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and other modifications may be made without departing from the spirit and scope of the invention. and program changes. this invention. Therefore, the following detailed description should not be taken as limiting, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that although the terms "first", "second", "third", "primary", "secondary", etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a second or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.

In addition, for the convenience of description, terms such as "below", "under", "below", "above", "below" may be used herein Spatially relative terms such as "on" are used to describe the relationship of a component or feature to it. Another component or feature as shown. The spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean ± 20% of the stated value, or ± 10% of the stated value, or ± 5% of the stated value, or ± 3% of the stated value , or ±2% of the specified value, or ±1% of the specified value, or within the range of ±0.5% of the specified value. The specified values in the present invention are approximate values. When not specifically stated, the stated value includes the meanings of "about", "approximately" and "approximately". The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a", "an" and "the" are also intended to include the plural unless the context clearly dictates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

It will be understood that when a “component” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent” to another component or layer, it can be directly on the other component or layer. on, connected to, coupled to, or adjacent to, or intervening components or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.

Note: (i) like features will be represented by like reference numerals throughout the drawings and will not necessarily be described in detail in every drawing in which they appear, and (ii) a series of drawings may show a single item , each of which is associated with various reference labels that may appear throughout the sequence, or may appear only in selected figures of the sequence.

In the following embodiments, the same reference numerals represent the same or similar elements or components.

Please refer to FIG. 1A and FIG. 1B , FIG. 1A shows a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, and FIG. 1B shows a schematic cross-sectional view of the semiconductor device 100 along the direction 1B-1B′.

As shown in FIG. 1A and FIG. 1B , the semiconductor device 100 includes at least one semiconductor component 110 and at least one silicon-based passive component (or passive component) 120 . The silicon-based passive part 120 is stacked on the semiconductor part 110 in the thickness direction D1 of the semiconductor part 110 . In this embodiment, the silicon-based passive component 120 may include at least one passive structure, such as at least one capacitor, at least one resistor and/or at least one inductor, and/or the silicon-based passive component 120 may provide at least one input/ Output contacts. Accordingly, the silicon-based passive component 120 can support the semiconductor component 110 with high input/output density.

In this embodiment, the semiconductor component 110 is, for example, a power management integrated circuit (Power Management IC, PMIC). The substrate 10 is, for example, a single-layer structure or a multi-layer structure. The semiconductor component 110 is, for example, an unpackaged die or a semiconductor package. For example, the semiconductor component 110 is a semiconductor die or a semiconductor chip. For example, the semiconductor component 110 is, for example, Wafer Level Chip Scale Packaging (WLCSP), flip-chip Ball Grid Array (BGA) or the like. The silicon-based passive component 110 is, for example, a silicon-based capacitor.

As shown in FIGS. 1A and 1B , since the silicon-based passive part 120 is stacked on the semiconductor part 110 in a thickness direction D1 of the semiconductor part 110 , the size (or area) of the semiconductor device 100 can be reduced. In addition, the size (or area) of the semiconductor component 110 is substantially equal to the size of the silicon-based passive component 120 when viewed from above. In another embodiment, the size (or area) of the semiconductor component 110 is different from the size (or area) of the silicon-based passive component 120 when viewed from above. In addition, the size of the semiconductor component 110 is larger or smaller than that of the silicon-based passive component 120 . In the embodiment of the present invention, the active surface of the semiconductor component 110 may face the substrate 10, so that the silicon-based passive component 120 is mounted on the passive surface of the semiconductor component 110, thereby facilitating the formation of the silicon-based passive component 120 and ensuring the stability of the semiconductor device. The active surface of the semiconductor component 110 may be a surface closer to the circuit inside the semiconductor component, and the passive surface is the opposite surface of the semiconductor component.

As shown in FIG. 1B , the semiconductor component 110 has a first side 110s, the silicon-based passive component 120 has a second side 120s, and the second side 120s does not protrude relative to the first side 110s. For example, the first side 110s and the second side 120s are flush with each other. In another embodiment, the second side 120s may be recessed relative to the first side 110s. In other embodiments, the second side 120s may protrude relative to the first side 110s. In the embodiment of the present invention, the silicon-based passive component 120 can be formed in the same wafer process as the semiconductor component 110 (silicon base means this meaning), so the size of the silicon-based passive component 120 can be compared with that of the semiconductor component. The size of 110 is comparable, and when the overall size of the silicon-based passive component 120 is small, a passive component with a large capacitance, resistance and/or inductance is formed.

In addition, the semiconductor device 100 may be disposed on the substrate 10 and electrically connected to the substrate 10 . Although not shown in the figure, the semiconductor device 100 may be disposed on the substrate 10 through, for example, at least one contact (eg, solder ball, bump, pillar, etc.). In another embodiment, the substrate 10 may belong to the semiconductor device 100 . The substrate 110 is, for example, a printed circuit board (printed circuit board, PCB), an interposer (interposer) and the like.

Please refer to FIG. 2 , which is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 includes at least one semiconductor component 210 and at least one silicon-based passive component 220 . The silicon-based passive component 220 is stacked on the semiconductor component 210 along the thickness direction D1 of the semiconductor component 210 .

The semiconductor component 210 is, for example, a PMIC. The semiconductor component 210 is, for example, an unpackaged die or a semiconductor package. For example, the semiconductor component 110 is, for example, WLCSP, flip-chip (or flip-chip) BGA, or the like. In addition, the semiconductor device 200 can be disposed on the substrate 10 and electrically connected to the substrate 10 . Although not shown, the semiconductor device 200 can be disposed on the substrate 10 through, for example, at least one contact (eg, solder ball, bump, pillar, etc.).

As shown in FIG. 2, the silicon-based passive component 220 includes at least one first electrode 220E1 and at least one second electrode 220E2, the semiconductor component 210 includes at least one first conductive via 211 and at least one second conductive via 212, the first The conductive via 211 and the second conductive via 212 are electrically connected to the first electrode 220E1 and the second electrode 220E2 respectively. In this embodiment, the first conductive via 211 and/or the second conductive via 212 are, for example, through-silicon vias (TSV). A set of first electrodes 220E1 and second electrodes 220E2 is, for example, an electrode set of one of multiple passive structures in the silicon-based passive component 220 . A passive structure may be provided with at least one, such as at least one capacitor, at least one resistor and/or at least one inductor; or a passive structure may be provided with multiple, such as one or more capacitors, one or more resistors and /or one or more inductors, etc. in combination.

As shown in FIG. 2, the semiconductor component 210 has an upper surface 210u and a lower surface 210b, and the first conductive via 211 and the second conductive via 212 are exposed on the upper surface 210u to electrically connect the silicon-based passive component 220 and exposed on the lower surface. 210b is electrically connected to the substrate 10 . Conductive vias may also be used to electrically connect silicon-based passive components to circuitry within the semiconductor component, among other things. In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

Please refer to FIG. 3 , which is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 includes at least one semiconductor component 310 and at least one silicon-based passive component 220 . The silicon-based passive component 220 is stacked on the semiconductor component 310 along the thickness direction D1 of the semiconductor component 310 .

The semiconductor component 310 is, for example, a PMIC. The semiconductor device 300 can be disposed on the substrate 10 and electrically connected to the substrate 10 . Although not shown, the semiconductor device 300 can be disposed on the substrate 10 through, for example, at least one contact (such as solder balls, bumps, pillars, etc.),

As shown in FIG. 3 , the silicon-based passive component 220 includes at least one first electrode 220E1 and at least one second electrode 220E2 , and the semiconductor component 310 includes at least one first conductive via 311 and at least one second conductive via 311 . At least one first conductive via 311 and at least one second conductive via 311 are electrically connected to the first electrode 320E1 and the second electrode 320E2 respectively. In this embodiment, the first conductive via 311 and/or the second conductive via 312 are, for example, TSVs.

As shown in FIG. 3 , the semiconductor component 310 has an upper surface 310u and a lower surface 310b, and the first conductive via 311 and the second conductive via 312 are exposed (exposed) on the upper surface 210u but not exposed (exposed) on the lower surface 310b. In other words, the first conductive via 311 and the second conductive via 312 do not extend to the lower surface 310b. Such conductive vias are also referred to as "partial through vias". Conductive vias (partial vias) can also be used to electrically connect silicon-based passive components to circuitry within the semiconductor component, etc. In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

Please refer to FIG. 4 , which is a schematic cross-sectional view of a semiconductor device 400 according to another embodiment of the present invention. The semiconductor device 400 includes at least one semiconductor component 410 and at least one silicon-based passive component 220 . The silicon-based passive component 220 is stacked on the semiconductor component 410 in the thickness direction D1 of the semiconductor component 410 .

The semiconductor component 410 is, for example, a PMIC. Although not shown in the figure, the semiconductor component 400 can be disposed on the substrate 10 (the substrate 10 is shown in FIG. 1B ) by at least one contact (such as a solder ball, bump, pillar, etc.) (such as the contact 415 in the figure), for example. and electrically connected to the substrate 10.

As shown in FIG. 4 , the semiconductor component 410 includes a silicon-based electronic component (or semiconductor component) 410A, a substrate 411 , a package body 412 , a first contact 413 , a second contact 414 and at least one conductive contact 415 . The silicon-based electronic component 410A includes a similar or identical structure to the semiconductor component 210 of FIG. 2 . For example, the silicon-based electronic component 410A includes at least one contact, such as a first conductive via 211 and a second conductive via 212 . The silicon-based electronic component 410A is disposed on the substrate 411 and is electrically connected to the substrate 411 through the first contact 413 and the second contact 414 . The package body 412 encapsulates the silicon-based electronic component 410A, the first contact 413 and the second contact 414, and exposes the contacts of the silicon-based electronic component 410 (such as the first conductive via 211 and the second conductive via 212) (that is, the package body 412 not covering the contacted upper surface). The silicon-based electronic component 410A is, for example, a crystal grain or a chip. Conductive vias may also be used to electrically connect silicon-based passive components to circuitry within the semiconductor component, among other things.

The silicon-based passive component 220 is coupled to the contacts (eg, the first conductive via 211 and the second conductive via 212 ) of the silicon-based electronic component 410A. Although not shown in the figure, the silicon-based passive component 220 and the silicon-based electronic component 410A are connected through bump-to-bump. In a plan view, the size of the silicon-based passive component 220 is substantially equal to the size of the silicon-based electronic component 410A. In another embodiment, the top view dimension of the silicon-based passive component 220 is larger or smaller than the silicon-based electronic component 410A. In an embodiment of the present invention, the upper surface of the package body 412 may also be flush with the upper surface of the silicon-based passive component 220 .

In addition, the package body 412 is, for example, a molding compound. The molding compound may be formed from molding materials including, for example, novolac-based resins, epoxy-based resins, silicone-based resins, or other suitable encapsulants. The molding compound may also contain suitable fillers, such as powdered SiO2. The molding compound can use any number of applied molding techniques, such as compression molding, injection molding or transfer molding. In addition, the contacts 413 , 414 and/or 415 are, for example, solder balls, bumps, pillars, and the like. The bumps and/or pillars may be formed from materials including, for example, copper. The package body 412 can protect the silicon-based electronic component 410A and ensure stable operation of the semiconductor device. In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

Please refer to FIG. 5 , which is a schematic cross-sectional view of a semiconductor device 500 according to another embodiment of the present invention. The semiconductor device 500 includes at least one semiconductor component 410 and at least one silicon-based passive component 520 . The silicon-based passive component 520 is stacked on the semiconductor component 410 along the thickness direction D1 of the semiconductor component 410 .

The semiconductor device 500 includes a structure similar or identical to that of the semiconductor device 400 except that, for example, the silicon-based passive component 520 has a size substantially equal to that of the semiconductor component 410 in plan view.

Although not shown, the silicon-based passive component 520 and the silicon-based electronic component 410A are connected via bump-to-bump, and the semiconductor device 500 may be connected via at least one contact, such as a solder ball, bump, pillar (or pillar) etc. are disposed on the substrate 10 (the substrate 10 is shown in FIG. 1B ) and are electrically connected to the substrate 10 . The connection mode of the bump-to-bump connection can make the connection between the silicon-based passive component and the silicon-based electronic component more compact, and can reduce the height of the semiconductor device.

Referring to FIG. 6 , FIG. 6 shows a schematic cross-sectional view of a semiconductor device 600 according to another embodiment. The semiconductor device 600 includes at least one semiconductor component 610 and at least one silicon-based passive component 220 . The silicon-based passive component 220 is stacked on the semiconductor component 610 along the thickness direction D1 of the semiconductor component 610 .

The semiconductor component 610 includes a silicon-based electronic component 410A, a substrate 411 , a package 612 , a first contact 413 , a second contact 414 and at least one conductive contact 415 . The package body 612 may be made of similar or the same material as the package body 412 of FIG. 4 .

The semiconductor device 600 includes a similar or identical structure to the semiconductor device 500 , except that the package body 612 also encapsulates the silicon-based passive component 220 , for example. For example, the package body 612 further covers the upper surface 220u and at least one side surface 220s of the silicon-based passive component 220 . This enables the package to also protect the silicon-based electronic components.

In addition, in a plan view, the size of the silicon-based passive component 220 is substantially equal to the size of the silicon-based electronic component 410A. In another embodiment, in a top view, the size of the silicon-based passive component 220 is larger or smaller than the silicon-based electronic component 410A.

Please refer to FIG. 7 , which is a schematic cross-sectional view of a semiconductor device 700 according to another embodiment of the present invention. The semiconductor device 700 includes at least one semiconductor component 410 and at least one silicon-based passive component 220 . The silicon-based passive part 720 is stacked on the semiconductor part 410 in the thickness direction D1 of the semiconductor part 410 .

The silicon-based passive component 720 includes the silicon-based passive component 220 and at least one contact 721 . The contacts 721 are, for example, solder balls.

The semiconductor device 700 includes a similar or identical structure to the semiconductor device 400 , except, for example, that the silicon-based passive component 220 and the semiconductor component 410 are connected by solder ball-to-solder ball. In addition, the silicon-based passive component 220 is electrically connected to the semiconductor component 410 through the contact 721 . The solder ball-to-solder ball connection can make the connection more flexible and facilitate the mounting and connection alignment of the silicon-based passive component 220 .

In another embodiment, the package 412 of FIG. 7 can package the silicon-based passive component 720 like the package 612 of FIG. 6 packages the silicon-based passive component 220 .

Please refer to FIG. 8 , which shows a schematic cross-sectional view of a semiconductor device 800 according to another embodiment of the present invention. The semiconductor device 800 includes at least one semiconductor component 810 and at least one silicon-based passive component 720 . The silicon-based passive part 720 is stacked on the semiconductor part 410 in the thickness direction D1 of the semiconductor part 410 .

The semiconductor device 800 includes a structure similar to or identical to that of the semiconductor device 700 , except, for example, that the semiconductor component 810 includes a structure different from that of the semiconductor component 410 .

As shown in FIG. 8, the semiconductor component 810 includes a silicon-based electronic component 410A, a substrate 411, a package body 412, at least one first contact 413, at least one second contact 414, at least one conductive contact 415, and at least one third conductive via 613. The third conductive via 613 passes through the package body 412 to connect the substrate 411 and the silicon-based passive component 720 . The silicon-based passive component 720 may be electrically connected to the substrate 411 through the third conductive via 613 . The provision of the third conductive via 613 can further increase the electrical connection channel between the substrate 411 and the silicon-based passive component 720 , so that the semiconductor device has greater transmission capability.

Please refer to FIG. 9 , which is a schematic cross-sectional view of a silicon-based passive component 920 according to another embodiment of the present invention. The silicon-based passive component 920 includes at least one conductive contact 921, a silicon substrate 922, at least one capacitor structure 923, at least one dielectric layer 924, at least one conductive layer 925, at least one conductive via 926, at least one conductive contact 927 and a A re-distributed layer (RDL) structure 928 . The silicon substrate 922 may be, for example, a silicon-based material, such as polysilicon or the like.

As shown in FIG. 9 , the conductive contact 921 has a similar or identical structure to the conductive contact 721 . The number of conductive contacts 921 depends on the number of capacitor structures 923 . For example, the number (number) of capacitor structures 923 is N, the number (number) of conductive contacts 921 is 2N, and N is, for example, a positive integer greater than 1, such as 1, 2, 3...100, 101..., 1000 , 1001...etc. The silicon substrate 922 is, for example, a part of a silicon wafer. Each capacitor structure 923 includes a first electrode 920E1, a second electrode 920E2 and a dielectric layer 9231, wherein the first electrode 920E1 is formed on (or in) the hole 922a of the silicon substrate 922, and the dielectric layer 9231 is formed on the first electrode Between 920E1 and the sidewall of the hole 922a, the second electrode 920E2 is formed on the silicon substrate 922 . One of the dielectric layers 924 covers the first electrode 920E1 and the second electrode 920E2 , and exposes end surfaces of the first electrode 920E1 and end surfaces of the second electrode 920E2 . One of the conductive layers 925 is formed on the dielectric layer 924 and is electrically connected to the end surface of the first electrode 920E1 and the end surface of the second electrode 920E2 . Another dielectric layer 924 is formed between two adjacent conductive layers 925 . Conductive layer 925 includes at least one trace. The conductive via 926 passes through the dielectric layer 924 and connects two adjacent conductive layers 925 . A conductive contact 927 is formed on the bottommost conductive layer 925 and exposed to the dielectric layer 924 to electrically connect the RDL structure 928 .

In addition, the first electrode 920E1 and the second electrode 920E2 may be formed of a material including, for example, titanium nitride (TiN, titaniumnitride). Conductive contact 927 may be formed from a material including a metal such as aluminum. In one embodiment of the present invention, the second electrode 920E2 is electrically connected to the silicon substrate 922, so that the silicon substrate 922 also becomes an electrode of the capacitor structure 923, and of course the other electrode is the first electrode 920E1; the first electrode 920E1 and the second electrode The two electrodes 920E2 are connected to different voltages, for example, one of them is grounded and the other is connected with a voltage greater than zero. There is a dielectric layer 9231 between the first electrode 920E1 and the silicon substrate 922 as a space between two electrodes of the capacitor; therefore, the silicon substrate 922 can surround (for example completely surround or partially surround) the first electrode 920E1 . The capacitor structure formed in the above-mentioned manner of the present invention is not only convenient to form in the wafer process, but also makes full use of the area advantage of the silicon substrate. The capacitor structure formed has a larger capacitance value and is easy to form in the process, so it uses less The cost forms the capacitor structure. And in the embodiment of the present invention, the number of the first electrodes 920E1 (and the corresponding holes and dielectric layers) can be set in multiples, or can be set more densely, so as to further and greatly improve the capacitance value of the capacitor structure . In the present invention, the silicon-based passive component can be formed in the same wafer process as the semiconductor component, so the size of the silicon-based passive component can be equivalent to the size of the semiconductor component, and the silicon-based passive component is stacked on the semiconductor component, so it can be The area occupied is saved, and the size of the semiconductor device is reduced.

As shown in FIG. 9 , the RDL structure 928 includes at least one conductive layer 9281 , at least one conductive via 9282 and at least one dielectric layer 9283 . A dielectric layer 9283 is formed between two adjacent conductive layers 9281 , and a conductive via 9282 passes through the dielectric layer 9283 to electrically connect the two adjacent conductive layers 9281 .

Please refer to FIG. 10 , which is a schematic cross-sectional view of a silicon-based passive component 1020 according to another embodiment of the present invention. The silicon-based passive component 1020 includes at least one conductive contact 921 , a silicon substrate 922 , at least one capacitor structure 923 , at least one dielectric layer 924 , at least one conductive layer 925 , at least one conductive via 926 and RDL. Silicon-based passive component 1020 includes similar or identical structures to silicon-based passive component 920 , except that, for example, silicon-based passive component 1020 may omit conductive contact 927 . Omitting the conductive contact 927 can reduce the height and process steps of the silicon-based passive component 1020 and reduce the cost.

Please refer to FIG. 11 . FIG. 11 is a schematic cross-sectional view of a silicon-based passive component 1120 according to another embodiment of the present invention. The silicon-based passive component 1120 includes at least one conductive contact 1121, a silicon substrate 922, at least one capacitor structure 923, at least one dielectric layer 924, at least one conductive layer 925, at least one conductive via 926, at least one conductive contact 927, and an RDL structure 928.

The silicon-based passive component 1120 includes similar or identical structures to the silicon-based passive component 920 , except that, for example, the conductive contacts 1121 of the silicon-based passive component 1120 may be conductive bumps.

Please refer to FIG. 12 , which is a schematic cross-sectional view of a silicon-based passive component 1220 according to another embodiment of the present invention. The silicon-based passive component 1220 includes at least one conductive contact 1121, a silicon substrate 922, at least one capacitor structure 923, at least one dielectric layer 924, at least one conductive layer 925, at least one conductive via 926, and an RDL structure 928.

The silicon-based passive component 1220 includes similar or identical structures to the silicon-based passive component 1020 , except that the conductive contacts 1121 of the silicon-based passive component 1220 may be conductive bumps.

Referring to FIG. 13 , FIG. 13 shows a schematic cross-sectional view of a semiconductor device 1300 according to another embodiment. The semiconductor device 1300 includes at least one semiconductor component 1310 and at least one silicon-based passive component 920 . The silicon-based passive component 920 is stacked on the semiconductor component 1310 along the thickness direction D1 of the semiconductor component 1310 (as shown in FIG. 1B ).

In this embodiment, the silicon-based passive component 920 is connected to the semiconductor component 1310 through solder balls. Furthermore, the semiconductor component 1310 includes a first conductive via 1311 , a second conductive via 1312 , a silicon substrate 1313 , at least one conductive layer 1314 , at least one conductive via 1315 , at least one dielectric layer 1316 and at least one conductive contact 1317 .

The first conductive via 1311 and the second conductive via 1312 are formed on the silicon substrate 1313 . The silicon substrate 1313 has an upper surface 1313u and a lower surface 1313b opposite to the upper surface 1313u. The first conductive via 1311 and the second conductive via 1312 extend from the upper surface 1313u to the lower surface 1313b, and the first conductive via 1311 and the second conductive via 1312 may extend to the lower surface 1313b to be flush with the lower surface 1313b . Alternatively, the first conductive via hole 1311 and the second conductive via hole 1312 may not extend to the lower surface 1313b, so as to form a partial through hole structure. A dielectric layer 1316 is formed between the lower surface 1313 b and the conductive layer 1314 . The conductive via 1315 passes through the dielectric layer 1316 to connect the conductive layer 1314 with the conductive vias, such as the first conductive via 1311 and the second conductive via 1312 . The conductive contact 1317 is formed on the conductive layer 1314 for electrically connecting the first conductive via 1311 and the second conductive via 1312 .

In this embodiment, the silicon-based passive component 920 is connected to the semiconductor component 1310 through a conductive contact 921 , wherein the conductive contact 921 is, for example, a solder ball.

Referring to FIG. 14 , FIG. 14 shows a schematic cross-sectional view of a semiconductor device 1400 according to another embodiment. The semiconductor device 1400 includes at least one semiconductor component 1310 and at least one silicon-based passive component 1020 . The silicon-based passive component 1020 is stacked on the semiconductor component 1310 along the thickness direction D1 of the semiconductor component 1310 .

In this embodiment, the silicon-based passive component 1020 and the semiconductor component 1310 are connected through a conductive contact 921 .

Please refer to FIG. 15 . FIG. 15 is a schematic cross-sectional view of a semiconductor device 1500 according to another embodiment of this embodiment. The semiconductor device 1500 includes at least one semiconductor component 1510 and at least one silicon-based passive component 1120 . The silicon-based passive component 1120 is stacked on the semiconductor component 1510 along the thickness direction D1 of the semiconductor component 1510 .

In this embodiment, the silicon-based passive component 1120 is connected to the semiconductor component 1510 in a bump-to-bump manner. Furthermore, semiconductor component 1510 includes similar or identical structures as semiconductor component 1510 , except, for example, semiconductor component 1510 also includes at least one conductive contact 1518 . The conductive contacts 1518 are, for example, bumps. The conductive contact 1121 of the silicon-based passive component 1120 and the conductive contact 1518 of the semiconductor component 1510 are connected by a bump-to-bump technique.

Please refer to FIG. 16 , which is a schematic cross-sectional view of a semiconductor device 1600 according to another embodiment of this embodiment. The semiconductor device 1600 includes at least one semiconductor component 1510 and at least one silicon-based passive component 1220 . The silicon-based passive component 1220 is stacked on the semiconductor component 1510 along the thickness direction D1 of the semiconductor component 1510 .

In this embodiment, the conductive contact 1121 of the silicon-based passive component 1220 and the conductive contact 1518 of the semiconductor component 1510 are connected through a bump-to-bump technique.

Referring to FIG. 17 , FIG. 17 shows a schematic diagram of a cross section. FIG. 17 is a schematic diagram of a semiconductor device 1700 according to another embodiment of this embodiment. The semiconductor device 1700 includes at least one semiconductor component 1710 and at least one silicon-based passive component 920 . The silicon-based passive component 920 is stacked on the semiconductor component 1710 along the thickness direction D1 of the semiconductor component 1710 .

The semiconductor component 1710 includes a structure similar or identical to that of the semiconductor component 1310, except, for example, at least one of the first conductive via 1311 and the second conductive via 1312 passes through the dielectric layer 1316 and extends below the bottommost dielectric layer 1316. surface 1316b, and is exposed outside the lower surface 1316b.

To sum up, the semiconductor device includes at least one semiconductor component and at least one silicon-based passive component, wherein the silicon-based passive component is stacked on the semiconductor component along the thickness direction of the semiconductor component. The silicon-based passive component may include at least one passive structure (component), such as at least one capacitor, at least one resistor, and/or at least one inductor, and/or the silicon-based passive component 120 may provide at least one input/output contact (or contact ). Therefore, silicon-based passive components can support semiconductor components with high input/output density. Furthermore, since the silicon-based passive components are stacked above the semiconductor components, the size (or top area) of the semiconductor device can be reduced.

Those skilled in the art will readily observe that many modifications and variations of this apparatus and method can be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the metes and bounds of the appended claims.

Claims (12)

1. A semiconductor device, characterized in that, comprising: semiconductor components; and A silicon-based passive component is stacked on the semiconductor component along the thickness direction of the semiconductor component. 2. The semiconductor device according to claim 1, wherein the silicon-based passive component comprises a first electrode and a second electrode, the semiconductor component comprises a first conductive via and a second conductive via, the first conductive The through hole and the second conductive through hole are electrically connected to the first electrode and the second electrode respectively. 3. The semiconductor device according to claim 2, wherein the semiconductor component has an upper surface and a lower surface, and the first conductive via and the second conductive via are exposed on the upper surface and the lower surface; or , the first conductive via hole and the second conductive via hole are exposed on the upper surface but not exposed on the lower surface. 4. The semiconductor device according to claim 1, wherein the silicon-based passive component is a silicon-based capacitor. 5. The semiconductor device according to claim 1, wherein the silicon-based passive component comprises: Silicon substrate; a capacitor structure formed in the silicon substrate; a dielectric layer formed on the silicon substrate and exposing the capacitor structure; and A redistribution layer is formed on the dielectric layer. 6. The semiconductor device of claim 1, wherein the semiconductor component is an unpackaged die. 7. The semiconductor device according to claim 1, wherein the semiconductor component is a PMIC. 8. The semiconductor device according to claim 1, wherein the semiconductor component is a semiconductor package. 9. The semiconductor device according to claim 8, wherein the semiconductor package comprises: Silicon-based electronic components, including contacts; a package encapsulating the silicon-based electronic component and exposing the contact of the silicon-based electronic component; Wherein the silicon-based passive component is coupled to the contact of the silicon-based electronic component. 10. The semiconductor device according to claim 8, wherein the semiconductor package comprises: A silicon-based electronic component on which the silicon-based passive component is stacked; The packaging body encapsulates the silicon-based electronic component and the silicon-based electronic component. 11. The semiconductor device according to claim 1, wherein the semiconductor component has a first side, the silicon-based passive component has a second side, and the second side does not protrude relative to the first side. 12. A semiconductor device, characterized in that it comprises: semiconductor components; and The silicon-based passive component is stacked on the semiconductor component and includes a plurality of passive structures.