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CN116599348A - Balance bridge circuit, multi-level inversion system and balance bridge control method - Google Patents

Balance bridge circuit, multi-level inversion system and balance bridge control method Download PDF

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Publication number
CN116599348A
CN116599348A CN202310771998.4A CN202310771998A CN116599348A CN 116599348 A CN116599348 A CN 116599348A CN 202310771998 A CN202310771998 A CN 202310771998A CN 116599348 A CN116599348 A CN 116599348A
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CN
China
Prior art keywords
balance bridge
bridge switch
capacitor
balance
switch
Prior art date
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Pending
Application number
CN202310771998.4A
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Chinese (zh)
Inventor
姚友素
李彦龙
肖永利
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Solax Power Network Technology Zhejiang Co Ltd
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Solax Power Network Technology Zhejiang Co Ltd
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Priority to CN202310771998.4A priority Critical patent/CN116599348A/en
Publication of CN116599348A publication Critical patent/CN116599348A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from AC input or output
    • H02M1/126—Arrangements for reducing harmonics from AC input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The application belongs to the technical field of inverter circuits, and discloses a balance bridge circuit, a multi-level inversion system and a balance bridge control method, wherein the balance bridge circuit comprises an inductorL bb Balance bridge switchS 1 And balance bridge switchS 2 CapacitorC 1 And capacitorC 2 The method comprises the steps of carrying out a first treatment on the surface of the The capacitorC 1 And capacitorC 2 The bus capacitor is used for dividing voltage; the balance bridge switchS 1 And balance bridge switchS 2 For regulating capacitorsC 1 And capacitorC 2 Is a pressure difference of (2); the inductorL bb For providing circuit protection. The application reasonably controls the balance bridge switchS 1 AndS 2 the on-off time sequence and the on-off time length of the bus capacitor voltage are restrained, the capacitor voltage fluctuation is controlled within the allowable range, and the flowing through the balance bridge switch and the inductor is reducedL bb The system loss is reduced and the inverter efficiency is improved. And under the condition that a half-wave load does not exist in the inverter, the balance bridge is controlled to be not operated, so that the bus capacitor voltage is prevented from being greatly fluctuated under unnecessary adjustment.

Description

Balance bridge circuit, multi-level inversion system and balance bridge control method
Technical Field
The application belongs to the technical field of inverter circuits, and particularly relates to a balance bridge circuit, a multi-level inversion system and a balance bridge control method.
Background
The multi-level inverter is widely applied to the photovoltaic inverter and the energy storage inverter due to the advantages of small voltage current ripple, low stress of a switching device, small size of a filtering element and the like. With the rapid development of photovoltaic and energy storage industries, the power of the inverter is larger and larger, and the comprehensive performance of the single-phase multi-level inverter is weaker than that of the three-phase multi-level inverter. In addition, the demands of industrial and commercial users on new energy inverters are rapidly increased at present, and most of industrial and commercial users use three-phase electricity, so that the demands of the market on three-phase multi-level inverters are further increased.
In order to meet different requirements of different users around the world, the three-phase multi-level inverter should have perfect functions as much as possible, support grid-connected and off-grid operation, support three-wire system and four-wire system, allow unbalanced load of each phase, and allow half-wave load (such as electric hair drier, electric blanket, etc.) to be connected. A great deal of researches are carried out on the problem of unbalanced voltage (namely the problem of midpoint voltage fluctuation) of bus capacitors of a three-phase three-wire system multi-level inverter at home and abroad, and various solutions based on an improved SVPWM (space vector pulse width modulation) strategy are provided. In general, the power of each phase of the three-phase three-wire system is basically balanced, and a half-wave load is not connected into the system, so that the problem of unbalanced voltage of a bus capacitor can be better solved by improving an SVPWM (space vector pulse width modulation) strategy. However, the SVPWM modulation strategy cannot be applied to a three-phase four-wire system (the phase voltage is a saddle wave, not a sine wave), in addition, the power of each phase of the three-phase four-wire system may be extremely unbalanced (the worst case is that one phase is fully loaded, and the other two phases are empty), so that the bus capacitor voltage greatly fluctuates, and in addition, any one phase of the three-phase four-wire system may be connected with a half-wave load with an unstable direction (positive half-cycle operation or negative half-cycle operation) and a larger power at any time, which further aggravates the imbalance of the bus capacitor voltage. At present, no research on a bus capacitor voltage balance strategy aiming at three-phase four-wire system, unbalanced power of each phase and possible half-wave load application scenes is seen.
Disclosure of Invention
The application aims to provide a balance bridge circuit, a multi-level inversion system and a balance bridge control method so as to solve the technical problems.
In order to solve the technical problems, the specific technical scheme of the balance bridge circuit, the multi-level inversion system and the balance bridge control method provided by the application is as follows:
a balanced bridge circuit includes an inductorL bb Balance bridge switchS 1 And balance bridge switchS 2 CapacitorC 1 And capacitorC 2 ；
The balance bridge switchS 1 And balance bridge switchS 2 Receiving a control signal to turn on or off;
the balance bridge switchS 1 The input end of the balance bridge circuit is used as the positive electrode input of the balance bridge circuit; the balance bridge switchS 1 Output terminal of (d) and balance bridge switchS 2 Is provided, and an inductorL bb Is connected to the input first end of the first circuit;
the balance bridge switchS 2 The output end of the (a) is used as the negative electrode input of the balance bridge circuit;
the capacitorC 1 Positive pole and balance bridge switch of (2)S 1 Is connected with the input end of the capacitorC 1 Is connected to the positive electrode of the capacitor C2;
the capacitorC 2 Is connected with the balance bridge switchS 2 Is connected with the output end of the inductorL bb Is connected to the capacitor at a second end thereofC 1 And capacitorC 2 Between them.
Further, the balance bridge switchS 1 Is one of Si MOSFET, siC MOSFET, gaN MOSFET, IGBT and triode;
the balance bridge switchS 2 Is Si MOSFET, siC MOSFET, gaN MOSFET, IGBT and triodeOne of them.
Further, the capacitorC 1 And capacitorC 2 The capacitance values of (2) are equal; balance bridge switchS 1 And balance bridge switchS 2 Can enable based on the control signalU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; regulating capacitorC1 and capacitorC 2 By adjusting the differential pressure of a balance bridge switchS 1 And balance bridge switchS 2 Is realized by the conduction parameters of the power supply circuit; the conduction parameters include duty cycle and phase.
The application also discloses a multi-level inverter system of the balance bridge circuit, which also comprises a multi-level inverter; the multi-level inverter comprises a first input end, a second input end and a third input end; the first input terminal and the capacitorC 1 Is connected with the positive electrode of the battery; the second input terminal is connected to the capacitorC 1 The capacitorC 2 Between them; the third input end and the capacitorC 2 Is connected to the negative electrode of the battery.
Further, the system also comprises a filter, and the output end of the multi-level inverter is connected with the filter.
Further, the filter is an L filter, an LC filter or an LCL filter;
when the filter is an LC filter or an LCL filter, the second end of the capacitor in the filter, the second input end and the capacitorC 1 Connecting wires are arranged between the connecting wires.
Further, the multi-level inverter is a three-level four-wire system inverter, a five-level four-wire system inverter or a seven-level four-wire system inverter.
The application also discloses a balance bridge control method of the multi-level inversion system, which is characterized by comprising the following steps:
acquisition ofU C1 、U C2 AndI Lbb The method comprises the steps of carrying out a first treatment on the surface of the The saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; the saidI Lbb Is flowing through the inductorL bb Is set according to the current value of (1);
judging whether a first condition is met; the first condition includes: balance bridge switchS 1 And balance bridge switchS 2 Are all in an off state andI Lbb is smaller than the amplitude ofI Lbbp The method comprises the steps of carrying out a first treatment on the surface of the The saidI Lbbp Protecting current for the balance bridge inductance;
if the first condition is satisfied, then based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU start To balance bridge starting voltage;
if the first condition is not satisfied, based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters; the saidU end To balance the bridge stopping voltage.
Further, based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 A pressure differential reduction, comprising:
when (when)U C1 -U C2 ＞U start When the conduction parameter is adjusted to be adjusted downwards, the conduction parameter is adjusted downwards to be reducedU C1 Increase and enlargeU C2 ；
When (when)U C2 -U C1 ＞U start When the conduction parameter is adjusted, the conduction parameter is adjusted to be in the forward directionUp-regulation to increaseU C1 Reduction ofU C2 。
Further, the balance bridge switch is adjustedS 1 Balance bridge switchS 2 The conduction parameters of (1) comprise an equal duty ratio scheme and a non-equal duty ratio scheme;
in the equal duty cycle scheme: control balance bridge switchS 1 AndS 2 duty cycleD S1 AndD S2 equal and balanced bridge switchS 1 And balance bridge switchS 2 Not simultaneously conducting; when the down regulation is performed, the balance bridge switchS 1 First conducting, balance bridge switchS 2 Conducting later; when up-regulating, balance bridge switchS 2 First conducting, balance bridge switchS 1 Conducting later;
in the unequal duty cycle scheme: control balance bridge switchS 1 And balance bridge switchS 2 Duty cycleD S1 AndD S2 is not equal andD S2 =(1 –D S1 ) The method comprises the steps of carrying out a first treatment on the surface of the When the downward adjustment is performed, the position of the guide rail is adjusted,D S1 greater than 0.5, balanced bridge switchS 1 First, the switch is turned on, when the upward adjustment is performed,D S2 greater than 0.5, balanced bridge switchS 2 First conducting.
Further, the unequal duty cycle scheme includes a fixed duty cycle scheme and a variable duty cycle scheme, the fixed duty cycle schemeD S1 AndD S2 the ratio is a constant value, and the variable duty ratio schemeD S1 AndD S2 according toU C1 AndU C2 and the difference value of (2) is adjusted in real time.
Further, the fixed duty ratio scheme further includes: when (when)U C1 AndU C2 when the difference is smaller than the preset first value, the temperature is increasedD S1 AndD S2 and (3) a difference.
Further, in the variable duty cycle scheme, the method further includes:U C1 andU C2 when the difference is greater than the preset second value,increase in sizeD S1 AndD S2 a difference between;
when (when)U C1 AndU C2 when the difference is smaller than the preset third value, the reduction is carried outD S1 AndD S2 and (3) a difference.
Further, based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters, comprising: when the balance bridge is in the downward adjusting stateU C2 –U C1 >U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp When balancing bridge switchS 1 And balance bridge switchS 2 Turning off;
when the balance bridge is in the upward regulated stateU C1 –U C2 >U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp When balancing bridge switchS 1 And balance bridge switchS 2 And switching off, otherwise, driving the balance bridge switch according to the set on parameter.
The balance bridge circuit, the multi-level inversion system and the balance bridge control method have the following advantages: the balance bridge circuit is suitable for a three-phase four-wire system multi-level inverter, has a simple hardware structure, needs few elements and has low system cost; the balance bridge circuit control method of the application can adjust the condition that half-wave load exists in the multi-level inverter by reasonably controlling the balance bridge switchS 1 AndS 2 ) The on-off time sequence and the on-off time length of the bus capacitor voltage are restrained, the capacitor voltage fluctuation is controlled within the allowable range, and the inductance of the balance bridge flowing through the balance bridge switch and the balance bridge is reducedL bb ) The system loss is reduced and the inverter efficiency is improved. And under the condition that a half-wave load does not exist in the inverter, the balance bridge is controlled to be turned off, so that the bus capacitor voltage is prevented from being greatly fluctuated under unnecessary adjustment. The application reduces the opening of the balance bridge through the parameter design of the balance bridgeAnd the current of the balance bridge inductor is closed, so that the system loss is reduced, the system efficiency is improved, and the volume of the balance bridge inductor is reduced. The balance bridge inductance current does not exceed the design value, the problem of overcurrent burnout of the balance bridge switch caused by inductance saturation is avoided, the reliability is high, and the balance bridge parameter design method is simple and practical and has higher engineering application value.
Drawings
FIG. 1 is a schematic diagram of a three-phase four-wire system three-level inverter system including a balanced bridge circuit according to the present application;
FIG. 2 is a schematic diagram of main waveforms during the voltage balancing process of the bus capacitor according to the equal duty ratio scheme of the present application;
FIG. 3 is a schematic diagram of main waveforms during the voltage balancing process of the bus capacitor according to the duty cycle scheme of the present application;
FIG. 4 is a flow chart of a method for controlling a balance bridge according to the present application;
FIG. 5 is a three-phase four-wire system T-type three-level inverter circuit diagram based on an LCL filter of the present application;
FIG. 6 is a schematic diagram of main waveforms of the balance bridge circuit when the balance bridge is not operating under a first condition in an embodiment of the present application;
FIG. 7 is a schematic diagram of main waveforms of the balance bridge circuit when the balance bridge is operated under a first condition in an embodiment of the present application;
FIG. 8 is a schematic diagram of main waveforms of the balance bridge circuit when the balance bridge is not operating under the second condition in the embodiment of the present application;
FIG. 9 is a schematic diagram of main waveforms of the balance bridge circuit when the balance bridge is operated under the second condition in the embodiment of the present application;
fig. 10 is a schematic diagram of main waveforms of the balanced bridge circuit under three conditions in the embodiment of the present application.
Detailed Description
In order to better understand the purpose, structure and function of the present application, a balanced bridge circuit, a multi-level inverter system and a balanced bridge control method according to the present application are described in further detail below with reference to the accompanying drawings.
As shown in fig. 1, a balanced bridge circuit of the present application includes an inductorL bb Balance bridge switchS 1 And balance bridge switchS 2 CapacitorC 1 And capacitorC 2 ；
The balance bridge switchS 1 And balance bridge switchS 2 Receiving a control signal to turn on or off; balance bridge switchS 1 And balance bridge switchS 2 Can enable based on the control signalU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; regulating capacitorC1 and capacitorC 2 By adjusting the differential pressure of a balance bridge switchS 1 And balance bridge switchS 2 Is realized by the conduction parameters of the power supply circuit; the conduction parameters include duty cycle and phase.
The balance bridge switchS 1 The input end of the balance bridge circuit is used as the positive electrode input of the balance bridge circuit; the balance bridge switchS 1 Output terminal of (d) and balance bridge switchS 2 Is provided, and an inductorL bb Is connected to the input first end of the first circuit;
the balance bridge switchS 2 The output end of the (a) is used as the negative electrode input of the balance bridge circuit;
the capacitorC 1 Positive pole and balance bridge switch of (2)S 1 Is connected with the input end of the capacitorC 1 Is connected to the positive electrode of the capacitor C2;
the capacitorC 2 Is connected with the balance bridge switchS 2 Is connected with the output end of the inductorL bb Is connected to the capacitor at a second end thereofC 1 And capacitorC 2 Between them.
The balance bridge circuit is connected with the bus voltageU bus And a multilevel inverter for adjusting the balance of the divided voltage of the bus voltage. The capacitorC 1 And capacitorC 2 The bus capacitor is used for dividing voltage; the balance bridge switchS 1 And balance bridge switchS 2 For regulating capacitorsC1 and capacitorC 2 Is a pressure difference of (2); the inductorL bb For providing circuit protection. The balance bridge circuit is suitable for inverters such as a three-phase four-wire system multi-level inverter, a five-level four-wire system inverter or a seven-level four-wire system inverter, has simple hardware structure, needs few elements, has low system cost and can effectively regulate the balance of bus voltage.
The balance bridge switch S1 is one of a Si MOSFET, a SiC MOSFET, a GaN MOSFET, an IGBT and a triode;
the balance bridge switch S2 is one of a Si MOSFET, a SiC MOSFET, a GaN MOSFET, an IGBT and a triode.
The capacitorC 1 And capacitorC 2 The capacitance values of (2) are equal.
The multi-level inversion system comprises the balance bridge circuit and a multi-level inverter; the multi-level inverter comprises a first input end, a second input end and a third input end; the first input terminal and the capacitorC 1 Is connected with the positive electrode of the battery; the second input terminal is connected to the capacitorC 1 The capacitorC 2 Between them; the third input end and the capacitorC 2 Is connected to the negative electrode of the battery. Specifically, a capacitorC 1 Balance bridge switchS 1 One end of (2) is connected with the bus voltageU bus Positive electrode of (a) capacitorC 1 Is connected with a capacitor at the other endC 2 Is a capacitorC 2 Is connected with the bus voltage at the other endU bus Is a negative pole, balance bridge switchS 1 The other end of the switch is connected with a balance bridge switchS 1 Is a balanced bridge switchS 1 Is connected with the bus voltage at the other endU bus Is a negative electrode of (a), an inductorL bb One end of (a) is connected with a balance bridge switchS 1 And balance bridge switchS 2 Is connected with the inductorL bb Is connected with a capacitor at the other endC 1 And capacitorC 2 Is the junction point of (i.e. the midpoint of the bus capacitance)O) Bus voltageU bus Midpoint of both ends and bus capacitorOThe first input end, the third input end and the second input end of the multi-level inverter are respectively connected.
The balanced bridge circuit can reasonably control the balanced bridge switch under the condition that half-wave load exists in the multi-level inverterS 1 And balance bridge switchS 2 The on-off time sequence and the on-off time length of the bus capacitor voltage are restrained, the capacitor voltage fluctuation is controlled within the allowable range, and the flowing through the balance bridge switch and the balance bridge inductance are reducedL bb The system loss is reduced and the efficiency of the multilevel inverter is improved. And under the condition that a half-wave load does not exist in the inverter, the balance bridge is controlled to be not operated, so that the bus capacitor voltage is prevented from being greatly fluctuated under unnecessary adjustment.
The system also comprises a filter, and the output end of the multi-level inverter is connected with the filter. The filter is an L filter, an LC filter or an LCL filter; as shown in fig. 5, when the filter is an LC filter or an LCL filter, the second end of the capacitor in the filter is connected with the second input end and the capacitorC 1 Connecting wires are arranged between the connecting wires.
The multi-level inverter is a three-level four-wire system inverter, a five-level four-wire system inverter or a seven-level four-wire system inverter.
The balance bridge control method of the application comprises the following steps:
acquisition ofU C1 、U C2 AndI Lbb The method comprises the steps of carrying out a first treatment on the surface of the The saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; the saidI Lbb Is flowing through the inductorL bb Is set according to the current value of (1);
judging whether a first condition is met; the first condition includes: balance bridge switchS 1 And balance bridge switchS 2 Are all in an off state andI Lbb is smaller than the amplitude ofI Lbbp The method comprises the steps of carrying out a first treatment on the surface of the The saidI Lbbp Protecting current for the balance bridge inductance;
if the first condition is satisfied, then based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU start To balance bridge starting voltage;
based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 A pressure differential reduction, comprising:
when (when)U C1 -U C2 ＞U start When the conduction parameter is adjusted to be adjusted downwards, the conduction parameter is adjusted downwards to be reducedU C1 Increase and enlargeU C2 ；
When (when)U C2 -U C1 ＞U start When the conduction parameter is adjusted to be upward adjusted to be increasedU C1 Reduction ofU C2 。
The balance bridge switchS 1 Balance bridge switchS 2 The conduction parameters of (1) comprise an equal duty ratio scheme and a non-equal duty ratio scheme;
in the equal duty cycle scheme: control balance bridge switchS 1 AndS 2 duty cycleD S1 AndD S2 equal and balanced bridge switchS 1 And balance bridge switchS 2 Not simultaneously conducting; when the down regulation is performed, the balance bridge switchS 1 First conducting, balance bridge switchS 2 Conducting later; when up-regulating, balance bridge switchS 2 First conducting, balance bridge switchS 1 Conducting later;
in the unequal duty cycle scheme: control balance bridge switchS 1 AndS 2 duty cycleD S1 AndD S2 is not equal andD S2 =(1 –D S1 ) The method comprises the steps of carrying out a first treatment on the surface of the When the downward adjustment is performed, the position of the guide rail is adjusted,D S1 greater than 0.5, balanced bridge switchS 1 First, the switch is turned on, when the upward adjustment is performed,D S2 greater than 0.5, balanced bridge switchS 2 First conducting.
The unequal duty cycle scheme comprises a fixed duty cycle scheme and a variable duty cycle scheme, wherein the fixed duty cycle schemeD S1 AndD S2 the ratio is a constant value, and the variable duty ratio schemeD S1 AndD S2 according toU C1 AndU C2 and the difference value of (2) is adjusted in real time.
The duty ratio setting scheme further comprises: when (when)U C1 AndU C2 when the difference is smaller than the preset first value, the temperature is increasedD S1 AndD S2 and (3) a difference.
The variable duty ratio scheme further comprises:U C1 andU C2 when the difference is larger than the preset second value, the temperature is increasedD S1 AndD S2 a difference between; when (when)U C1 AndU C2 when the difference is smaller than the preset third value, the reduction is carried outD S1 AndD S2 and (3) a difference. The preset first value, the preset second value and the preset third value may be point values or range values. The preset first value, the preset second value and the preset third value can be selected by a person skilled in the art according to the circuit performance requirements under the condition of meeting the requirements of electric power compliance and the like.
If the first condition is not satisfied, based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters; the saidU end To balance the bridge stopping voltage.
The base is based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters, comprising:
when the balance bridge is in the downward adjusting stateU C2 –U C1 >U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp When the balance bridge stops working;
when the balance bridge is in the upward regulated stateU C1 –U C2 >U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp And if not, driving the balance bridge switch according to the set conduction parameter.
Equal duty cycle scheme embodiment:
taking the most commonly used duty cycle scheme of 0.5, etc., as shown in figure 2,U GS1 andU GS2 respectively balanced bridge switchS 1 And balance bridge switchS 2 Is used for the driving signal of the (a),Tis a switching period.t 0 ~t 1 Time period, balance bridge switchS 1 Switch on and balance bridge switchS 2 Turn-off, the voltage across the inductor isU C1 DC power supplyU bus By passing throughS 1 、L bb Feed capacitorC 2 The electric power is charged up and the electric power is supplied to the electric power,I Lbb the rise is made in a linear fashion,U C2 the number of the cells to be processed is increased,U C1 a reduction;t 1 ~t 2 time period, balance bridge switchS 1 Switch-off, balance bridge switchS 2 Conducting, the voltage at two ends of the inductor is-U C2 Since the balance bridge inductance current cannot be suddenly changed, the balance bridge inductance current is still positive,C 1 by dc power supplyU bus 、S 2 、L bb The electric discharge is carried out by a discharge lamp,U C2 the increase is continued and the process is continued,U C1 and continue to decrease. After the lapse of 1 period of time,U C1 andU C2 the difference is reduced, butU C1 Still higher thanU C2 Thus continuing to repeatThe process is carried out untilU C1 AndU C2 equal. The speed of regulating the bus capacitor voltage in the equal duty ratio scheme is positively related to the capacitor voltage difference whenU C1 AndU C2 when the difference is smaller, the voltage regulating speed of the bus capacitor is slower, and the dynamic characteristic of the system is poorer.
Unequal duty cycle scheme embodiment:
as shown in FIG. 3, the voltage balancing method is a main waveform in the voltage balancing process of the bus capacitor with a fixed duty ratio scheme, and in the diagram, a balancing bridge switchS 1 Duty cycle of (2)D S1 Constant, balanced bridge switch greater than 0.5S 2 Duty cycle of (2)D S2 Equal to (1-D S1 ). FIG. 3 is generally similar to FIG. 2, but due toD S1 Greater thanD S2 The balance bridge inductance current changes faster, the bus capacitor voltage regulating speed is faster, and the dynamic response characteristic is better. When (when)U C1 AndU C2 when the difference is smaller than the preset first value, the difference can be increasedD S1 Reduction ofD S2 To maintain a good dynamic response speed. The principle of regulating the bus capacitor voltage is the same as that of the fixed duty ratio scheme, but the voltage is regulated in real time according to the bus capacitor voltage difference in the process of regulating the bus capacitor voltageD S1 AndD S2 . When the bus capacitance differential pressure is larger than the preset second value, the bus capacitance differential pressure is properly increasedD S1 AndD S2 the difference accelerates the adjustment process; when the bus capacitance differential pressure is smaller than the preset third value, the method properly reducesD S1 AndD S2 and the difference between the two is improved, so that the adjustment precision is improved.
Balance bridge control method embodiment:
as shown in fig. 4, which is a flowchart of a control method of the balance bridge of the multi-level inverter, flag is a working state Flag of the balance bridge; flag equal to 0 indicates an idle state, balanced bridge switchS 1 And balance bridge switchS 2 Are all in an off state; flag equal to 1 indicates a downward regulation state, and the energy of the upper voltage-equalizing capacitor is transferred to the lower voltage-equalizing capacitor to reduceU C1 Increase in sizeU C2 Balance bridge switchS 1 First conducting, balance bridge switchS 2 Conducting later; flag equal to 2 indicates an upward regulation state, and the energy of the lower equalizing capacitor is transferred to the upper equalizing capacitor to increaseU C1 Reduction ofU C2 Balance bridge switchS 2 First conducting, balance bridge switchS 1 And then conducting.I Lbbp Is the protection current of the inductance of the balance bridge,I Lbb is the real-time current of the inductance of the balance bridge only whenI Lbb Is smaller than the amplitude ofI Lbbp Only when the balance bridge works, otherwise, the balance bridge switchS 1 And balance bridge switchS 2 Will be in an off state.U start Is the starting voltage of the balance bridge whenU C1 AndU C2 the difference is greater thanU start The balance bridge starts to work, and the upper and lower voltage equalizing capacitor voltages are regulated. Under the conditions of three-phase four-wire system, unbalanced power of each phase and high-power half-wave load,U start the overlarge voltage difference between the upper voltage-sharing capacitor and the lower voltage-sharing capacitor is easy to cause, and the service life of the bus capacitor is influenced;U start too small, the balance bridge can erroneously adjust voltage fluctuation of the bus capacitor caused by unbalanced power of each phase, so that the balance bridge moves more reactive power, system efficiency is reduced, and the voltage adjusting effect of the bus capacitor is affected.U end Is the stopping voltage of the balance bridge, when the balance bridge is in a downward regulating stateU C2 –U C1 >U end When the balance bridge stops working; when the balance bridge is in the upward regulated stateU C1 –U C2 >U end When the balance bridge stops working.
After the sampling of the bus capacitor voltage is finished, the system main controller enters a flow shown in fig. 4. The balance bridge control method mainly comprises the following 11 steps:
step 1: judging that the balance bridge is in an idle state (flag=0) and the amplitude of the inductance current of the balance bridge is smaller than the inductance protection current of the balance bridge (|I Lbb |<I Lbbp ) If so, entering step 2, otherwise jumping to step 6.
Step 2: judgingU C1 –U C2 Greater thanU start If so, entering step 3, otherwise jumping to step 4.
Step 3: determining a balanced bridge switch using any one of an equal duty cycle scheme, a fixed duty cycle scheme, or a variable duty cycle schemeS 1 AndS 2 the balance bridge operating state flag is set to 1.
Step 4: judgingU C2 –U C1 Greater thanU start If so, entering step 5, otherwise jumping to step 6.
Step 5: determining a balanced bridge switch using any one of an equal duty cycle scheme, a fixed duty cycle scheme, or a variable duty cycle schemeS 1 AndS 2 the balance bridge operating state flag is set to 2.
Step 6: and judging whether the balance bridge working state mark is 1 or not, if so, entering a step 7, otherwise, jumping to the step 8.
Step 7: judgingU C2 –U C1 Greater thanU end Or if the magnitude of the balance bridge inductance current is greater than or equal to the balance bridge inductance protection current, if so, jumping to the step 10, otherwise jumping to the step 11.
Step 8: and judging whether the balance bridge working state mark is 2 or not, if so, entering a step 9, otherwise, jumping to the step 10.
Step 9: judgingU C1 –U C2 Greater thanU end Or if the magnitude of the balance bridge inductance current is greater than or equal to the balance bridge inductance protection current, if so, jumping to the step 10, otherwise jumping to the step 11.
Step 10: switch for balancing bridge working state sign and balancing bridgeS 1 AndS 2 the duty cycles of (2) are all set to 0. And the bus capacitor voltage regulation flow in the period is finished.
Step 11: driving balance bridge switch according to set duty ratioS 1 AndS 2 . And the bus capacitor voltage regulation flow in the period is finished.
Taking the three-phase four-wire system T-shaped multi-level inverter based on the LCL filter as an example, which is shown in fig. 5, the correctness of the real-time modulation strategy and the parameter design method of the balance bridge of the multi-level inverter provided by the application is illustrated.
FIG. 6 shows the drive signal of the switch on the balance bridge when the balance bridge is not in operation under the conditions of 650/V, A phase with 2kW half-wave load, full B phase (10 kW) and no C phase (working condition one)U GS1 Balanced underbridge switch drive signalU GS2 Upper voltage equalizing capacitor voltageU C1 Voltage of lower equalizing capacitorU C2 And balancing bridge inductor currentI Lbb And simulating waveforms.U GS1 、U GS2 、I Lbb Is always zero and is used for the treatment of the heart failure,U C1 the water is gradually lowered down to the water level,U C2 gradually rise, and the capacitance voltage deviation is larger.
FIG. 7 is a graph of the switching drive signals on a balance bridge during operation of the balance bridge according to the proposed modulation scheme under one conditionU GS1 Balanced underbridge switch drive signalU GS2 Upper voltage equalizing capacitor voltageU C1 Voltage of lower equalizing capacitorU C2 And balancing bridge inductor currentI Lbb And simulating waveforms. When (when)U C2 –U C1 >U start When the balance bridge starts to work, the inductance current is negative,C 1 the electric power is charged up and the electric power is supplied to the electric power,C 2 and (5) discharging. Since the balance bridge has limited power, and A, B phase instant power is very high, when the balance bridge just begins to work,U C1 the voltage is continued to be reduced and,U C2 the voltage continues to increase, but, after the A, B phase instantaneous power decreases,U C1 the voltage starts to rise and,U C2 the voltage starts to drop and, eventually,U C1 fluctuating up and down around 305V,U C2 fluctuating up and down around 345V. Compared with the sixth result of the graph, the proposal obviously reduces the pressure difference of the upper and lower equalizing capacitors.
FIG. 8 is a DC bus voltage of 650V, A phase with 2kW half wave load, B phase andswitch driving signal on balance bridge when balance bridge is not working under C-phase no-load condition (working condition two)U GS1 Balanced underbridge switch drive signalU GS2 Upper voltage equalizing capacitor voltageU C1 Voltage of lower equalizing capacitorU C2 And balancing bridge inductor currentI Lbb And simulating waveforms.U GS1 、U GS2 、I Lbb Is always zero and is used for the treatment of the heart failure,U C1 the water is gradually lowered down to the water level,U C2 gradually rise, and the capacitance voltage deviation is large.
FIG. 9 is a graph of the switching drive signals on the balance bridge during operation of the balance bridge according to the proposed modulation scheme for two conditionsU GS1 Balanced underbridge switch drive signalU GS2 Upper voltage equalizing capacitor voltageU C1 Voltage of lower equalizing capacitorU C2 And balancing bridge inductor currentI Lbb And simulating waveforms. When (when)U C2 –U C1 >U start When the balance bridge starts to work, the inductance current is negative,C 1 the electric power is charged up and the electric power is supplied to the electric power,C 2 and (5) discharging. Because the balance bridge has limited power and the phase A instantaneous power is larger, when the balance bridge just begins to work,U C1 the voltage is continued to be reduced and,U C2 the voltage continues to increase, but, after the a-phase instantaneous power decreases,U C1 the voltage starts to rise and,U C2 the voltage starts to drop and, eventually,U C1 andU C2 the pressure differential decreases. Compared with the eighth result of the graph, the proposal obviously reduces the pressure difference of the upper and lower equalizing capacitors.
FIG. 10 shows the DC bus voltage of 650V, B phases full load (10 kW), and the switch drive signals on the balance bridge under the condition of A phase and C phase no-load (working condition three)U GS1 Balanced underbridge switch drive signalU GS2 Upper voltage equalizing capacitor voltageU C1 Voltage of lower equalizing capacitorU C2 And balancing bridge inductor currentI Lbb And simulating waveforms.U GS1 、U GS2 、I Lbb Is always zero and is used for the treatment of the heart failure,U C1 andU C2 all fluctuate at 325V, peakPeak value of 340V, belowU start The balancing bridge is therefore not working. Under the third working condition, the system has no half-wave load, the balance bridge does not work, and the correctness of the provided modulation strategy is verified.
It will be understood that the application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.

Claims (14)

1. A balanced bridge circuit comprising an inductorL bb Balance bridge switchS 1 And balance bridge switchS 2 CapacitorC 1 And capacitorC 2 ；
The balance bridge switchS 1 And balance bridge switchS 2 Receiving a control signal to turn on or off;
the balance bridge switchS 1 The input end of the balance bridge circuit is used as the positive electrode input of the balance bridge circuit; the balance bridge switchS 1 Output terminal of (d) and balance bridge switchS 2 Is provided, and an inductorL bb Is connected to the input first end of the first circuit;
the balance bridge switchS 2 The output end of the (a) is used as the negative electrode input of the balance bridge circuit;
the capacitorC 1 Positive pole and balance bridge switch of (2)S 1 Is connected with the input end of the capacitorC 1 Is connected to the positive electrode of the capacitor C2;
the capacitorC 2 Is connected with the balance bridge switchS 2 Is connected with the output end of the power supplySensor(s)L bb Is connected to the capacitor at a second end thereofC 1 And capacitorC 2 Between them.
2. The balanced bridge circuit of claim 1, wherein the balanced bridge switchS 1 Is one of Si MOSFET, siC MOSFET, gaN MOSFET, IGBT and triode;
the balance bridge switchS 2 Is one of Si MOSFET, siC MOSFET, gaN MOSFET, IGBT and triode.
3. The balanced bridge circuit according to claim 1 or 2, characterized in that the capacitorC 1 And capacitorC 2 The capacitance values of (2) are equal; balance bridge switchS 1 And balance bridge switchS 2 Can enable based on the control signalU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; regulating capacitorC1 and capacitorC 2 By adjusting the differential pressure of a balance bridge switchS 1 And balance bridge switchS 2 Is realized by the conduction parameters of the power supply circuit; the conduction parameters include duty cycle and phase.
4. A multilevel inverter system comprising the balanced bridge circuit according to any one of claims 1-3, wherein the system further comprises a multilevel inverter; the multi-level inverter comprises a first input end, a second input end and a third input end; the first input terminal and the capacitorC 1 Is connected with the positive electrode of the battery; the second input terminal is connected to the capacitorC 1 The capacitorC 2 Between them; the third input end and the capacitorC 2 Is connected to the negative electrode of the battery.
5. The multilevel inverter system of claim 4, further comprising a filter, the multilevel inverter output coupled to the filter.
6. The multilevel inverter system of claim 5, wherein the filter is an L filter, an LC filter, or an LCL filter;
when the filter is an LC filter or an LCL filter, the second end of the capacitor in the filter, the second input end and the capacitorC 1 Connecting wires are arranged between the connecting wires.
7. The multi-level inverter system of claim 4, wherein the multi-level inverter is a three-level four-wire inverter, a five-level four-wire inverter, or a seven-level four-wire inverter.
8. A balance bridge control method of the multilevel inverter system according to any one of claims 4 to 7, comprising:
acquisition ofU C1 、U C2 AndI Lbb The method comprises the steps of carrying out a first treatment on the surface of the The saidU C1 A voltage value across the capacitor C1; the saidU C2 Is a capacitorC 2 The voltage values at both ends; the saidI Lbb Is flowing through the inductorL bb Is set according to the current value of (1);
judging whether a first condition is met; the first condition includes: balance bridge switchS 1 And balance bridge switchS 2 Are all in an off state andI Lbb is smaller than the amplitude ofI Lbbp The method comprises the steps of carrying out a first treatment on the surface of the The saidI Lbbp Protecting current for the balance bridge inductance;
if the first condition is satisfied, then based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 The pressure difference is reduced; the saidU start To balance bridge starting voltage;
if the first condition is not satisfied, based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters; the saidU end To balance the bridge stopping voltage.
9. The balance bridge control method of claim 8, based onU C1 And (3) withU C2 Pressure difference of (2)U start Is used for adjusting the balance bridge switchS 1 Balance bridge switchS 2 To the conduction parameter of (1) so thatU C1 A kind of electronic deviceU C2 A pressure differential reduction, comprising:
when (when)U C1 -U C2 ＞U start When the conduction parameter is adjusted to be adjusted downwards, the conduction parameter is adjusted downwards to be reducedU C1 Increase and enlargeU C2 ；
When (when)U C2 -U C1 ＞U start When the conduction parameter is adjusted to be upward adjusted to be increasedU C1 Reduction ofU C2 。
10. The balance bridge control method of claim 9, wherein the balance bridge switch is adjustedS 1 Balance bridge switchS 2 The conduction parameters of (1) comprise an equal duty ratio scheme and a non-equal duty ratio scheme;
in the equal duty cycle scheme: control balance bridge switchS 1 AndS 2 duty cycleD S1 AndD S2 equal and balanced bridge switchS 1 And balance bridge switchS 2 Not simultaneously conducting; when the down regulation is performed, the balance bridge switchS 1 First conducting, balance bridge switchS 2 Conducting later; when upward adjustment is performed, the device is flatHeng Qiaokai offS 2 First conducting, balance bridge switchS 1 Conducting later;
in the unequal duty cycle scheme: control balance bridge switchS 1 And balance bridge switchS 2 Duty cycleD S1 AndD S2 is not equal andD S2 =(1 –D S1 ) The method comprises the steps of carrying out a first treatment on the surface of the When the downward adjustment is performed, the position of the guide rail is adjusted,D S1 greater than 0.5, balanced bridge switchS 1 First, the switch is turned on, when the upward adjustment is performed,D S2 greater than 0.5, balanced bridge switchS 2 First conducting.
11. The method of claim 10, wherein the unequal duty cycle scheme comprises a fixed duty cycle scheme and a variable duty cycle scheme, the fixed duty cycle schemeD S1 AndD S2 the ratio is a constant value, and the variable duty ratio schemeD S1 AndD S2 according toU C1 AndU C2 and the difference value of (2) is adjusted in real time.
12. The method according to claim 11, characterized in that in the fixed duty ratio scheme further comprises: when (when)U C1 AndU C2 when the difference is smaller than the preset first value, the temperature is increasedD S1 AndD S2 and (3) a difference.
13. The balance bridge control method according to claim 11, characterized in that in the variable duty ratio scheme, further comprising:U C1 andU C2 when the difference is larger than the preset second value, the temperature is increasedD S1 AndD S2 a difference between;
when (when)U C1 AndU C2 when the difference is smaller than the preset third value, the reduction is carried outD S1 AndD S2 and (3) a difference.
14. The balance bridge control method according to claim 9,characterized by that based onU C1 And (3) withU C2 Pressure difference of (2)U end Size relation or (v) ofI Lbb Amplitude of (2)I Lbbp Judging whether to drive the balance bridge switch according to the set conduction parameters, comprising: when the balance bridge is in the downward adjusting stateU C2 – U C1 > U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp When balancing bridge switchS 1 And balance bridge switchS 2 Turning off;
when the balance bridge is in the upward regulated stateU C1 – U C2 > U end Or (b)I Lbb Is greater than the amplitude ofI Lbbp When balancing bridge switchS 1 And balance bridge switchS 2 And switching off, otherwise, driving the balance bridge switch according to the set on parameter.
CN202310771998.4A 2023-06-28 2023-06-28 Balance bridge circuit, multi-level inversion system and balance bridge control method Pending CN116599348A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118590037A (en) * 2024-08-01 2024-09-03 浙江大学舟山海洋研究中心 A circuit system replacing high-voltage relay for ultrasonic receiving control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118590037A (en) * 2024-08-01 2024-09-03 浙江大学舟山海洋研究中心 A circuit system replacing high-voltage relay for ultrasonic receiving control

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