CN116598340B - A SiC MOSFET and its manufacturing process - Google Patents

Abstract

The application relates to a SiC MOSFET and a manufacturing process method thereof, which can reduce the follow current loss of a parasitic body diode, ensure the normal conduction and reverse voltage withstanding characteristics of the SiC MOSFET, and the SiC MOSFET comprises a drain electrode metal layer, a substrate, a drift layer, a gate insulating layer, a gate, source electrode metal layers, a P+ Ge doped region, a well region and a source region which are distributed on two sides of the gate from bottom to top, wherein the P+ Ge doped region, the well region and the source region are positioned in the drift layer, the well region is positioned in the top regions on two sides of the drift layer, the P+ Ge doped region longitudinally penetrates through the well region and then contacts with the drift layer, and the well region is divided into two regions: the source region is positioned at the right-angle inner side of the L-shaped region, the outer side end of the P+ Ge doped region is contacted with the inner side end of the L-shaped region, the inner side end of the P+ Ge doped region is contacted with the outer side end of the source region and the bottom side end of the L-shaped region, the source metal layer is positioned at the top ends of the source region and the P+ Ge doped region, and the P+ Ge doped region and the drift layer form a heterojunction.

Description

A SiC MOSFET and its manufacturing process

Technical field

The invention belongs to the field of semiconductor technology, and specifically relates to a planar gate SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) with controllable conduction voltage drop.

Background technique

Silicon carbide metal oxide field effect transistor (SiC MOSFET), as a typical representative of the third generation semiconductor, is widely used in 5G due to its advantages such as small parasitic capacitance, breakdown electric field, small size, fast heat dissipation, and low energy loss. In high-voltage and high-speed switches such as smart cars, power electronics, etc., when SiC MOSFET is used as a freewheeling diode, due to its wide bandgap characteristics, the parasitic body diode existing between its source and drain is smaller than the dedicated freewheeling diode. There is a higher forward voltage drop, and the conduction voltage drop of the parasitic body diode is generally 2V-3V, which is much larger than Si material devices. In this case, the problem of large freewheeling loss of the parasitic body diode will occur in the application.

Contents of the invention

In view of the technical problem of large freewheeling loss of parasitic body diodes existing in the prior art, this application provides a SiC MOSFET with a simple and reasonable structural design, which can reduce the freewheeling loss of parasitic body diodes.

In order to achieve the above purpose, this application adopts the following technical solutions:

A SiC MOSFET, which includes a drain metal layer, a substrate, a drift layer, a gate insulating layer, a gate electrode, and a source metal layer distributed on both sides of the gate electrode in order from bottom to top, and is characterized in that it It also includes a P+Ge doped region, a well region, and a source region. The P+Ge doped region, well region, and source region are located in the drift layer. The well region is located in the top areas on both sides of the drift layer. , the P+Ge doped region penetrates the well region longitudinally and then contacts the drift layer, and divides the well region into two regions: a strip region and an L-shaped region, and the source region is located in the Inside the right angle of the L-shaped region, the outer end of the P+Ge doped region is in contact with the inner end of the strip region, and the inner end of the P+Ge doped region is in contact with the outer end of the source region, the L-shaped The bottom side end of the region is in contact, the source metal layer is located at the top of the source region and the P+Ge doped region, and forms ohmic contact with the source region and the P+Ge doped region respectively, and the P+Ge The doped region forms a heterojunction with the drift layer.

It is further characterized by,

The substrate is a SiC substrate;

Further, the thickness of the P+Ge doped region is 160 times the thickness of the thinnest part of the well region, and the doping concentration of the P+Ge doped region is one 160th of that of the well region;

Further, the doping concentration of the well region is 6×10 ¹⁷ cm-3~1.2×10 ¹⁸ cm-3, and the doping concentration of the source region is 1×10 ¹⁸ cm-3~2×10 ¹⁸ cm. -3;

Further, the drift layer is an N+SiC doped region, and the P+Ge doped region forms a heterojunction with the N+SiC doped region;

Further, the L-shaped region includes a vertical region and a lateral region, the thickness of the vertical region ranges from 200nm to 400nm, the thickness of the lateral region ranges from 20nm to 50nm, and the thickness of the source region is the thickness of the lateral region. The difference from the thickness of the vertical area.

A method of manufacturing SiC MOSFET, characterized in that the method includes:

S1. Provide a substrate;

S2. Deposit a drain metal layer on the bottom of the substrate, and epitaxially grow a drift layer on the top of the substrate;

S3. Inject ions into the tops of both sides of the drift layer to form well regions;

S4. Etch the middle portion of the well region near the outer edge to form a second through hole that penetrates the well region. The second through hole divides the well region into two strip-shaped regions: the first strip-shaped region. , a second strip-shaped region, in which a P+Ge doped region is epitaxially grown inside and outside the second through hole;

S5. Inject ions into the top outer region of the second strip-shaped region to form a source region;

S6. Deposit a source metal layer on the top of the source region and the P+Ge doped region;

S7. Deposit a gate insulating layer and a gate layer sequentially on the top and middle portion of the drift layer.

It is further characterized by,

In step S3, using a photolithography process and an ion implantation process, the steps of forming the well region include: S31, covering the top of the drift layer with a first barrier layer;

S32. Etch and expose the first barrier layer to form a first through hole. The first through hole exposes the tops of both sides of the drift layer;

S33. Use an ion implantation process to inject ions into the tops of both sides of the drift layer through the first through hole to form the well region;

S34. Clear the first barrier layer;

Furthermore, the material of the well region is SIC, and the ions implanted in the well region are boron ions;

Further, in step S4, using a photolithography process and a deposition process, the steps of forming the P+Ge doped region include:

S41. Cover the drift layer and the top of the well region with a second barrier layer;

S42. Etch and expose the second barrier layer and the well region in sequence, and form a second through hole in the well region;

S43. Deposit P+Ge material in the second through hole to form a P+Ge doped region;

S44. Clear the second barrier layer;

Further, in step S5, using photolithography process and ion implantation process, the steps of forming the source region include:

S51. Cover the second strip-shaped region and the top of the P+Ge doped region with a third barrier layer;

S52. Etch and expose the third barrier layer to form a third through hole. The third through hole exposes the top outer area of the second strip-shaped area;

S53. Inject ions into the top outer region of the second strip-shaped region through the third through hole to form the source region;

S54. Clear the third barrier layer;

Furthermore, the material of the source area is SIC, and the implanted ions are phosphorus ions;

Further, in step S6, the steps of forming the source metal layer using photolithography process and deposition process include:

S61. Cover the tops of the first strip region, P+Ge doped region, and source region with a fourth barrier layer;

S62. Etch and expose the fourth barrier layer to form a fourth through hole. The fourth through hole exposes the tops of the P+Ge doped region and the source region;

S63. Deposit metal material in the fourth through hole to form a source metal layer;

S64. Clear the fourth barrier layer;

Furthermore, the source metal layer is made of nickel-copper alloy;

Further, in step S7, using a photolithography process and a deposition process, the step of forming the gate insulating layer includes: S71, covering the top and middle portion of the drift layer with a fifth barrier layer;

S72. Etch and expose the fifth barrier layer to form a fifth through hole. The fifth through hole exposes the top and middle portion of the drift layer;

S73. Deposit and form a gate insulating layer in the fifth through hole;

S74. Deposit a metal material on the top of the gate insulation layer to form a gate metal layer;

Furthermore, the material of the gate insulating layer is silicon dioxide;

Furthermore, the material of the gate metal layer is aluminum;

Furthermore, the first to fifth barrier layers are all made of silicon dioxide.

The following beneficial effects can be achieved by adopting the above structure of the present invention: the SiC MOSFET of this application is provided with a P+Ge doped region, and the P+Ge doped region and the drift layer form a heterojunction. This heterojunction serves as a parasitic body diode working mechanism. There is a carrier injection phenomenon, which can improve the freewheeling capability of the parasitic body diode. Since the conduction performance of the Ge material is better than that of the Si material in the traditional freewheeling diode, it can effectively reduce the cost of the SiC MOSFET. The conduction voltage drop of the parasitic body diode, under the condition that the conduction current remains unchanged, the reduction of the conduction voltage drop reduces the power consumption of the parasitic body diode, that is, the freewheeling loss of the parasitic body diode is reduced.

In addition, the SiC MOSFET device of this application only contains a single heterojunction formed by a P+Ge doped region and a drift layer. The conduction voltage drop of a single heterojunction is about 0.4V. Compared with the existing SiC MOSFET With two junction structures in the device, the conduction voltage drop of a single heterojunction is lower. Under the condition that the freewheeling ability of the parasitic body diode remains unchanged, the reduction of the conduction voltage drop reduces its power consumption, that is, the parasitic body diode is reduced. of freewheeling power consumption.

In the SiC MOSFET of this application, the P+Ge doped region and the drift layer form a heterojunction freewheeling path. This freewheeling path does not overlap or contact the normal conduction channel of the device. Therefore, the heterojunction has no effect on the conductive channel of the device. No impact, that is, no impact on the gate characteristics of the device, and the conduction voltage drop of this heterojunction is not affected by the conduction current of other heterojunctions or other paths, so the conduction voltage drop is highly controllable, ensuring The device conducts normally.

Description of the drawings

Figure 1 is a schematic cross-sectional structural view of the SiC MOSFET of the present invention;

Figure 2 is a schematic cross-sectional structural diagram of the well region formed in step S33 in the SiC MOSFET manufacturing process of the present invention;

Figure 3 is a schematic cross-sectional structural diagram of the P+Ge doped region formed in step S43 in the SiC MOSFET manufacturing process method of the present invention;

Figure 4 is a schematic cross-sectional structural diagram of the source region formed in step S53 in the SiC MOSFET manufacturing process of the present invention;

Figure 5 is a schematic cross-sectional structural diagram of the source metal layer formed in step S63 in the SiC MOSFET manufacturing process of the present invention;

Figure 6 is a schematic cross-sectional structural diagram of the gate insulating layer deposited in step S73 of the SiC MOSFET manufacturing process of the present invention;

Figure 7 is a schematic cross-sectional structural view of the gate deposited in step S74 in the SiC MOSFET manufacturing process of the present invention;

Figure 8 is a flow chart of the SiC MOSFET manufacturing process method of the present invention;

Reference signs: drain metal layer 1, substrate 2, drift layer 3, gate insulation layer 4, gate 5, source metal layer 6 distributed on both sides of the gate 5, P+Ge doped region 7, Well region 8, stripe region 81, L-shaped region 82, first stripe region 801, second stripe region 802, source region 9, first barrier layer 101 to fifth barrier layer 105.

Detailed ways

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only These are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of the present invention.

It should be noted that the terms "comprising" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusion, for example, a series of steps or units. The processes, methods, apparatus, products or devices are not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the processes, methods, products or devices.

See Figure 1, a SiC MOSFET with low body diode turn-on voltage, which includes a drain metal layer 1, a substrate 2, a drift layer 3, a gate insulating layer 4, a gate 5, and a distribution distribution from bottom to top. The source metal layer 6, the P+Ge doped region 7, the well region 8, and the source region 9 on both sides of the gate 5, in which the substrate 2 is a SiC substrate, the P+Ge doped region 7, and the well region 8 The source region 9 is located at the top of the drift layer 3, and the well regions 8 are located at the top areas on both sides of the drift layer 3. After the P+Ge doped region 7 penetrates the well region 8 longitudinally, the bottom end is in contact with the drift layer 3, and the well region 8 is divided into two regions: a strip region 81 and an L-shaped region 82. The source region 9 is located inside the L-shaped region 82 at right angles. The outer end of the P+Ge doped region 7 is in contact with the inner end of the strip region 81. P The inner end of the +Ge doped region 7 is in contact with the outer end of the source region 9 and the bottom side end of the L-shaped region 82. The source metal layer 6 is located at the top of the source region 9 and the P+Ge doped region 7. P+Ge doped Region 7 and drift layer 3 form a heterojunction.

The thickness of the P+Ge doped region 7 is 160 times the thickness of the thinnest part of the well region 8 (ie, the thickness of the lateral region), and the doping concentration of the P+Ge doped region 7 is one 160 times that of the well region 8 . Because the breakdown field strength of Ge material is 160 times that of SiC material, in order to ensure the reverse breakdown voltage of the device, the thickness of Ge material needs to be 160 times that of SiC material; since the thinnest part of the well region is most easily Breakdown, therefore, the thickness of the P+Ge doped region needs to be set to 160 times the thickness of the thinnest part of the well region.

The L-shaped region 82 includes a vertical region and a lateral region. The thickness of the vertical region ranges from 200 nm to 400 nm. In this embodiment, 300 nm is preferred. The thickness of the lateral region ranges from 20 nm to 50 nm. In this embodiment, the thickness of the lateral region ranges from 30 nm. That is, it is the thickness of the thinnest part of the well region 8, and the thickness of the source region 9 is the difference between the thickness of the lateral region and the vertical region. This application effectively ensures that the thickness of the P+Ge doped region is 160 times the thickness of the thinnest part of the well region by limiting the thickness range of the vertical region, lateral region, and source region.

The doping concentration of the well region 8 is 6×1017cm-3~1.2×1018cm-3, the doping concentration of the source region 9 is 1×1018cm-3~2×1018cm-3; the drift layer 3 is an N+SiC doped area , the P+Ge doped region 7 and the N+SiC doped region form a heterojunction. The junction barrier of the heterojunction is smaller than the junction barrier of the SiC pn junction. Therefore, the parasitic body diode of the SiC MOSFET of the present application is turned on. The voltage drop is smaller than the conduction voltage drop of the traditional parasitic body diode. The conduction voltage drop of the parasitic body diode of the SiC MOSFET in this application (that is, the conduction voltage drop of the heterojunction) is 0.4V.

A process method for manufacturing the above-mentioned SiC MOSFET, referring to Figure 8, the method includes:

S1. Provide a substrate 2;

S2. Deposit the drain metal layer 1 on the bottom of the substrate 2. The material of the drain metal layer is nickel-titanium alloy, and epitaxially grow the drift layer 3 on the top of the substrate 2;

S3. Inject ions into the tops of both sides of the drift layer to form the well region 8. The specific steps include:

S31. Cover the first barrier layer 101 on the top of the drift layer 3. The material of the first barrier layer 101 is silicon dioxide;

S32. Etch and expose the first barrier layer 101 to form a first through hole. The first through hole exposes the top ends of both sides of the drift layer 3;

S33. Use an ion implantation process to inject boron (B) ions into the tops of both sides of the drift layer through the first through hole to form a well region. The material of well region 8 is SiC, refer to Figure 2;

S34. Use wet cleaning to remove the first barrier layer 101;

S4. Etch the middle portion of the well region 8 near the outer edge to form a second through hole penetrating the well region 8. The second through hole divides the well region 8 into two strip-shaped regions: a first strip-shaped region 801 and a second strip-shaped region 801. In the two strip regions 802, P+Ge material is deposited in the second through hole to form the P+Ge doped region 7. The specific steps include:

S41. Cover the drift layer 3 and the top of the well region 8 with the second barrier layer 102. The material of the second barrier layer 102 is silicon dioxide;

S42. Etch and expose the second barrier layer 102 and the well region 8 sequentially to form a second through hole in the well region 8;

S43. Deposit P+Ge material in the second through hole to form P+Ge doped region 7, refer to Figure 3;

S44. Use a wet cleaning method to remove the second barrier layer 102.

S5. Inject ions into the top outer region of the second strip region 802 to form a source region. Specific steps include:

S51. Cover the second stripe region 802 and the top of the P+Ge doped region with the third barrier layer 103. The material of the third barrier layer 103 is silicon dioxide;

S52. Etch and expose the third barrier layer 103 to form a third through hole. The third through hole exposes the top outer area of the second strip area 802;

S53. Inject phosphorus (i.e., P) ions into the top outer region of the second strip-shaped region 802 through the third through hole to form the source region 9. The material of the source region is SiC. Refer to Figure 4;

S54. Clear the third barrier layer 103.

S6. Deposit the source metal layer 6 on the top of the source region 9 and the P+Ge doped region 7. The specific steps include: S61. On the top of the first strip region 801, the P+Ge doped region 7 and the source region 9 Covering the fourth barrier layer 104, the material of the fourth barrier layer 104 is silicon dioxide;

S62. Etch and expose the fourth barrier layer 104 to form a fourth through hole. The fourth through hole exposes the tops of the P+Ge doped region 7 and the source region 9;

S63. Deposit a metal material in the fourth through hole to form the source metal layer 6. The metal material of the source metal layer is nickel-copper alloy (ie, Ni-Cu). Refer to Figure 5;

S64. Use a wet cleaning method to remove the fourth barrier layer 104.

S7. Deposit gate insulating layer 4 and gate 5 sequentially on the top and middle of the drift layer. Specific steps include:

S71. Cover the top of the drift layer 3 and the outer surface of the source metal layer 6 with the fifth barrier layer 105. The material of the fifth barrier layer 105 is silicon dioxide;

S72. Etch and expose the fifth barrier layer 105 to form a fifth through hole. The fifth through hole exposes the top and middle portion of the drift layer 3;

S73. Deposit and form a gate insulating layer 4 in the fifth through hole. The material of the gate insulating layer is silicon dioxide. Refer to Figure 6;

S74. Deposit a metal material on the top of the gate insulating layer 4. The metal material is aluminum to form the gate 5. Refer to Figure 7.

To sum up, in this application, by limiting the thickness range of the vertical region, lateral region, and source region, the source metal layer 6 covers the top of the source region 9 and the P+Ge doped region 7, and is connected to the source region 9 and the P+ doped region 7 respectively. The Ge doped region 7 forms an ohmic contact, the P+Ge doped region extends into the drift layer, forms an ohmic contact with the source metal through the drift layer, and forms a heterojunction with the N+SiC doped region of the drift layer. , ensuring the forward conduction characteristics and reverse withstand voltage characteristics of SiC MOSFET devices.

Currently commonly used SiC MOSFET devices generally include two junction structures. For example, the two junction structures are: P+Ge doped region (ie, P-type Ge epitaxial region) and P+SiC doped region (ie, P+SiC injection region). The heterojunction, P+SiC and pn junction in the drift region have different conduction voltage drops (the conduction voltage drop of the heterojunction is about 0.4V, and the conduction voltage of the pn junction is about 1.4V. The total conduction voltage drop is about 1.8V, the power consumption of the parasitic body diode P=18V*I, where I is the conduction current of the parasitic body diode), and there is a low-resistance path between the two heterojunctions, making the two A conduction current flowing along a low-resistance path is generated between the heterojunctions (for example, the current between the P+SiC injection region, the P-type Ge epitaxial region, and the P-well injection region). This conduction current accounts for the proportion of the body diode current. is: one-fifth to one-third. This ratio is affected by the lateral structure width of the device and the doping concentration of the drift layer and well region. The existence of this conduction current not only increases the internal loss of the device, but also has a voltage division As a result, the conduction voltage drop of the heterojunction is affected, and the conduction voltage drop cannot reach the preset conduction voltage threshold and affects the normal conduction of the freewheeling diode, thus affecting the normal conduction of the SiC MOSFET device. Pass.

The SiC MOSFET device in this application only contains one heterojunction. Compared with the existing two heterojunction structures, the arrangement of a single heterojunction in this application simplifies the device structure, reduces the size, and reduces the manufacturing process of the entire device. The process is also more simplified, and a single heterojunction in this application has no impact on the gate characteristics of the device and will not affect the normal conduction of the gate. The reason is that the heterojunction freewheeling path in this application (that is, through the source metal layer in sequence) , source region, P+Ge doped region, drift layer, SiC substrate, and the freewheeling path formed by the drain metal layer) and the normal conduction channel of the SiC MOSFET device (that is, through the gate metal layer and the gate insulating layer in sequence , drift layer, SiC substrate, and drain metal layer) do not overlap or contact. Therefore, this heterojunction has no effect on the conductive channel of the device, that is, it has no effect on the gate characteristics of the device. In addition, the conduction voltage drop of the heterojunction formed by the P+Ge doped region 7 and the drift layer 3 in this application is not affected by the conduction current of other heterojunctions or other paths, so the conduction voltage drop is highly controllable, thereby Ensure that the device is conducting normally.

In the SiC MOSFET device of the present application, the heterojunction formed by the P+Ge doped region 7 and the drift layer 3 and the parameters of each structural layer (thickness of the P+Ge doped region, doping concentration of the P+Ge doped region, well The improvement of the doping concentration of the P+Ge doped region, the doping concentration of the source region, the vertical region thickness range, the lateral region thickness range, and the source region thickness) effectively ensures that the thickness of the P+Ge doped region is the thickness of the thinnest part of the well region 160 times, reducing the risk of breakdown in the thinnest part of the well region, that is, avoiding the reverse withstand voltage degradation problem of SiC MOSFET that may be caused by changes in the heterojunction structure, and ensuring the reverse withstand voltage characteristics of SiC MOSFET devices. In addition, the above improvements ensure that the conduction voltage drop of the parasitic body diode (i.e. heterojunction) in SiC MOSFET devices is maintained at around 0.4V, and the conduction current I of the parasitic body diode remains unchanged (i.e. the freewheeling capability remains unchanged). According to the power It can be seen from the power consumption calculation formula P=U*I that under the condition that the current I remains unchanged, compared with the power consumption of the existing two-junction structure with a conduction voltage drop U=1.8V, the freewheeling power of the parasitic diode of this application is Consumption is significantly reduced.

It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or equivalently substituted to achieve the same technical effect; as long as the requirements for use are met, they are all within the protection scope of the present invention.

Claims (9)

1. The SiCNOSFET comprises a drain metal layer (1), a substrate (2), a drift layer (3), a gate insulating layer (4), a gate (5) and source metal layers (6) distributed on two sides of the gate (5) from bottom to top, and is characterized by further comprising a P+ Ge doped region (7), a well region (8) and a source region (9), wherein the P+ Ge doped region (7), the well region (8) and the source region (9) are positioned in the drift layer (3), the well region (8) is positioned in the top areas on two sides of the drift layer (3), the P+ Ge doped region (7) and the source region (9) are positioned in the well region (8), and the P+ Ge doped region (7) longitudinally penetrates through the well region (8) and then contacts the drift layer (3) and divides the well region (8) into two areas: the source region (9) is positioned on the right-angle inner side of the L-shaped region (82), the outer side end of the P+ Ge doped region (7) is contacted with the inner side end of the strip-shaped region (81), the inner side end of the P+ Ge doped region (7) is contacted with the outer side end of the source region (9) and the bottom side end of the L-shaped region (82), the source metal layer (6) is positioned on the top ends of the source region (9) and the P+ Ge doped region (7) and forms ohmic contact with the source region (9) and the P+ Ge doped region (7) respectively, and the P+ Ge doped region (7) and the drift layer (3) form a heterojunction;

the substrate (2) is a SiC substrate, the thickness of the P+Ge doped region (7) is 160 times of the thickness of the thinnest part of the well region (8), and the doping concentration of the P+Ge doped region (7) is 160 times of the thickness of the well region (8).

2. The SiCMOSFET as claimed in claim 1, characterized in that the doping concentration of the well region (8) is 6 x 1017cm ^-3 ~1.2×1018cm ^-3 The doping concentration of the source region (9) is 1X 1018cm ^-3 ~2×1018cm ^-3 。

3. The SiCMOSFET as claimed in claim 1, characterized in that the drift layer (3) is an n+ SiC doped region, the p+ Ge doped region (7) forming a heterojunction with the n+ SiC doped region.

4. The SiCMOSFET of claim 1, wherein the L-shaped region (82) comprises a vertical region having a thickness in the range of 200nm to 400nm, a lateral region having a thickness in the range of 20nm to 50nm, and a source region (9) having a thickness that is the difference between the lateral region and the vertical region.

5. A process for fabricating a SiCMOSFET in accordance with claim 1, comprising:

s1, providing a substrate (2);

s2, depositing a drain metal layer (1) at the bottom end of the substrate (2), and epitaxially growing a drift layer (3) at the top end of the substrate (2);

s3, injecting ions into the tops of two sides of the drift layer (3) to form a well region (8);

s4, etching the position, close to the outer edge, of the middle part of the well region (8) to form a second through hole penetrating through the well region (8), and dividing the well region (8) into two strip-shaped regions by the second through hole: a first strip-shaped region (801) and a second strip-shaped region (802), and a P+Ge doped region (7) is epitaxially grown in the second through hole;

s5, implanting ions into the outer side area of the top end of the second strip-shaped area (802) to form a source area (9);

s6, depositing a source metal layer (6) at the top ends of the source region (9) and the P+Ge doped region (7);

and S7, sequentially depositing a gate insulating layer (4) and a gate (5) at the middle part of the top end of the drift layer (3).

6. The method for fabricating a SiCMOSFET according to claim 5, wherein in step S3, the well region (8) is formed by using a photolithography process and an ion implantation process, the steps comprising:

s31, covering a first barrier layer (101) on the top end of the drift layer (3);

s32, etching exposure is carried out on the first barrier layer (101) to form a first through hole, and the top ends of two sides of the drift layer (3) are exposed by the first through hole;

s33, implanting ions into the tops of the two sides of the drift layer (3) through the first through hole by adopting an ion implantation process to form the well region (8);

s34, removing the first barrier layer (101).

7. The method according to claim 6, wherein in step S4, the step of forming the p+ge doped region (7) by using a photolithography process and a deposition process comprises:

s41, covering a second barrier layer (102) on the top ends of the drift layer (3) and the well region (8);

s42, sequentially etching and exposing the second barrier layer (102) and the well region (8), and forming a second through hole in the well region (8);

s43, depositing a P+Ge material in the second through hole to form a P+Ge doped region (7); s44, removing the second barrier layer (102).

8. The process for manufacturing a SiCNMOSFET as in claim 7, wherein

In step S5, the step of forming the source region by using a photolithography process and an ion implantation process includes:

s51, covering a third barrier layer (103) on the top ends of the second strip-shaped region (802) and the P+ Ge doped region (7);

s52, etching and exposing the third barrier layer (103) to form a third through hole, wherein the third through hole exposes the top outer side area of the second strip-shaped area (802);

s53, implanting ions into the top outer side area of the second strip-shaped area (802) through the third through hole to form the source area (9);

s54, removing the third barrier layer (103).

9. The method of manufacturing a SiCMOSFET according to claim 8, wherein in step S6, the step of forming the source metal layer (6) using a photolithography process and a deposition process comprises:

s61, covering a fourth barrier layer (104) on the top ends of the first strip-shaped region (801), the P+Ge doped region (7) and the source region (9);

s62, etching exposure is carried out on the fourth barrier layer (104) to form a fourth through hole, and the top ends of the P+Ge doped region (7) and the source region (9) are exposed through the fourth through hole;

s63, depositing a metal material in the fourth through hole to form a source metal layer (6); s64, removing the fourth barrier layer;

in step S7, the step of forming the gate insulating layer by using a photolithography process and a deposition process includes:

s71, covering a fifth barrier layer (105) on the middle part of the top end of the drift layer (3);

s72, etching exposure is carried out on the fifth barrier layer (105) to form a fifth through hole,

a fifth through hole exposes a top end middle part of the drift layer (3);

s73, depositing and forming a gate insulating layer (4) in the fifth through hole;

and S74, depositing a metal material on the top end of the gate insulating layer (4) to form a gate (5).