CN116580728A

CN116580728A - ROM output control circuit and method

Info

Publication number: CN116580728A
Application number: CN202310861066.9A
Authority: CN
Inventors: 张武; 刘华; 王建军; 卢昌鹏
Original assignee: Shanghai Hailichuang Technology Co ltd
Current assignee: Shanghai Hailichuang Technology Co ltd
Priority date: 2023-07-14
Filing date: 2023-07-14
Publication date: 2023-08-11

Abstract

The invention discloses a ROM output control circuit and a method, wherein the circuit comprises: a memory cell and an inverter; the memory cell includes a word line and a bit line, the word line is kept in an activated state when charged, and a voltage of the bit line is determined by information of the memory cell; the inverter is connected to the bit line to read a voltage of the bit line as information of the memory cell. The invention reduces the complexity of the ROM control circuit, reduces the power consumption, improves the data reading speed and saves the area of a silicon chip, thereby realizing the purpose of low cost; the reading circuit method of the invention does not need an extra high-precision reading amplifier circuit and a complex time sequence control circuit, and can realize the direct reading of data by using a simple time sequence control circuit and an NOT gate, thereby realizing the purposes of high data reading speed, small power consumption, small area of an output control unit and low production cost.

Description

ROM output control circuit and method

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a ROM output control circuit and method.

Background

ROM read-only memory can stably store data, has a simple structure and is convenient to use, and is often used for storing various fixed programs and data. Technicians typically cure programs in the ROM to complete power-on self-test of the system, initialization of functional modules in the system, drivers for basic input/output of the system, and booting the operating system.

The conventional ROM mainly comprises an address decoder, a memory bank and an output control circuit, wherein the output control circuit is an important point in circuit design and relates to sequential logic, power consumption, data reading speed and the like of the ROM. Currently, as described in chinese patent publication No. CN102903382a, the output control circuit flow of the ROM generally pre-charges the bit line to a certain voltage, then selects a word line, activates a sense amplifier, and reads the data stored in the memory cell. The traditional ROM output control circuit has the problems of long flow and period and complex sequential logic, and if multiple paths of data are output simultaneously, a plurality of high-precision amplifier circuits are also needed to be matched for use, so that the problems of slower data reading speed, larger power consumption, large area of an output control unit, high production cost and the like can be faced.

Therefore, a simple ROM output control circuit and method are needed to solve the problem of insufficient ROM data reading.

Disclosure of Invention

The invention aims to provide a ROM output control circuit and a ROM output control method, which are used for solving the problem that ROM data reading is not fast enough.

In order to solve the technical problems, the invention provides a ROM output control method, which keeps the activation state of a word line when a memory cell is charged.

Furthermore, the memory cell is directly selected to be charged through the decoding circuit.

Further, the data stored in the memory cell is read through an inverter.

Further, the inverter is a two-stage inverter.

Further, the two-stage inverter includes a first NOT gate, a second NOT gate, and a third NOT gate, the second NOT gate and the third NOT gate forming a latch, an output of the first NOT gate being connected to an input of the latch.

Further, when the information stored in the memory cell is "1", the bit line can be charged high.

Further, when the information stored in the memory cell is "0", the bit line cannot be charged high.

Further, the storage unit is a storage unit of a mask ROM.

The invention also provides a ROM output control method, which comprises the following steps:

directly selecting and charging a memory cell, wherein the memory cell comprises a word line and a bit line, and the word line is kept in an activated state during charging;

determining a voltage of the bit line according to information of the memory cell;

and reading the voltage of the bit line as the data of the memory cell.

The present invention also provides a ROM output control circuit including: a memory cell and an inverter; the memory cell includes a word line and a bit line, the word line is kept in an activated state when charged, and a voltage of the bit line is determined by information of the memory cell; the inverter is connected to the bit line to read a voltage of the bit line as information of the memory cell.

Further, the inverter is a two-stage inverter.

Compared with the prior art, the invention has at least the following beneficial effects:

when the memory cell is charged, the word line is directly opened without a precharge process, so that the memory cell can be charged and discharged, and the time for reading data is shortened.

Furthermore, the data is directly read through the inverter, so that the output control flow is simplified, and the area of an output control unit is reduced.

Drawings

FIG. 1 is a schematic diagram of a ROM base memory cell in one embodiment of the invention;

FIG. 2 is a schematic diagram of reading data "0" in one embodiment of the invention;

FIG. 3 is a schematic diagram of reading data "1" in one embodiment of the invention;

FIG. 4 is a schematic diagram of a ROM output control circuit in an embodiment of the invention;

FIG. 5 is a flow chart of a ROM output control method of the present invention;

FIG. 6 is a simulated waveform diagram in an embodiment of the invention.

Detailed Description

A ROM output control circuit and method of the present invention will be described in more detail below with reference to the drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the beneficial effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.

The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Example 1

As shown in fig. 5, an embodiment of the present invention proposes a ROM output control method that directly turns on a word line when a memory cell is charged.

In one specific example, the memory cells are directly selected for charging by the decoding circuit, and the word lines are directly turned on when the memory cells are charged. Discharging is performed while charging the memory cell, shortening the waiting time from the completion of charging to discharging.

In a specific example, please refer to fig. 1, the memory cell is a memory cell of a mask ROM.

In a memory array of a ROM, a plurality of bit lines bl (bit lines) and word lines wl (word lines) are provided, and intersections of the bit lines bl and the word lines wl are memory cells.

Next, please refer to fig. 2-3, the data stored in the memory cell is directly read.

Specifically, the data stored in the storage unit can be read by setting an inverter and a latch, or can be read by other means, such as setting a sense amplifier, etc., so that a person skilled in the art can select the data according to specific needs in different practical application scenarios.

In a specific example, when the information stored in the memory cell is "0", the bit line bl cannot be charged high, and the data stored in the memory cell is read out to be "0" through the action of the inverter.

In a specific example, when the information stored in the memory cell is "1", the bit line bl can be charged high, and the data stored in the memory cell is read out to be "1" through the action of the inverter.

Referring to fig. 4, in a specific example, the ROM selects a memory cell in the memory array through the decoding circuit to charge, and for the case that the data stored in the memory cell is "1", the word line wl (1) is kept in an open state, and the bit line bl can be charged high, i.e. is "1", so that the node a is "0", the node B is "1", the node C is "0", and finally the output DOUT is "1", i.e. the data stored in the memory cell is "1" through the effect of the inverter. In this example, by turning on the word line wl (1) at the start of charging, charging and discharging of the memory cells in the memory array are performed in parallel, simplifying the flow of reading ROM memory data, and shortening the time required for reading data.

With continued reference to fig. 4, in a specific example, the ROM selects a memory cell in the memory array through the decoding circuit to charge, and for the case that the data stored in the memory cell is "0", the word line wl (0) is kept in an open state, and the bit line bl cannot be charged high, i.e. is "0", so that the node a is "1", the node B is "0", the node C is "1", and finally the output DOUT is "0", i.e. the data stored in the memory cell is "0" through the effect of the inverter.

In this example, by turning on the word line wl (0) at the start of charging, charging and discharging of the memory cells in the memory array are performed in parallel, simplifying the flow of reading ROM memory data, and shortening the time required for reading data.

Further, in this example, the data stored in the memory cell is read through the inverter, and the structure is simple and reasonable. The embodiment does not need to additionally arrange a high-precision sense amplifier circuit and a complex time sequence control circuit, and can directly read data through a simple time sequence control circuit and an NOT gate.

According to the ROM output control method, when multiple paths of data are simultaneously output, a plurality of high-precision amplifier circuits are not required to be additionally arranged for matching use, so that the data reading speed of a product can be effectively improved, the power consumption and the area of an output control unit are reduced, the area of a silicon wafer is saved, the purpose of low cost is achieved, and the production cost can be reduced.

Example two

Referring to fig. 5, a second embodiment of the present invention provides a ROM output control method, including:

s1, directly selecting and charging a memory cell, wherein the memory cell comprises a word line, and the word line is kept in an activated state during charging;

s2, determining the voltage of the bit line according to the information of the storage unit;

s3, reading the voltage of the bit line as the data of the memory cell.

In a specific example, in step S1, the ROM is charged without precharging, but rather the word line is selected and turned on directly by the decoding circuit.

Referring to fig. 2, in step S2, for the case where the data stored in the memory cell is "0", the word line is kept in an open state, and the bit line bl cannot be charged high, i.e., is "0".

In addition, referring to fig. 3, in the case where the data stored in the memory cell is "1", the word line is kept in an open state, and the bit line bl can be charged high, i.e., "1".

With continued reference to fig. 2-3, for step S3, the bit line bl is "0", the final output DOUT is "0", and the bit line bl is "1", the final output DOUT is "1".

Referring to fig. 4, for example, in the case where the bit line bl is "1", the node a is "0", the node B is "1", the node C is "0", and the final output DOUT is "1", that is, the data stored in the read memory cell is "1" through the effect of the inversion unit.

For the case that the data stored in the storage unit is "0", the node a is "1", the node B is "0", the node C is "1", and finally the output DOUT is "0", that is, the data stored in the read storage unit is "0" through the actions of the inversion unit and the storage unit.

In this embodiment, by turning on the word line wl at the start of charging, charging and discharging of the memory cells in the memory array are performed in parallel, simplifying the flow of reading the ROM memory data, and shortening the time required for reading the data.

Further, in this embodiment, step S3 may read the data stored in the memory cell through the inverter, so that the structure is simple and reasonable. The embodiment does not need to additionally arrange a high-precision sense amplifier circuit and a complex time sequence control circuit, and can directly read data through a simple time sequence control circuit and an NOT gate.

Example III

Referring to fig. 2-4, a third embodiment of the present invention provides a ROM output control circuit, including: a memory cell and an inverter; the memory cell includes a word line and a bit line, the word line is kept in an activated state when charged, and a voltage of the bit line is determined by information of the memory cell; the inverter is connected to the bit line to read a voltage of the bit line as information of the memory cell.

Specifically, the inverter is a two-stage inverter.

Preferably, the two-stage inverter comprises a first not gate, a second not gate and a third not gate, the second and third not gates constituting a latch, the output of the first not gate being connected to the input of the latch.

In this embodiment, fig. 4 illustrates a specific structure of the inverter, and it is understood that those skilled in the art can flexibly adjust the inverter based on the concept of the present invention.

The ROM output control circuit comprises the storage unit and the inverter, has a simple structure, can effectively improve the data reading speed of products, reduces the power consumption and the area of the output control unit, and saves the area of a silicon wafer, thereby realizing the purpose of low cost and reducing the production cost.

The method and the corresponding circuit of the embodiment of the invention are adopted under the 180 nanometer process, the simulation waveform diagram is shown in fig. 6, the word line wl (0) and the word line wl (1) are kept in an open state from beginning, the charge and the discharge of the memory cells in the memory array are performed in parallel, the reading of the data stored in the memory cells is completed only through 9.483ns, and the purpose of quickly reading the data stored in the ROM is realized.

In summary, according to the ROM output control circuit and the ROM output control method, the word line is opened at the beginning of charging, so that the charging and discharging of the memory cells in the memory array are performed in parallel, the process of reading ROM stored data is simplified, and the time required for reading data is shortened. In addition, the ROM output control circuit and the ROM output control method can realize the direct data reading through a simple time sequence control circuit and an NOT gate, and realize the purposes of high data reading speed, small power consumption, small area of an output control unit and low production cost.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A ROM output control method is characterized in that the activation state of a word line is maintained when a memory cell is charged.

2. The ROM output control method of claim 1, wherein the memory cells are directly selected for charging by a decoding circuit.

3. The ROM output control method of claim 1, wherein the data stored by the memory cell is read through an inverter.

4. A ROM output control method according to claim 3, wherein the inverter is a two-stage inverter.

5. The ROM output control method of claim 4, wherein the two-stage inverter comprises a first not gate, a second not gate, and a third not gate, the second not gate and the third not gate constituting a latch, an output of the first not gate being connected to an input of the latch.

6. The ROM output control method of claim 1, wherein the bit line can be charged high when the information stored in the memory cell is "1".

7. The ROM output control method of claim 1, wherein the bit line cannot be charged high when the information stored in the memory cell is "0".

8. The ROM output control method of claim 1, wherein the memory unit is a memory unit of a mask ROM.

9. A ROM output control method, characterized by comprising:

and reading the voltage of the bit line as the data of the memory cell.

10. A ROM output control circuit, characterized by comprising: a memory cell and an inverter; the memory cell includes a word line and a bit line, the word line is kept in an activated state when charged, and a voltage of the bit line is determined by information of the memory cell; the inverter is connected to the bit line to read a voltage of the bit line as information of the memory cell.

11. The ROM output control circuit of claim 10, wherein the inverter is a two-stage inverter.

12. The ROM output control circuit of claim 11, wherein the two-stage inverter comprises a first not gate, a second not gate, and a third not gate, the second not gate and the third not gate constituting a latch, an output of the first not gate being connected to an input of the latch.