CN116566778B - All-digital single-carrier symbol timing synchronization method under any oversampling ratio - Google Patents
All-digital single-carrier symbol timing synchronization method under any oversampling ratioInfo
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- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0036—Correction of carrier offset using a recovered symbol clock
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Abstract
A full digital single carrier symbol timing synchronization method under any oversampling ratio belongs to the field of communication signal processing. The method comprises the steps of carrying out DFT conversion on received signal sampling points to a frequency domain, carrying out matched filtering processing on signals through point-by-point multiplication of the frequency domain, then estimating symbol timing deviation of the signals by adopting a Godard method, driving a numerical control oscillator after the estimation result passes through a loop filter, determining sliding of the sampling points and frequency domain compensation of the timing deviation through phase accumulation and overflow of the numerical control oscillator, calculating the length of a frequency domain aliasing area and an IDFT according to an over-sampling rate, converting the signal sampling points to a time domain through the IDFT, obtaining recovered symbols, realizing all-digital single carrier symbol timing synchronization under any over-sampling multiplying power, and adapting to any over-sampling rate. The invention is suitable for the field of communication signal processing and is used for expanding the application range of a single carrier system.
Description
Technical Field
The invention relates to a full-digital single-carrier symbol timing synchronization method for a single-carrier signal, in particular to a full-digital single-carrier symbol timing synchronization method under any oversampling ratio, and belongs to the field of communication signal processing.
Background
Single carrier communication is one of the most important transmission modes in a communication system, and signals such as MPSK, MAPSK, QAM are widely used in single carrier systems. Under the application scene of high speed and large bandwidth, the modulation modes such as MPSK, MAPSK, QAM and the like are widely applied in a broadband single-carrier system due to a simpler mapping/demapping method, better power efficiency and stronger adaptability of the single-carrier system to carrier frequency offset and phase noise.
Different from the corresponding Orthogonal Frequency Division Multiplexing (OFDM) system, the single carrier system has stronger tolerance capability to carrier frequency offset and phase noise, but the precision requirement to symbol timing synchronization is far greater than that of the OFDM system, and especially in the case of high-order modulation such as 16/64QAM, and the like, the tiny symbol timing deviation can bring great error rate deterioration. In addition, in a large bandwidth scenario, due to the performance limitations of the existing analog-to-digital conversion (a/D) and digital-to-analog conversion (D/a) devices, in a wideband signal of up to several GHz and even tens of GHz, only a receiver architecture with zero intermediate frequency can be adopted, so that the analog signal can be completely acquired even at a lower oversampling rate, but the oversampling rate cannot be guaranteed to be an integer multiple of the symbol rate, which makes many classical symbol timing synchronization methods ineffective.
The common single carrier symbol timing deviation estimation method with better performance mainly comprises Godard algorithm, gardner algorithm, O & M algorithm and the like, and the corresponding compensation methods comprise a Farrow interpolation method based on Lagrange interpolation, a triangular interpolation method and a method for converting the frequency domain into time domain extraction after the frequency domain compensation. These compensation methods all require operation at 2 times and above the oversampling rate and therefore fail to operate properly in low oversampling systems under zero intermediate frequency architecture.
Disclosure of Invention
Aiming at the problem of limited application range of the over-sampling rate in the existing single carrier system, the main purpose of the invention is to provide a full digital single carrier symbol timing synchronization method under any over-sampling multiplying power, which is to convert signals into a frequency domain by using a Discrete Fourier Transform (DFT), estimate symbol timing deviation in the frequency domain and compensate by using frequency domain phase characteristics, then to realize the extraction process on the frequency domain by using the length randomness of the DFT and a frequency domain pre-mixing method, and finally to convert frequency domain signals into a time domain by using an Inverse Discrete Fourier Transform (IDFT) to finish symbol timing synchronization. The invention can avoid complex interpolation processing of the traditional method, can adapt to any rational multiple oversampling relation, and is particularly suitable for low oversampling rate. The full digital architecture is convenient for the realization of the FPGA, can be completely decoupled with the front-end radio frequency module, is suitable for any receiver architecture with any oversampling multiplying power, and can expand the application range of a single carrier system.
The invention aims at realizing the following technical scheme:
The invention discloses a full-digital single-carrier symbol timing synchronization method under any oversampling multiplying power, which is characterized in that a received signal sampling point is subjected to DFT conversion to a frequency domain, the signal is subjected to matched filtering processing by multiplying the frequency domain point by point, symbol timing deviation of the signal is estimated by adopting a Godard method after matched filtering, a Numerical Control Oscillator (NCO) is driven after an estimation result passes through a loop filter, sliding of the sampling point and frequency domain compensation of the timing deviation are determined through phase accumulation and overflow of the NCO, the length of a frequency domain aliasing area and the length of an IDFT are calculated according to the oversampling rate, the signal sampling point is converted to a time domain through the IDFT, and a recovered symbol is obtained. Since the lengths of DFT and IDFT are arbitrarily set, an arbitrary multiple of the oversampling rate can be accommodated. All operations are performed in a digital signal domain, so that all digital single carrier symbol timing synchronization under any oversampling multiplying power can be realized, and the application range of a single carrier system is expanded.
The invention discloses a full-digital single-carrier symbol timing synchronization method under any oversampling ratio, which comprises the following steps:
and 1, sampling a received signal through an analog-to-digital converter (ADC), and performing quadrature frequency conversion to zero frequency to obtain an orthogonal zero frequency signal. The over-sampling rate of the ADC is N/M times the symbol rate, where N > M. And storing the data into a memory, and selecting and outputting the sampled data in batch according to the output bias control signal by the data in the subsequent memory.
And 2, performing DFT conversion on the received signal, wherein the conversion length is integer multiple of N, namely N multiplied by L, and L is a positive integer, so as to obtain a corresponding frequency domain signal, and the output data length of the memory in the step 1 is N multiplied by L.
The frequency domain signal obtained after n×l point DFT conversion is X (k), k=0, 1..nl-1, and the roll-off factor of the transmitting-end shaping filter is α, and the effective signal is
And carrying out matched filtering processing on the effective signals in a frequency domain, wherein the matched filtering is in a convolution form in a time domain, and is in a point-by-point multiplication form in the frequency domain. The frequency domain of the matched filtering is expressed as G (k), and the filtered frequency domain signal is obtained after the point-by-point multiplication of the G (k) and the X s (k)
Y(k)=Xs(k)G(k)
Where k=0, 1, NL-1.
Step 3, compensating the timing deviation of the frequency domain signal Y (k) subjected to the matched filtering in the step 2, wherein the timing deviation to be compensated is that
The method of multiplying the frequency domain point by point is adopted, and the corrected frequency domain signal is
Step 4, correcting the frequency domain signal after the timing deviation in the step 3Timing deviation estimation is performed.
Step 4.1 first forPerforming cyclic shift to obtain
Here, |·| NL denotes a cyclic shift of the NL point.
Step 4.2 pairAnd (3) withIs multiplied point by the conjugate of (2) to obtain
All components of Z (k) here contain timing synchronization bias values.
Step 4.3 summing all components of Z (k) and taking the phase to obtain a symbol timing offset estimate for maximum signal-to-noise ratio
In the middle ofTo obtain complex phaseThe range of the values of (C) is [ -pi, pi).
Step 4.4 for convenience of subsequent treatmentNormalization processing is carried out to obtain
Here, theThe range of values of [ -0.5, 0.5) represents the relative value of the symbol timing offset estimate for one symbol duration.
Step5, the normalized symbol timing deviation obtained in the step 4And the noise is fed into a second-order loop filter, and the influence of noise in symbol timing deviation estimation can be reduced through the loop filter.
And 6, driving the NCO by a loop output result, judging whether the NCO has positive overflow, negative overflow or no overflow, and determining the offset of output data of the front-end memory according to whether the NCO overflows or not and the overflow direction. While the residual amount of NCO will be used as the timing synchronization bias compensation amount.
Step 6.1 Loop Filter result isThe cumulative value of NCO is
Step 6.2, after finishing one accumulation, judging the current NCO value, wherein the threshold is
Step 6.3, memory offset control index amount O (i) satisfying
The value of O (i) determines whether the corresponding data block is additionally advanced by 1 sample point, i.e., O (i) = -1, or additionally delayed by 1 sample point, i.e., O (i) =1, or is not subjected to additional offset processing, i.e., O (i) =0, when the data block is fetched from the memory next time.
And 6.4, after O (i) is calculated, overflow updating is carried out on NCO:
then the overflow updated NCO (i) is obtained and will be taken as In step 3, compensation is performed.
Step 7, the signals in the step 3 are processedAnd carrying out frequency domain aliasing processing.Is NL, and the length of the signal S (n) after the mixing is ML. The aliasing process satisfies
Step 8, performing IDFT with length of ML on S (n):
s(n)=IDFT(S(n))ML
s (n) is the final recovered symbol.
And 9, returning to the step 1, controlling the output data position of the (i+1) th memory according to the O (i) obtained in the step 6, and performing loop iteration to continuously obtain the recovered symbol. As N, M in the process can be selected at will, the steps can be suitable for signals under any oversampling multiplying power, and the application range of a single carrier system is enlarged.
The beneficial effects are that:
1. The invention discloses a full-digital single-carrier symbol timing synchronization method under any oversampling multiplying power, which is characterized in that DFT (discrete Fourier transform) is carried out on an input signal to a frequency domain, matched filtering, timing deviation compensation, timing deviation estimation and frequency domain aliasing extraction are completed in the frequency domain, and frequency domain signals are converted to a time domain through IDFT to complete frequency domain timing synchronization. In the processing process, the read-write offset of the buffer data of the front-end memory is accurately controlled through the accumulated overflow value of the NCO, so that the accurate tracking of sampling clock deviation signals is realized.
2. The full-digital single-carrier symbol timing synchronization method under any oversampling ratio can carry out symbol timing deviation estimation at any oversampling ratio in a frequency domain by utilizing Godard method, greatly improves adaptability of symbol synchronization and expands application range of a single-carrier system.
3. The invention discloses a full-digital single-carrier symbol timing synchronization method under any oversampling ratio, which essentially belongs to parallel signal processing in the processes of DFT and IDFT processing of memory output and can arbitrarily expand parallelism. When the processing clock of the logic device is limited and the symbol rate is too high, the logic device can still work normally, and symbol synchronization under ultra-high speed is realized.
4. The full-digital single-carrier symbol timing synchronization method under any oversampling multiplying power can replace the extraction process in the traditional time domain method by configuring DFT and IDFT with different lengths and combining the frequency domain aliasing process. Especially under non-integer times of oversampling, the traditional time domain decimation needs to face the process of polyphase filtering, and the method is not affected.
5. The all-digital single-carrier symbol timing synchronization method under any oversampling multiplying power disclosed by the invention has the advantages that all processing is performed in the frequency domain, so that frequency domain equalization which is largely adopted in high-speed communication can be directly applied to the method, additional DFT and IDFT processing is not needed, and the resource consumption can be greatly reduced from the whole system.
Drawings
Fig. 1 is a block diagram of an all-digital single-carrier symbol timing synchronization method under an arbitrary oversampling ratio disclosed in this embodiment;
FIG. 2 is a graph showing the power spectrum of a signal received when the sampling clock deviation is 1× -4, wherein the graph shows that the roll-off factor is 0.125, the signal-to-noise ratio E b/N0 is 31dB in a 1.25-time oversampling rate 256QAM modulation mode according to the embodiment of the invention;
FIG. 3 is a loop filter structure disclosed in an embodiment of the present invention;
fig. 4 shows a constellation diagram before and after symbol synchronization when the sampling clock deviation is 1 x 10 -4 in the mode of 1.25 times oversampling rate 256QAM modulation, roll-off factor 0.125, signal-to-noise ratio E b/N0 of 31dB,
Wherein the diagram (a) is a constellation diagram before synchronization, and the diagram (b) is a constellation diagram after synchronization;
Fig. 5 illustrates an embodiment of the present invention, in which the roll-off factor is 0.125, the sampling clock deviation is 1×10 -4, and the error rates under different E b/N0 are compared with the theoretical values in a 256QAM modulation mode with 1.25 times of the oversampling rate.
Fig. 6 is a flow chart of an all-digital single carrier symbol timing synchronization method under any oversampling ratio.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples. The technical problems and the beneficial effects solved by the technical proposal of the invention are also described, and the described embodiment is only used for facilitating the understanding of the invention and does not have any limiting effect.
The structure of the all-digital single-carrier symbol timing synchronization method under any oversampling ratio disclosed by the embodiment is shown in fig. 1, and the structure block diagram of the all-digital single-carrier symbol timing synchronization method under any oversampling ratio disclosed by the embodiment comprises a RAM buffer module, an NL point DFT module, a matched filtering module, a symbol timing deviation compensation module, a symbol timing deviation estimation module, a loop filter, an NCO, a RAM deviation control module, a frequency domain aliasing module and an ML point IDFT module. After the ADC performs zero intermediate frequency sampling, an over-sampling signal is obtained, and the ADC sampling signal is sent into the RAM buffer module to buffer data; the RAM cache module checks the cached data inside, and when one DFT processing length is met, the data is output to the DFT module; the DFT module performs discrete Fourier transform on the received time domain signals to obtain the same number of frequency domain signals, the frequency domain signals are sent to the matched filtering module, the matched filtering module performs multiplication operation on the frequency domain signals according to the corresponding matched filtering coefficients to obtain filtered signals and sends the filtered signals to the symbol timing deviation compensation module, the symbol timing deviation compensation module receives timing deviation output by the NCO module and performs frequency domain compensation on the frequency domain signals and outputs the signals to the symbol timing deviation estimation module and the frequency domain aliasing module, the symbol timing deviation estimation module performs timing deviation estimation on the corrected frequency domain signals and sends the estimation results to the loop filter, the loop filter performs second-order Jaffe filtering on the estimation results and sends the filtering results to the NCO module, the NCO receives the filtering results of the loop filter, performs NCO accumulation, judges overflow conditions after accumulation, sends forward overflow/reverse overflow/no-overflow results to the RAM offset control module, simultaneously sends residual values after accumulation overflow as timing deviation correction input to the symbol timing deviation compensation module, the RAM offset control module receives the overflow results and performs offset control on the output address of the RAM module according to the result, the whole processing loop carries out offset control on the output address of the corrected frequency domain signals, the frequency domain signals are subjected to the frequency domain offset factor offset modulation and the frequency domain signals are subjected to the frequency domain offset and the frequency domain offset module is subjected to the frequency domain offset and the frequency domain offset modulation relation is subjected to the frequency domain offset and the frequency domain offset module, and the IDFT module performs IDFT conversion on the frequency domain signals from the frequency domain aliasing module to finally obtain recovered time domain symbols, and the whole processing process is completed.
In this embodiment, the oversampling rate is 1.25 (i.e., 5/4), the roll-off factor is 0.125, and the sampling clock deviation of the received signal is 1×10 -4 in 256QAM modulation, and the spectrum is shown in fig. 2. According to the oversampling multiple 1.2, the number of single-processing points of DFT is 160 points, the number of corresponding IDFT processing points is 128 points, and specific steps are as follows after the number of points is explicitly processed.
And S1, the buffer RAM module buffers the data, records an initial read address ADDR_rd, updates a write address ADDR_wr one by one when the data enters, and reads 160 sampling data when the buffer is enough for one DFT processing (160 sampling points corresponding to ADDR_wr=ADDR_rd+160+Offset_index) and the corresponding addresses are ADDR_rd+Offset_index+1 to ADDR_rd+Offset_index+160, wherein the Offset signal input by the RAM Offset control module is Offset_index (the value range is 0 and +/-1). The current read address is recorded and ADDR _ rd is updated for the next backward output of data.
S2, the DFT module receives 160 sampling points X 0～x159 from the cache RAM module, performs 160-point DFT operation on the 160 sampling points X 0～x159 to obtain 160 frequency domain sampling points X 0～X159, and sends the 160 frequency domain sampling points X 0～X159 to the matched filtering module.
And S3, the matched filtering module receives 160 frequency domain sampling points and performs equivalent 81-order matched filtering. Tail zero padding to 160 length for 81 filter time domain impulse responses
gextend＝{g0,g1,…,g80,0,0,…,0}1×160
Performing 160-point DFT operation on the zero-padded time domain impulse response G extend to obtain 160-point frequency domain response G 0～G159, storing the value into a local ROM, and performing point-by-point multiplication operation with the received frequency domain sampling point X 0～X159
Yn＝XnGn,n=0,1,...,159
Y 0～Y159 is obtained.
And S4, the symbol timing deviation compensation module performs timing deviation compensation processing on the received frequency domain filtering result Y 0～Y159.
S4.1, carrying out 128-point cyclic shift on Y 0～Y159 to obtain a shift sequence Y' 0～Y′159 meeting the requirement
{Y′0,Y′1,…,Y′159}＝{Y128,Y129,…,Y159,Y0,Y1,…,Y127}
S4.2 conjugate multiplication of Y 0～Y159 and Y' 0～Y′159, resulting in Z 0～Z159 satisfying
Zn＝Yn(Y′n)*,n=0,1,...,159
S4.3 summing Z 0～Z159 and taking the normalized phase to obtain the normalized timing deviation epsilon
And S5, sending the estimated timing deviation epsilon to a loop filter, wherein the loop filter adopts a Jaffe second-order loop, and the structure of the loop filter is shown in figure 3. Where ω n is the characteristic frequency and its value is 1.8868 ×b L,BL is the loop bandwidth, here set to 0.1, and k is the loop gain, here set to 0.3.
The output of the loop filter is sent to the NCO module where the overflow threshold of the NCO is 0.2 (1-1/1.25=0.2). For example, the original residual value of NCO is 0.15, the timing deviation value after the filtering is received is 0.08, the accumulated NCO is 0.23, forward overflow occurs, and a forward overflow identification signal is output to the RAM control offset module. The NCO also performs overflow modulo operation, and the final NCO value is 0.03 (0.23-0.2=0.03), which will be the offset τ for the next timing offset compensation. After receiving the forward overflow identification signal, the RAM control Offset module sets 1 to the offset_index signal in the RAM buffer module to indicate the output Offset of RAM data at the next iteration.
In the step S7, the compensated frequency domain data Y 0～Y159 in the step S3 is subjected to frequency domain aliasing extraction processing in a frequency domain aliasing module to obtain 128 (160/1.25=128) frequency domain symbols S 0～S127, and when the roll-off factor α is 0.125 and the number of valid signal frequency domain points is 128, the number of roll-off band frequency domain points is 16 (128×0.125=16), and the aliasing mode is as follows:
(1) S 0～S55 is free of aliasing and equal to Y 0～Y55;
(2) S 56～S63 there is an aliasing whose value is equal to the point-wise summation of Y 56～Y63 and Y 80～Y87;
(3) S 64～S71 there is an aliasing whose value is equal to the point-wise summation of Y 96～Y103 and Y 64～Y71;
(4) S 72～S127 is free of aliasing and is equal to Y 104～Y159.
And S8, carrying out 128-point IDFT operation on the frequency domain aliasing frequency domain symbol S 0～S127 to obtain a finally recovered time domain symbol S 0～s127.
And S9, repeating the step S1, and performing loop iteration until the loop gradually converges to complete the whole symbol synchronization process.
Simulation results of the above procedure are shown in fig. 4 and 5. Under the conditions of extremely low non-integer times of oversampling rate (1.25 times of oversampling) and large clock deviation (1×10 -4) during sampling, from the result of fig. 4, the timing synchronization can perfectly recover the signal, the 256QAM constellation point is clearly visible, in fig. 5, compared with the 256QAM theoretical error code curve, the timing synchronization result is close to the theoretical value under different E b/N0 conditions. The results of fig. 4 and 5 illustrate that the proposed method can adapt to conditions of non-integer low oversampling rate and different signal to noise ratios, ensure extremely low performance loss, and can expand the application range of a single carrier system.
While the foregoing detailed description has described the objects, aspects and advantages of the invention in further detail, it should be understood that the foregoing description is only illustrative of the invention, and is intended to cover various modifications, equivalents, alternatives, and improvements within the spirit and scope of the present invention.
Claims (2)
1. A full-digital single carrier symbol timing synchronization method under any oversampling ratio is characterized by comprising the following steps,
The method comprises the steps of 1, sampling a received signal through an analog-to-digital converter (ADC), and carrying out quadrature frequency conversion to zero frequency to obtain an orthogonal zero frequency signal, wherein the over-sampling rate of the ADC is N/M times of symbol rate, wherein N is more than M;
Step 2, DFT conversion is carried out on the received signal, the conversion length is integer multiple of N, namely N multiplied by L, L is a positive integer, and a corresponding frequency domain signal is obtained, and then the output data length of the memory in the step 1 is N multiplied by L, and matched filtering is carried out on the frequency domain;
Step 3, compensating the timing deviation of the frequency domain signal Y (k) subjected to the matched filtering in the step 2, wherein the timing deviation to be compensated is that
The method of multiplying the frequency domain point by point is adopted, and the corrected frequency domain signal is
Step 4, correcting the frequency domain signal after the timing deviation in the step 3Performing timing deviation estimation;
the implementation method of the step 4 is that,
Step 4.1 first forPerforming cyclic shift to obtain
Here, |·| NL represents the cyclic shift of the NL point;
Step 4.2 pair And (3) withIs multiplied point by the conjugate of (2) to obtain
Where all components of Z (k) contain timing synchronization bias values;
step 4.3 summing all components of Z (k) and taking the phase to obtain a symbol timing offset estimate for maximum signal-to-noise ratio
In the middle ofTo obtain complex phaseThe value range of (C) is [ -pi, pi);
step 4.4 for convenience of subsequent treatment Normalization processing is carried out to obtain
Here, theThe range of values of [ -0.5, 0.5) representing the relative value of the symbol timing offset estimate for one symbol duration;
step5, the normalized symbol timing deviation obtained in the step 4 Sending the first-order signal to a second-order loop filter;
Step 6, loop output results drive NCO, judge whether NCO has positive overflow, negative overflow or no overflow, and confirm the deviation of front end memory output data according to overflow or not and overflow direction;
The implementation method of the step 6 is that,
Step 6.1 Loop Filter result isThe cumulative value of NCO is
Step 6.2, after finishing one accumulation, judging the current NCO value, wherein the threshold is
Step 6.3, memory offset control index amount O (i) satisfying
The value of O (i) determines whether the corresponding data block is additionally advanced by 1 sampling point, i.e., O (i) = -1, or additionally lagged by 1 sampling point, i.e., O (i) =1, or is not subjected to additional offset processing, i.e., O (i) =0, when the data block is fetched from the memory next time;
and 6.4, after O (i) is calculated, overflow updating is carried out on NCO:
then the overflow updated NCO (i) is obtained and will be taken as Compensating in step 3;
Step 7, the signals in the step 3 are processed Carrying out frequency domain aliasing treatment; The length of the signal S (n) after aliasing is NL, the aliasing process satisfies
Alpha is a roll-off factor of the transmitting end shaping filter;
step 8, performing IDFT with length of ML on S (n):
s(n)=IDFT(S(n))ML
s (n) is the final recovered symbol;
and 9, returning to the step 1, controlling the output data position of the (i+1) th memory according to the O (i) obtained in the step 6, and performing loop iteration to continuously obtain a recovered symbol, wherein N, M in the process can be arbitrarily selected.
2. The method for synchronizing symbol timing of all-digital single carrier under any oversampling ratio as set forth in claim 1, wherein the implementation method of step 2 is,
The frequency domain signal obtained by performing n×l point DFT conversion is X (k), k=0, 1, & NL-1, and the effective signal is
Performing matched filtering processing on the effective signal in the frequency domain, wherein the matched filtering is in a convolution form in the time domain and in a point-by-point multiplication form in the frequency domain, wherein the frequency domain of the matched filtering is expressed as G (k), and the point-by-point multiplication of the G (k) and X s (k) is performed to obtain a filtered frequency domain signal
Y(k)=Xs(k)G(k)
Where k=0, 1, NL-1.
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