CN116565000A - Four-terminal tunneling field effect transistor and preparation method thereof - Google Patents

Abstract

The invention provides a four-terminal tunneling field effect transistor and a preparation method thereof, belonging to the technical field of micro-nano electronics. According to the four-terminal tunneling field effect transistor structure provided by the invention, the substrate regions of the four-terminal TFET devices are provided with the PN junctions with zero offset or reverse offset, so that electric leakage between TFET devices and between TFET and CMOS can be inhibited. Under all circuit application scenes, the low-power consumption advantage and normal operation of the TFET circuit and the TFET-CMOS hybrid circuit are ensured, and the circuit reliability is improved. The source end of the four-end TFET device can be designed by adopting a tunneling junction with a single doping type or a mixed mechanism junction with two doping types. The invention adopts the existing mature process steps in the bulk silicon CMOS, has simple process, and truly has the potential of large-scale application and mass production of the tunneling field effect transistor.

Description

A four-terminal tunneling field effect transistor and its manufacturing method

technical field

The invention belongs to the technical field of micro-nano electronics, and in particular relates to a tunneling field-effect transistor device and a preparation method that can face full-circuit application scenarios.

Background technique

With the continuous advancement of semiconductor technology, the size of devices has been continuously reduced, circuit performance has been continuously improved, and chip power consumption density has also increased sharply. Low power consumption has become an important design direction. From the device level, reducing the power supply voltage can effectively reduce the power consumption of the circuit. However, in order to maintain sufficient driving capability, the threshold voltage of the MOSFET device must also be reduced, resulting in an increase in off-state current and static power consumption. Tunneling Field Effect Transistor (TFET) adopts the current mechanism of band-band tunneling, and the carriers at the high-energy band tail are effectively cut off, which can obtain an ultra-steep sub-threshold slope lower than 60mV/dec, providing a higher current On-off ratio, which enables low-voltage operation, is considered a promising ultra-steep alternative to MOSFETs.

Based on Sentaurus TCAD and HSPICE simulations, tunneling field effect transistors have been proven to have significantly better power delay product (PDP) than MOSFETs under certain low-voltage and low-frequency operating conditions, and have certain application fields and prospects. However, in large-scale integrated circuit applications, due to the characteristics of lightly doped substrate and asymmetric source-drain doping of tunneling field effect transistors, the leakage current between each tunneling field effect transistor and the tunneling field effect transistor The leakage current between the substrate and the CMOS device is higher than the off-state current of the tunneling field effect transistor itself, which increases the static power consumption of the circuit and even makes the circuit function invalid.

Further, the existing TFET devices are all three-terminal devices, and the substrate has no electrodes drawn out and is in a floating state. In large-scale integrated circuits, if a forward-biased PN junction is formed between the floating substrate and the source-drain of a zero-biased TFET device, additional leakage current will be introduced, which may increase the static power consumption of the circuit, and may also cause The circuit function fails.

Therefore, how to design TFET devices so that they can still maintain the advantage of low power consumption and work normally in the application of large-scale hybrid integrated circuits with CMOS has become an urgent problem to be solved.

Contents of the invention

The purpose of the present invention is to provide a four-terminal tunneling field effect transistor and its preparation method, so that it can still maintain the advantage of low power consumption and work normally in the application of large-scale hybrid integrated circuits with CMOS.

The technical scheme provided by the invention is as follows:

A four-terminal tunneling field-effect transistor device includes an active area (AA) and a body-extraction area (BC) defined by shallow trench isolation (STI). The inside of the active region is composed of three parts, which are the TFET source and drain region (SD), the TFET channel region (Channel) and the TFET substrate region (SUB) along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate. The doping type is determined by the doping type of the first type doping region in the substrate region. The channel region is located in the middle and bottom of the source and drain regions. The source and drain regions can be wrapped to separate the substrate region from the source and drain regions. The TFET substrate region (SUB) consists of two parts, along the direction perpendicular to the channel are the first type doped region (SUB-I) and the second type doped region (SUB-II), the first The doped region of the first type can be N-type doped or P-type doped, and the doping type of the doped region of the second type is opposite to that of the doped region of the first type. The peak of the second type doped region (SUB-I) is located below the bottom of the shallow trench isolation (STI). The body lead-out region (BC) consists of two parts, which are the TFET substrate electrode region (BE) and the substrate doped region (BWELL) along the direction perpendicular to the channel. The doping type of the substrate doped region is related to the substrate The doping type of the second type doped region in the bottom region is the same, and the two realize the spatial connection at the bottom of the shallow trench isolation, so as to ensure that the TFET substrate region (SUB) can be covered by the TFET substrate of the body extraction region (BC). The bottom electrode area (BE) leads out.

The technical effect of the proposed device structure is that if the first type doped region (SUB-I) is P-type doped, then the first type doped region is drawn out by the P-type heavily doped source and drain regions of the TFET, The second type doped region (SUB-II) is extracted to the power supply voltage VDD by the body extraction region (BC). If the first type doped region (SUB-I) is N-type doped, then the first type doped region is drawn out by the N-type heavily doped source and drain regions of the TFET, and the second type doped region (SUB-I) II) will be led out to the power supply voltage GND by the body lead-out area (BC). Therefore, no matter whether the TFET device is designed in the forward-biased PIN region or the reverse-biased PIN region in the circuit application, between the first type doped region (SUB-I) and the second type doped region (SUB-II) A zero-bias or reverse-bias PN junction will be formed, which can suppress the leakage between TFET devices and between TFET and CMOS. Further, since the bottom layer of the substrate of the four-terminal TFET device is always connected to a constant voltage, compared with the traditional three-terminal TFET device, in large-scale integrated circuits, the contact between the substrate and the source-drain region of the zero-bias TFET device is avoided. Leakage improves the reliability of the circuit and reduces the power consumption of the circuit. In addition, the top of the TFET substrate region is a lightly doped channel region, which ensures the advantage of low off-state current of the TFET device.

The above-mentioned four-terminal tunneling field effect transistor device can be prepared by the following process. This process method can realize the mixed integration of four-terminal tunneling field effect transistor and CMOS device, and its characteristics are:

Step 1: Select a wafer corresponding to high-resistance silicon for device and circuit preparation;

Step 2: Do shallow trench isolation (STI), the specific method is to etch silicon anisotropically outside the active area; then deposit an oxide layer anisotropically outside the active area;

Step 3: Depositing an oxide layer on the substrate in an anisotropic manner;

Step 4: Define the CMOS P-well implantation region and the body-extraction implantation region requiring P-type doping in the TFET device through the photolithography process, and the boundaries of the implantation regions are all located in the center of the STI;

Step 5: Form the P-well of CMOS and the body lead-out region that requires P-type doping in TFET devices by ion implantation, and remove the glue after ion implantation;

Step 6: respectively define the N-well implantation region of CMOS and the body-extraction implantation region requiring N-type doping in TFET devices through photolithography, and the boundaries of the implantation regions are all located in the center of the STI;

Step 7: Form the N well of CMOS and the body lead-out region that needs N-type doping in the TFET device by ion implantation, and remove the glue after ion implantation;

Step 8: After removing the oxide layer formed in step 3, repeat step 3;

Step 9: Define the N-type TFET substrate injection region by photolithography process, the width of the N-type TFET substrate injection region is larger than the width of the active region, and the boundary of the injection region is located in the center of the STI;

Step 10: implanting P-type impurities and N-type impurities by ion implantation to form the first type doped region (SUB-I) and the second type doped region (SUB-II) of the N-type TFET substrate region, The ion implantation energy corresponding to the first type doped region (SUB-I) is low, and the ion implantation energy corresponding to the second type doped region (SUB-II) is relatively high, and the glue is removed after ion implantation;

Step 11: Define the P-type TFET substrate injection region by photolithography process, the width of the P-type TFET substrate injection region is larger than the width of the active region, and the boundary of the injection region is located in the center of the STI;

Step 12: implanting P-type impurities and N-type impurities by ion implantation to form the first type doped region (SUB-I) and the second type doped region (SUB-II) of the P-type TFET substrate region, The ion implantation energy corresponding to the first type doped region (SUB-I) is low, and the ion implantation energy corresponding to the second type doped region (SUB-II) is relatively high, and the glue is removed after ion implantation;

Step 13: Etch the oxide layer anisotropically on the whole chip, do gate stacking and heavily doped region implantation and other subsequent steps to complete the device preparation.

Wherein, the doping type of the wafer in step 1 can be boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm;

The thickness of STI in step 2 should be between 200nm-1000nm;

The thickness of the oxide layer deposited in step 3 and the thickness of the oxide layer etched in step 8 are between 1nm and 2nm;

Step 5 and step 7 are the well implantation conditions in the mature CMOS process. These two steps form the substrate doped region ( BWELL);

In step 10 and step 12, the ion implantation energy corresponding to the first type doped region (SUB-I) of the TFET substrate region is relatively low, and the peak position of the impurity distribution is inside the STI, so doping is only formed between the STIs. district. For the second type doped region (SUB-II) of the TFET substrate region, the corresponding ion implantation energy is relatively high, and the peak position of the impurity distribution is below the bottom of the STI. Since STI has the effect of suppressing the channel effect of ion implantation, it can increase the peak concentration, reduce the tail concentration, and reduce the depth of the peak position, so that there is a higher doping concentration below the bottom of the STI. At the depth and in the region away from the STI, the doping concentration decreases, and the boundary line between the upper and lower doped regions of the TFET substrate region shifts toward the depth of the substrate;

In step 10 and step 12, the N-type impurity may be phosphorus (P) or arsenic (As), and the P-type impurity may be boron (B) or boron fluoride (BF2). It is necessary to adjust the ion implantation conditions so that there is only the second type doped region (SUB-II) of the TFET substrate region (SUB) at the bottom of the STI, and at the same time, at the STI boundary, the first type doped region of the TFET substrate region The boundary between (SUB-I) and the second type doped region (SUB-II) is located at and above the bottom of the STI. The peak position of the impurity distribution corresponding to the first type doped region (SUB-I) of the TFET substrate region is located at a distance of more than 200nm from the channel surface and between the bottom of the STI, thereby ensuring that the first type doped region A lightly doped TFET channel region (Channel) is simultaneously formed above (SUB-I). The ion implantation conditions also need to ensure that the peak concentrations corresponding to the first type doped region (SUB-I) and the second type doped region (SUB-II) of the TFET substrate region (SUB) are both greater than 5E16cm ^-2 , The channel surface concentration is less than 1E16cm ^-2 . In addition, STI is used to define the active area (AA) and body extraction area (BC), and also acts as a hard mask for ion implantation. Since STI has the effect of suppressing the channel effect of ion implantation, it can increase the peak concentration, reduce the concentration of the band tail, and reduce the depth of the peak position, so that the second type of doped region (SUB-II) in the STI A region with a higher doping concentration is formed below the bottom. At the same depth and far away from the STI, the doping concentration of the second type doping region (SUB-II) is reduced, and the doping concentration of the first type doping region (SUB-II) is reduced. -I) The boundary line with the second type doped region (SUB-II) is shifted toward the depth of the substrate.

Step 13 is the process preparation method of TFET devices and CMOS devices, including the annealing step of source-drain activation, and can utilize the heavily doped region implantation in the device preparation process to simultaneously form the substrate electrode of the body lead-out region (BC) of the four-terminal TFET device region (BE), the impurity activation of the first type doped region (SUB-I) and the second type doped region (SUB-II) is realized by annealing in the device preparation process; The heavily doped region is implanted to synchronously form the substrate electrode region of the body lead-out region of the four-terminal TFET device.

The invention is oriented to large-scale integrated circuits, and TFET devices with the same substrate area can share the lead-out area (BC), saving layout area.

The four-terminal tunneling field effect transistor structure proposed by the present invention can ensure the low power consumption advantage and normal operation of TFET circuits and TFET-CMOS hybrid circuits in all circuit application scenarios, and improve circuit reliability. Moreover, the source terminal of the four-terminal TFET device can adopt either a tunnel junction design of a single doping type, or a mixed mechanism junction design of two doping types.

The process method of the four-terminal tunneling field effect transistor proposed by the present invention adopts the existing mature process steps in the bulk silicon CMOS, and does not lead out new materials, and the realization process is simple, so that the tunneling field effect transistor really has large-scale application and mass production potential.

Description of drawings

Fig. 1 is a schematic cross-sectional view of a four-terminal TFET device of the present invention, wherein: (a) the first type doped region (SUB-I) of the substrate region (SUB) of the four-terminal TFET device is an N-type doped region, and the second The type doping region (SUB-II) is a P-type doping region; (b) the first type doping region (SUB-I) of the substrate region (SUB) of the four-terminal TFET device is a P-type doping region , the second type doping region (SUB-II) is an N-type doping region;

Figure 2 is a four-terminal TFET device that can apply a mixed source junction. The upper layer of the N-type device substrate region is a P-type doped region, the lower layer is an N-type doped region, and the upper layer of the P-type device substrate region is N-type doped region, the lower layer is a P-type doped region;

Figure 3 is a schematic diagram of the process steps of the mixed integration of four-terminal TFET devices and CMOS, in which: (a) is the diagram after the shallow trench isolation process; (b) is the diagram after the oxide layer deposition process; (c) photolithographically defines the P well of the nMOSFET Figure after implantation region; (d) Figure after implantation of P well of nMOSFET; (e) Figure after lithography definition of N well implantation area of pMOSFET; (f) Figure after injection of N well of pMOSFET; (g) Photolithography definition of N type (h) After implantation of N-type TFET substrate; (i) After photolithographic definition of P-type TFET substrate implantation region; (j) After implantation of P-type TFET substrate;

In the picture:

1——gate conductive layer 2——gate dielectric layer

3——P-type heavily doped region 4——N-type heavily doped region

5—shallow trench isolation 6—lightly doped substrate

7——P-type doped region 8——N-type doped region

9——N well of pMOSFET 10——Deposition of oxide layer

11 - photoresist 12 - P well of nMOSFET

Detailed ways

The present invention will be further described below by example. It should be noted that the purpose of the disclosed embodiments is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present invention and the appended claims of. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

The first type doped region (SUB-I) of the substrate region (SUB) of the proposed four-terminal tunneling field effect transistor can be N-type doped or P-type doped, depending on the actual circuit application scenario It is determined by the design of the doping type of the source and drain of the TFET.

If you want to avoid the leakage current between the substrate and the source-drain region of the zero-bias TFET device, you can design the first type doped region (SUB-I) of the substrate region (SUB) as N-type doping, and The second type doping region (SUB-II) of the substrate region (SUB) is designed as P-type doping, referring to Figure 1(a), a four-terminal tunneling field-effect transistor device, including a shallow trench isolation (STI) defined active area (AA) and body-extraction area (BC). The inside of the active region is composed of three parts, which are the TFET source and drain region (SD), the TFET channel region (Channel) and the TFET substrate region (SUB) along the direction perpendicular to the channel. Between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2 is the active region (AA), and the P-type heavily doped region 3 and the N-type heavily doped region 4 inside the AA region form the source of the TFET. Drain area (SD). The TFET substrate region (SUB) consists of two parts, which are N-type doped region (NSUB) 8 and P-type doped region (PSUB) 7 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate, located in the middle and bottom of the source and drain regions, which can wrap the source and drain regions, thereby separating the substrate region from the source and drain regions. The body lead-out region (BC) consists of two parts, which are the TFET substrate electrode region (BE) 3 and the P-type doped region (PWELL) 12 along the direction perpendicular to the channel, and the PWELL12 and PSUB7 are connected to each other to ensure that the TFET The substrate area (SUB) can be extracted to GND by the TFET substrate electrode area (BE) of the body extraction area (BC).

If you want to apply a four-terminal TFET device in an application scenario that requires a forward-biased PIN current such as a multi-state gate logic circuit, you can design the first type doped region (SUB-I) of the substrate region (SUB) as a P-type Doping, the second type doping region (SUB-II) of the substrate region (SUB) is designed as N-type doping,

Referring to FIG. 1(b), a four-terminal TFET device includes an active region (AA) and a body-lead region (BC) defined by shallow trench isolation (STI). The inside of the active region is composed of three parts, which are the TFET source and drain region (SD), the TFET channel region (Channel) and the TFET substrate region (SUB) along the direction perpendicular to the channel. Between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2 is the active region (AA), and the P-type heavily doped region 3 and the N-type heavily doped region 4 inside the AA region form the source of the TFET. Drain area (SD). The TFET substrate region (SUB) consists of two parts, which are respectively a P-type doped region (PSUB) 7 and an N-type doped region (NSUB) 8 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate, located in the middle and bottom of the source and drain regions, which can wrap the source and drain regions, thereby separating the substrate region from the source and drain regions. The body lead-out region (BC) consists of two parts, which are the TFET substrate electrode region (BE) 4 and the N-type doped region (NWELL) 9 along the direction perpendicular to the channel, and NWELL9 and NSUB8 are connected to each other to ensure that the TFET The substrate area (SUB) can be extracted to VDD by the TFET substrate electrode area (BE) of the body extraction area (BC).

For some TFET devices with a new hybrid mechanism, the source end has two doping types, one is the same as the drain end doping type, and the other is the opposite of the drain end doping type. Therefore, this type of device requires a channel region with an opposite doping type to that of the drain, thereby suppressing the leakage current of the device itself from source to drain. For this reason, the device structure of the four-terminal tunneling field effect transistor designed for the new hybrid mechanism is as follows, referring to Figure 2, the left side is an N-type device, and the right side is a P-type device:

For N-type TFET devices, it includes the active area (AA) and body-extraction area (BC) defined by shallow trench isolation (STI). The inside of the active region is composed of three parts, which are the TFET source and drain region (SD), the TFET channel region (Channel) and the TFET substrate region (SUB) along the direction perpendicular to the channel. Between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2 is the active region (AA), and the P-type heavily doped region 3 and the N-type heavily doped region 4 inside the AA region form a mixed source junction. . The TFET substrate region (SUB) consists of two parts, which are respectively a P-type doped region (PSUB) 7 and an N-type doped region (NSUB) 8 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate, located in the middle and bottom of the source and drain regions, which can wrap the source and drain regions, thereby separating the substrate region from the source and drain regions. The body lead-out region (BC) consists of two parts, which are the TFET substrate electrode region (BE) 4 and the N-type doped region (NWELL) 9 along the direction perpendicular to the channel, and NWELL9 and NSUB8 are connected to each other to ensure that the TFET The substrate area (SUB) can be extracted to VDD by the TFET substrate electrode area (BE) of the body extraction area (BC).

For a P-type TFET device, it includes an active area (AA) and a body-extraction area (BC) defined by shallow trench isolation (STI). The inside of the active region is composed of three parts, which are the TFET source and drain region (SD), the TFET channel region (Channel) and the TFET substrate region (SUB) along the direction perpendicular to the channel. Between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2 is the active region (AA), and the N-type heavily doped region 4 and the P-type heavily doped region 3 inside the AA region form a mixed source junction. . The TFET substrate region (SUB) consists of two parts, which are N-type doped region (NSUB) 8 and P-type doped region (PSUB) 7 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate, located in the middle and bottom of the source and drain regions, which can wrap the source and drain regions, thereby separating the substrate region from the source and drain regions. The body lead-out region (BC) consists of two parts, which are the TFET substrate electrode region (BE) 3 and the P-type doped region (PWELL) 12 along the direction perpendicular to the channel, and the PWELL12 and PSUB7 are connected to each other to ensure that the TFET The substrate area (SUB) can be extracted to GND by the TFET substrate electrode area (BE) of the body extraction area (BC).

The device structure shown in FIG. 2 can be prepared through the steps shown in FIG. 3 . Proceed as follows:

First, select a wafer corresponding to boron-doped P-type high-resistance silicon for device and circuit preparation, with a resistivity of 9 Ohm-cm;

Secondly, to do shallow trench isolation (STI), the specific method is to etch silicon anisotropically outside the active area; then deposit an oxide layer anisotropically outside the active area; as As shown in Figure 3(a), 5 is a 300nm STI, and 6 is a P-type lightly doped substrate;

Next, as shown in FIG. 3(b), an oxide layer 10 of 2 nm is deposited on the substrate in an anisotropic manner;

Next, as shown in Figure 3(c), the P-type doped body-extraction implantation regions of the P-type TFET devices are respectively defined by a photolithography process, and the boundaries of the implantation regions are all located in the center of the STI;

Next, as shown in Figure 3(d), the P-type doped body extraction region of the P-type TFET device is formed by ion implantation. A total of three ion implantations are performed under the conditions of 90keV1E13cm ^-3 , 200keV5E13cm ^-3 , and 10keV1E13cm ^-3 , to remove glue after ion implantation;

Next, as shown in Figure 3(e), the N-type doped body-extraction injection regions of the N-type TFET device are respectively defined by a photolithography process, and the boundaries of the injection regions are all located in the center of the STI;

Next, as shown in Figure 3(f), the N-type doped body extraction region of the N-type TFET device is formed by ion implantation. A total of three ion implantations are performed under the conditions of 30keV5E12cm ^-3 , 220keV5E12cm ^-3 , and 380keV5E13cm ^-3 , to remove glue after ion implantation;

Next, etch the oxide layer 10, and deposit a 2nm oxide layer 10 on the substrate in an anisotropic manner; next, as shown in FIG. Substrate implant area;

Next, as shown in Figure 3(h), boron is implanted by ion implantation to form P-type doped region 7, the implantation energy is 60keV, and the implantation dose is 1e13cm ^-3 , and phosphorus is implanted by ion implantation to form N-type doped region 7. In impurity region 8, the implantation energy is 340keV, the implantation dose is 1e13cm ^-3 , and the glue is removed after ion implantation;

Next, as shown in FIG. 3(i), the substrate implantation region of the P-type TFET is defined by photolithography;

Next, as shown in Fig. 3(j), phosphorous is implanted by ion implantation to form N-type doped region 8, the implantation energy is 180keV, and the implantation dose is 1e13cm ^-3 , and boron is implanted by ion implantation to form P-type doped region 8. In impurity region 7, the implantation energy is 140keV, the implantation dose is 1e13cm ^-3 , and the glue is removed after ion implantation;

Next, the oxide layer 10 is anisotropically etched across the entire chip, followed by subsequent steps such as gate stacking and heavily doped region implantation, to complete the device preparation, and activate the impurities in the isolation well through the thermal budget of the subsequent source-drain activation. Form the final device structure as shown in Figure 2.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A four-terminal tunneling field effect transistor device comprises an active region and a body leading-out region, wherein the active region and the body leading-out region are defined by shallow trench isolation, the inside of the active region is composed of three parts, a TFET source drain region, a TFET channel region and a TFET substrate region are respectively arranged along the direction vertical to a channel, the TFET channel region is a lightly doped silicon substrate, the doping type is determined by the doping type of a first type doping region of the substrate region, the channel region is positioned in the middle and at the bottom of the source drain region, the source drain region is wrapped by the substrate region, the substrate region is further separated from the source drain region, the TFET substrate region is composed of two parts, the first type doping region and the second type doping region are respectively arranged along the direction vertical to the channel, the first type doping region is N-type doping or P-type doping, the doping type of the second type doping region is opposite to the first type doping region, the peak value of the second type doping region is positioned below the shallow trench isolation bottom, the body leading-out region is composed of the substrate region and the substrate region, the TFET substrate region and the TFET substrate region are respectively arranged along the direction vertical to the channel, the direction vertical to the channel is consistent with the position of the substrate region, and the body leading-out region is realized.

2. The four-terminal tunneling field effect transistor device of claim 1, wherein the shallow trench isolation bottom has only the second type doped region of the TFET substrate region, such that at the shallow trench isolation boundary, the boundary of the first type doped region and the second type doped region of the TFET substrate region is located at and above the shallow trench isolation bottom, and at the region between the shallow trench isolations, the boundary of the first type doped region and the second type doped region of the TFET substrate region is located at or above and below the shallow trench isolation bottom.

3. The four-terminal tunneling field effect transistor device of claim 1, wherein a peak impurity profile location corresponding to the first type doped region of the TFET substrate region is located above 200nm from a channel surface to a location between shallow trench isolation bottoms.

4. A preparation method of a four-terminal tunneling field effect transistor device comprises the following steps:

1) Selecting a wafer corresponding to high-resistance silicon to prepare devices and circuits;

2) Shallow trench isolation is carried out by etching silicon in an anisotropic manner at a place outside the active region; depositing an oxide layer outside the active region in an anisotropic manner;

3) Depositing an oxide layer on the substrate in an anisotropic manner;

4) Defining a P-well injection region of the CMOS and a body extraction injection region needing P-type doping in a TFET device respectively through a photoetching process, wherein the boundary of the injection region is positioned at the center of shallow slot isolation;

5) Forming a P well of the CMOS and a body leading-out region needing P type doping in a TFET device in an ion implantation mode, and removing photoresist after the ion implantation;

6) Defining an N-well injection region of the CMOS and a body extraction injection region needing N-type doping in a TFET device respectively through a photoetching process, wherein the boundary of the injection region is positioned at the center of shallow slot isolation;

7) Forming an N-type doped body leading-out region in the CMOS N-well and TFET device by means of ion implantation, and removing photoresist after the ion implantation;

8) Removing the oxide layer formed in the step 3), and repeating the step 3);

9) Defining an N-type TFET substrate injection region through a photoetching process, wherein the width of the N-type TFET substrate injection region is larger than that of the active region, and the boundary of the injection region is positioned at the center of shallow slot isolation;

10 The first type doped region and the second type doped region of the N-type TFET substrate region are formed by implanting P-type impurities and N-type impurities in an ion implantation mode, the ion implantation energy corresponding to the first type doped region is low, the ion implantation energy corresponding to the second type doped region is high, and photoresist is removed after ion implantation;

11 Defining a P-type TFET substrate injection region through a photoetching process, wherein the width of the P-type TFET substrate injection region is larger than that of the active region, and the boundary of the injection region is positioned at the center of shallow slot isolation;

12 The first type doped region and the second type doped region of the P type TFET substrate region are formed by implanting P type impurities and N type impurities in an ion implantation mode, the ion implantation energy corresponding to the first type doped region is low, the ion implantation energy corresponding to the second type doped region is high, and photoresist is removed after ion implantation;

13 Etching the oxide layer on the whole wafer by an anisotropic method, and performing subsequent steps such as gate stack and heavy doping region injection to complete device preparation.

5. The method of claim 4, wherein the doping type of the wafer in step 1) is boron or phosphorus, and the resistivity of the wafer is greater than 8Ohm-cm.

6. The method of claim 4, wherein the shallow trench isolation in step 2) has a thickness in the range of 200nm to 1000 nm.

7. The method of claim 4, wherein the thickness of the oxide layer deposited in step 3) is in the range of 1nm to 2 nm.

8. The method of claim 4, wherein the N-type doped impurity is phosphorus or arsenic and the P-type doped impurity is boron or boron fluoride.

9. The method of claim 4, wherein peak concentrations of the first type doped region and the second type doped region of the TFET substrate region are each greater than 5E16cm ^-2 The surface concentration of the channel is less than 1E16cm ^-2 。

10. The method of claim 4, wherein step 13) comprises a source drain activation annealing step, and wherein the annealing achieves impurity activation of the first type doped region and the second type doped region, and wherein the heavily doped regions in the device fabrication process are used to implant the substrate electrode regions that simultaneously form the body-out regions of the four-terminal TFET device.