CN116564380B - Correction method and device for gate pulse signals in DRAM (dynamic random Access memory) - Google Patents

Abstract

The application provides a correction method and a correction device for a gate pulse signal in a DRAM (dynamic random access memory), belonging to the technical field of memories, wherein the method comprises the following steps: determining a maximum phase offset based on the clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal to obtain a target gating pulse signal, and taking the target gating pulse signal as the gating pulse signal corresponding to the current correction node, so that the correction can be performed under the condition of not influencing the working of the DRAM, and the working efficiency of the DRAM is improved.

Description

Method and device for correcting gate pulse signals in DRAM

Technical field

The present application relates to the field of memory technology, and in particular to a method and device for correcting gate pulse signals in DRAM.

Background technique

When performing a read operation on the memory of a dynamic random access memory (Dynamic Random Access Memory, DRAM) particle, the storage controller needs to read the data in the memory based on the data strobe signal (Bidirectional datastrobe, DQS) generated by the storage unit. . In order to ensure the accuracy of reading data, it is necessary to obtain accurate DQS valid signals.

To address this problem, the existing technology outputs a gating pulse signal (i.e., DQS gating signal) with the same length as the effective DQS signal through the memory controller to perform a gating operation on the DQS signal output by the memory unit to obtain a gating DQS signal (i.e., DQS gating signal). gated DQS signal), and read data based on the gatedDQS signal. In order to ensure that the gatedDQS signal is an accurate and valid DQS signal, the DQSgating signal needs to be trained in advance. The training process of the DQSgating signal is: perform multiple read operations on the memory of the DRAM particle. The phase of the DQS gating signal corresponding to each read operation is different. The final read data is compared with the expected data to determine whether the read operation is correct. And the phase of the corresponding DQSgating signal when the read operation is correct is used as the gating pulse signal phase of the subsequent read operation.

Using the above method can ensure the accurate reading of data in DRAM particles to the greatest extent. However, during the actual operation of DRAM, the tdqsck parameters will dynamically change with changes in temperature and voltage within the range specified by the design specifications, that is, the phase of the DQS signal will dynamically change, so the phase of the DQS gating signal needs to be retrained to ensure accurate acquisition. DQS valid signal. However, because the training process of the DQS gating signal takes a long time and requires the suspension of normal access to the DRAM, frequent DQS gating signal training will cause a serious reduction in the working efficiency of the DRAM.

Contents of the invention

The present application provides a method and device for correcting a gate pulse signal in a DRAM to solve the problem that the existing correction method of the gate pulse signal reduces the working efficiency of the DRAM.

This application provides a method for correcting gate pulse signals in DRAM. The method includes:

Determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset;

The initial gating pulse signal is phase adjusted based on the phase adjustment step to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating corresponding to the previous correction node. Pulse signal;

Sampling the data strobe signal corresponding to the current correction node based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set respectively to obtain the first sampling value sequence and the second sampling value sequence;

Determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, correct the initial gate pulse signal based on the phase correction value to obtain the target gate pulse signal, and The target gating pulse signal is used as the gating pulse signal corresponding to the current correction node.

According to a method for correcting gate pulse signals in DRAM provided by this application, the maximum phase offset is the phase offset corresponding to half of the clock cycle of the DRAM. Correspondingly, the phase adjustment step is the The quotient of the maximum phase offset and the preset number of phase adjustment gears.

According to a method for correcting gating pulse signals in DRAM provided by this application, the phase of the initial gating pulse signal is adjusted based on the phase adjustment step to obtain a first gating pulse signal set and a second gating pulse. Signal collection, specifically including:

The initial gate pulse signal is shifted to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and the initial gate pulse signal is shifted to the right N times based on the phase adjustment step to obtain the first gate pulse signal set. A second set of gated pulse signals is obtained; where N is the preset number of phase adjustment gears.

According to a method for correcting gate pulse signals in DRAM provided by this application, the first gate pulse signal set includes N gate pulse signals corresponding to N shifts to the left, and the second gate pulse signal The signal set includes N gate pulse signals corresponding to N shifts to the right.

According to a method for correcting gate pulse signals in DRAM provided by this application, the current correction node is corrected based on the gate pulse signals in the first gate pulse signal set and the second gate pulse signal set respectively. The corresponding data strobe signal is sampled to obtain the first sample value sequence and the second sample value sequence, specifically including:

Based on the rising edges of N gate pulse signals in the first gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding first sample value set, and based on the first The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting the sample values in the first sample value set to obtain the first sample value sequence;

Based on the rising edges of N gate pulse signals in the second gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding second sample value set, and based on the second The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal is used to sort the sample values in the second sample value set to obtain a second sample value sequence.

According to a method for correcting a gate pulse signal in a DRAM provided by this application, the step of determining the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:

Determine the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence;

The phase correction value of the gate pulse signal is determined based on the current phase offset direction and phase offset amount of the initial gate pulse signal.

According to a method for correcting a gate pulse signal in a DRAM provided by this application, the current phase offset direction and phase offset of the initial gate pulse signal are determined based on the first sample value sequence and the second sample value sequence. Movement amount, specifically including:

When the sampled values in the first sampled value sequence are all 0 and the sampled values in the second sampled value sequence are all 1, it is determined that the initial gating pulse signal has no offset;

In the case where the sample values in the first sample value sequence and the second sample value sequence both include 0 and 1, the determination is based on the positions and numbers of 0 and 1 in the first sample value sequence and the second sample value sequence. The current phase offset direction and phase offset amount of the initial gating pulse signal.

This application also provides a device for correcting gate pulse signals in DRAM. The device includes:

A first determination module, configured to determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset;

A gated pulse signal set generation module, configured to perform phase adjustment on the initial gated pulse signal based on the phase adjustment step to obtain a first gated pulse signal set and a second gated pulse signal set; the initial gated pulse The signal is the gate pulse signal corresponding to the previous correction node;

A sampling value sequence generating module, configured to sample the data strobe signal corresponding to the current correction node based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set respectively to obtain the first a sequence of sampled values and a second sequence of sampled values;

A signal correction module, configured to determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, and correct the initial gate pulse signal based on the phase correction value to obtain the target gate control pulse signal, and use the target gate control pulse signal as the gate control pulse signal corresponding to the current correction node.

The present application also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for correcting a gate pulse signal in a DRAM as described above are implemented.

The present application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method for correcting a gate pulse signal in a DRAM as described above.

The method and device for correcting gate pulse signals in DRAM provided by this application determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset; based on the phase adjustment step Phase adjustment is performed on the initial gating pulse signal to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating pulse signal corresponding to the previous correction node; respectively based on the The gated pulse signals in the first gated pulse signal set and the second gated pulse signal set sample the data strobe signal corresponding to the current correction node to obtain a first sampled value sequence and a second sampled value sequence; Determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, correct the initial gate pulse signal based on the phase correction value to obtain the target gate pulse signal, and The target gate pulse signal is used as the gate pulse signal corresponding to the current correction node. Compared with the existing method of correcting the gate pulse signal through training, the gate pulse signal can be corrected without affecting the normal access of the DRAM. Fast and accurate correction greatly improves the working efficiency of DRAM.

Description of drawings

In order to explain the technical solutions in this application or the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are of the present invention. For some embodiments of the application, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a schematic flow chart of the method for correcting gate pulse signals in DRAM provided by this application;

Figure 2 is a schematic waveform diagram corresponding to the correction method of the gate pulse signal in DRAM provided by this application;

Figure 3 is a schematic flow chart for determining the phase correction value provided by this application;

Figure 4 is a schematic structural diagram of a correction device for gate pulse signals in DRAM provided by this application;

Figure 5 is a schematic structural diagram of an electronic device provided by this application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Figure 1 is a schematic flow chart of the method for correcting gate pulse signals in DRAM provided by this application. As shown in Figure 1, the method includes:

Step 101: Determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset.

Specifically, the maximum phase offset is the phase offset corresponding to half of the clock cycle of the DRAM. Correspondingly, the phase adjustment step is the maximum phase offset and the preset number of phase adjustment gears. quotient. Based on the foregoing, it can be seen that during the actual operation of DRAM, the tdqsck parameter will dynamically change with changes in temperature and voltage within the range specified by the design specification, that is, the phase of the DQS signal will dynamically change. Figure 2 is a diagram of the DRAM provided by this application. The waveform diagram corresponding to the correction method of the gate pulse signal is shown in Figure 2. In order to ensure the accuracy of the read operation, it is necessary to ensure that the gate pulse signal (i.e., DQS gating signal) is aligned with the rising edge of the DQS valid signal. Therefore, when When the phase of the DQS signal changes dynamically, the phase of the DQS gating signal must also change accordingly. Based on this, the embodiment of the present application first determines the phase fluctuation range of the DQS signal based on the fluctuation range of the tdqsck parameter. Preferably, the embodiment of the present application sets the phase fluctuation range of the DQS signal to half of the clock cycle of the DRAM. Based on this, it is necessary to ensure The accuracy of the read operation needs to ensure that the phase adjustment range of the DQS gating signal matches the phase fluctuation range of the DQS signal. Therefore, in the embodiment of this application, the phase offset corresponding to half of the clock cycle of the DRAM is used as the maximum value of the gating pulse signal. Phase offset (corresponding to the maximum phase adjustment range). On this basis, in order to ensure the adjustment accuracy of the gate pulse signal during actual application, the embodiment of the present application can pre-set the number of phase adjustment gears (that is, the phase offset of the gate pulse signal from 0 to the maximum phase offset The number of adjustments corresponding to the amount), the phase adjustment step can be determined based on the maximum phase offset and the preset number of phase adjustment gears. It can be understood that the phase fluctuation range of the DQS signal is not limited to half of the clock cycle of the DRAM. In actual application, it can be flexibly adjusted based on the fluctuation range of the tdqsck parameter. It can also be understood that in actual application, the phase of the DQS signal may shift to the left or right. Therefore, the aforementioned maximum phase shift actually refers to one direction (ie, left or right). Maximum phase offset.

Step 102: Phase-adjust the initial gating pulse signal based on the phase adjustment step to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal corresponds to the previous correction node. gating pulse signal.

Specifically, the phase adjustment of the initial gate pulse signal based on the phase adjustment step to obtain the first gate pulse signal set and the second gate pulse signal set specifically includes:

The initial gate pulse signal is shifted to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and the initial gate pulse signal is shifted to the right N times based on the phase adjustment step to obtain the first gate pulse signal set. A second set of gated pulse signals is obtained; where N is the preset number of phase adjustment gears.

It can be understood that the correction nodes in the embodiment of the present application can be set according to actual needs, for example, correction can be performed based on a preset time interval, or correction can be performed in units of one read operation, which is not specifically limited in the embodiment of the present application. However, it is worth noting that before the DRAM is officially put into use, the first accurate gating pulse signal is still obtained by training the DQSgating signal in advance. Based on this, after the DRAM is officially put into use, this application can be used The gate pulse signal correction method of the embodiment corrects the gate pulse signal obtained by training without re-training, thereby performing fast and accurate correction of the gate pulse signal without affecting normal access to the DRAM.

It can also be understood from Figure 2 that the rising edge of the gate pulse signal corresponding to the previous correction node is aligned with the rising edge of the DQS valid signal corresponding to the previous correction node. Therefore, the previous correction node can perform accurate data Read. However, due to changes in the tdqsck parameter, the phase of the DQS signal will also change, so the rising edge of the DQS valid signal corresponding to the current correction node will be offset. If the gating pulse signal corresponding to the previous correction node is still used, data will be read. mistake. Based on this, the embodiment of the present application shifts the initial gate pulse signal to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and shifts the initial gate pulse signal to the left based on the phase adjustment step. Shift right N times to obtain the second gated pulse signal set, and sample the DQS signal corresponding to the current correction node through the gated pulse signals in the first and second gated pulse signal sets to determine the current correction node. The offset of the corresponding DQS signal is used to correct the gate pulse signal. It can be understood that N is the preset number of phase adjustment gears, the first gate pulse signal set includes N gate pulse signals corresponding to N shifts to the left, and the second gate pulse signal set The pulse signal set includes N gated pulse signals corresponding to N shifts to the right. Based on this, the first gating pulse signal set covers the leftward phase offset relative to the initial gating pulse signal from 1 phase adjustment step to N phase adjustment steps (corresponding to the maximum phase deviation Shift) N gating pulse signals, the second gating pulse signal set covers the rightward phase offset relative to the initial gating pulse signal from 1 phase adjustment step to N phase adjustment N gated pulse signals of step size (corresponding to the maximum phase offset). On this basis, through the gated pulse signals in the first gated pulse signal set and the second gated pulse signal set By sampling the data strobe signal corresponding to the current correction node, the offset of the DQS signal corresponding to the current correction node must be determined.

Step 103: Sample the data strobe signal corresponding to the current correction node based on the gate pulse signal in the first gate pulse signal set and the second gate pulse signal set to obtain a first sample value sequence and The second sequence of sampled values.

Specifically, the data strobe signal corresponding to the current correction node is sampled based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set to obtain the first sampling value. sequence and the second sampled value sequence, specifically including:

Based on the rising edges of N gate pulse signals in the first gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding first sample value set, and based on the first The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting the sample values in the first sample value set to obtain the first sample value sequence;

Based on the rising edges of N gate pulse signals in the second gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding second sample value set, and based on the second The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal is used to sort the sample values in the second sample value set to obtain a second sample value sequence.

It can be understood that based on the above method, the sampling values at different positions of the data strobe signal corresponding to the current correction node can be obtained. For the first set of sampled values, the embodiment of the present application preferably sorts the sampled values in descending order according to the phase offset of the corresponding gating pulse signal relative to the initial gating pulse signal. For the two sampled value sets, the embodiment of the present application preferably sorts the sampled values in order from small to large according to the phase offset of the corresponding gating pulse signal relative to the initial gating pulse signal. As can be seen from Figure 2, based on this, It can ensure that the first sampled value sequence and the second sampled value sequence can intuitively feedback the sampled values from left to right of the data strobe signal corresponding to the current correction node. Based on this, it can be based on the first sampled value sequence and the second sampled value. The sequence quickly determines the phase correction value of the gated pulse signal.

Step 104: Determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, and correct the initial gate pulse signal based on the phase correction value to obtain the target gate pulse signal. , and use the target gating pulse signal as the gating pulse signal corresponding to the current correction node.

Specifically, Figure 3 is a schematic flow chart of the phase correction value determination provided by the present application. As shown in Figure 3, the phase correction value of the gated pulse signal is determined based on the first sample value sequence and the second sample value sequence, Specifically include:

Step 201: Determine the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence;

Step 202: Determine the phase correction value of the gate pulse signal based on the current phase offset direction and phase offset amount of the initial gate pulse signal.

Determining the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:

When the sampled values in the first sampled value sequence are all 0 and the sampled values in the second sampled value sequence are all 1, it is determined that the initial gating pulse signal has no offset;

In the case where the sample values in the first sample value sequence and the second sample value sequence both include 0 and 1, the determination is based on the positions and numbers of 0 and 1 in the first sample value sequence and the second sample value sequence. The current phase offset direction and phase offset amount of the initial gating pulse signal.

It can be understood from Figure 2 that when the sample values in the first sample value sequence are all 0 and the sample values in the second sample value sequence are all 1, it means that the DQS signal has no offset, so it is judged that the The initial gating pulse signal has no offset;

When the sampled values in the first sampled value sequence and the second sampled value sequence both include 0 and 1, there will be two situations. The first situation: the sampled values in the first sampled value sequence are N-M in sequence. 0s and M 1s. The sampled values in the second sample value sequence are N-M 1s and M 0s, indicating that the DQS signal has been shifted to the left by M phase adjustment steps relative to the previous correction node, that is, the initial gate The control pulse signal is shifted to the right by M phase adjustment steps relative to the DQS signal (that is, the current phase shift direction of the initial gate pulse signal is to the right, and the phase shift amount is M phase adjustment steps). Based on this That is, the phase correction value of the gate pulse signal is determined and the initial gate pulse signal is corrected based on the phase correction value to obtain the target gate pulse signal. It can be understood that the phase correction value in the embodiment of the present application can be a positive value or a negative value. A positive value represents a shift to the right, and a negative value represents a shift to the left.

The second situation: the sampled values in the first sampled value sequence are M 1s and N-M 0s, and the sampled values in the second sampled value sequence are M 0s and N-M 1s, indicating that the DQS signal is relatively different from the previous one. The correction node is shifted to the right by M phase adjustment steps, that is, the initial gate pulse signal is shifted to the left by M phase adjustment steps relative to the DQS signal (that is, the current phase shift direction of the initial gate pulse signal is toward Left, the phase offset is M phase adjustment steps), based on which the phase correction value of the gate pulse signal can be determined and the initial gate pulse signal can be corrected based on the phase correction value. It can be understood that M is a positive integer less than N. It can also be understood that the embodiments of the present application can respectively realize the phase adjustment of the initial gate pulse signal and the sampling of the data strobe signal corresponding to the current correction node through any existing phase adjustment circuit and sampling circuit. Which one is specifically used? Class circuit, the embodiments of this application are not specifically limited here.

The method provided by the embodiment of the present application determines the maximum phase offset based on the clock cycle of the DRAM, and determines the phase adjustment step based on the maximum phase offset; the initial gating pulse signal is processed based on the phase adjustment step. The phase is adjusted to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating pulse signal corresponding to the previous correction node; respectively based on the first gating pulse signal set Sampling the data strobe signal corresponding to the current correction node with the gate pulse signal in the second gate pulse signal set to obtain a first sample value sequence and a second sample value sequence; based on the first sample value sequence and the second sequence of sampled values to determine the phase correction value of the gated pulse signal, correct the initial gated pulse signal based on the phase correction value to obtain the target gated pulse signal, and use the target gated pulse signal as Compared with the existing method of correcting the gate pulse signal through training, the gate pulse signal corresponding to the current correction node can be quickly and accurately corrected without affecting the normal access of the DRAM, which greatly improves the performance of the DRAM. work efficiency.

Based on any of the above embodiments, Figure 4 is a schematic structural diagram of a device for correcting gate pulse signals in DRAM provided by this application. As shown in Figure 4, the device includes:

The first determination module 301 is used to determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset;

The gate pulse signal set generation module 302 is configured to perform phase adjustment on the initial gate pulse signal based on the phase adjustment step to obtain a first gate pulse signal set and a second gate pulse signal set; the initial gate The pulse signal is the gate pulse signal corresponding to the previous correction node;

The sampling value sequence generation module 303 is configured to sample the data strobe signal corresponding to the current correction node based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sequence of sampled values and a sequence of second sampled values;

Signal correction module 304, configured to determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, and correct the initial gate pulse signal based on the phase correction value to obtain the target Gating pulse signal, and using the target gate pulse signal as the gating pulse signal corresponding to the current correction node.

The device provided by the embodiment of the present application uses the first determination module 301 to determine the maximum phase offset based on the clock cycle of the DRAM, and determines the phase adjustment step based on the maximum phase offset; the gate pulse signal set generation module 302 is based on The phase adjustment step performs phase adjustment on the initial gating pulse signal to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating pulse corresponding to the previous correction node signal; the sampling value sequence generation module 303 samples the data strobe signal corresponding to the current correction node based on the gate pulse signal in the first gate pulse signal set and the second gate pulse signal set respectively to obtain the third A sequence of sampled values and a second sequence of sampled values; the signal correction module 304 determines the phase correction value of the gated pulse signal based on the first sequence of sampled values and the second sequence of sampled values, and corrects the initial gate pulse signal based on the phase corrected value. The gated pulse signal is corrected to obtain the target gated pulse signal, and the target gated pulse signal is used as the gated pulse signal corresponding to the current correction node. Compared with the existing method of correcting the gated pulse signal through training, it is possible to The gate pulse signal can be quickly and accurately corrected without affecting the normal access of the DRAM, which greatly improves the working efficiency of the DRAM.

Based on the above embodiment, the maximum phase offset is the phase offset corresponding to half of the clock cycle of the DRAM. Correspondingly, the phase adjustment step is the maximum phase offset and the preset phase adjustment gear. Quotient of digits.

Based on any of the above embodiments, the phase adjustment of the initial gate pulse signal based on the phase adjustment step to obtain the first gate pulse signal set and the second gate pulse signal set specifically includes:

The initial gate pulse signal is shifted to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and the initial gate pulse signal is shifted to the right N times based on the phase adjustment step to obtain the first gate pulse signal set. A second set of gated pulse signals is obtained; where N is the preset number of phase adjustment gears.

Based on any of the above embodiments, the first gate pulse signal set includes N gate pulse signals corresponding to N shifts to the left, and the second gate pulse signal set includes N shifts to the right. Corresponding N gate pulse signals.

Based on any of the above embodiments, the data strobe signal corresponding to the current correction node is sampled based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set to obtain The first sample value sequence and the second sample value sequence specifically include:

Based on the rising edges of N gate pulse signals in the first gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding first sample value set, and based on the first The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting the sample values in the first sample value set to obtain the first sample value sequence;

Based on the rising edges of N gate pulse signals in the second gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding second sample value set, and based on the second The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal is used to sort the sample values in the second sample value set to obtain a second sample value sequence.

Based on any of the above embodiments, determining the phase correction value of the gated pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:

Determine the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence;

The phase correction value of the gate pulse signal is determined based on the current phase offset direction and phase offset amount of the initial gate pulse signal.

Based on any of the above embodiments, determining the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:

When the sampled values in the first sampled value sequence are all 0 and the sampled values in the second sampled value sequence are all 1, it is determined that the initial gating pulse signal has no offset;

In the case where the sample values in the first sample value sequence and the second sample value sequence both include 0 and 1, the determination is based on the positions and numbers of 0 and 1 in the first sample value sequence and the second sample value sequence. The current phase offset direction and phase offset amount of the initial gating pulse signal.

Figure 5 illustrates a schematic diagram of the physical structure of an electronic device. As shown in Figure 5, the electronic device may include: a processor 401, a communication interface 402, a memory 403, and a communication bus 404. The processor 401, the communication interface 402, The memories 403 communicate with each other through the communication bus 404. The processor 401 can call the logic instructions in the memory 403 to execute the correction method of the gate pulse signal in the DRAM provided by the above methods. The method includes: determining the maximum phase offset based on the clock cycle of the DRAM, and based on the The maximum phase offset determines the phase adjustment step; the initial gate pulse signal is phase adjusted based on the phase adjustment step to obtain the first gate pulse signal set and the second gate pulse signal set; the initial gate The control pulse signal is the gate control pulse signal corresponding to the previous correction node; the data corresponding to the current correction node is selected based on the gate control pulse signals in the first gate control pulse signal set and the second gate control pulse signal set respectively. The pass signal is sampled to obtain a first sampled value sequence and a second sampled value sequence; a phase correction value of the gated pulse signal is determined based on the first sampled value sequence and the second sampled value sequence, and the phase correction value of the gated pulse signal is determined based on the phase correction value. The initial gating pulse signal is corrected to obtain a target gating pulse signal, and the target gating pulse signal is used as the gating pulse signal corresponding to the current correction node.

In addition, the above-mentioned logical instructions in the memory 403 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), magnetic disk or optical disk and other various media that can store program codes.

On the other hand, the present application also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can Execute the method for correcting the gate pulse signal in the DRAM provided by the above methods. The method includes: determining the maximum phase offset based on the clock cycle of the DRAM, and determining the phase adjustment step based on the maximum phase offset; The phase adjustment step performs phase adjustment on the initial gating pulse signal to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating pulse corresponding to the previous correction node signal; sampling the data strobe signal corresponding to the current correction node based on the gate pulse signal in the first gate pulse signal set and the second gate pulse signal set respectively to obtain the first sample value sequence and the first sample value sequence. Two sampling value sequences; determining the phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, and correcting the initial gating pulse signal based on the phase correction value to obtain the target gating pulse signal, and use the target gate pulse signal as the gate pulse signal corresponding to the current correction node.

On the other hand, the present application also provides a non-transitory computer-readable storage medium on which a computer program is stored. The computer program is implemented when executed by the processor to perform the correction of the gate pulse signal in the DRAM provided by the above methods. Method, the method includes: determining the maximum phase offset based on the clock cycle of the DRAM, and determining the phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step To obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating pulse signal corresponding to the previous correction node; respectively based on the first gating pulse signal set and the The gate pulse signal in the second gate pulse signal set samples the data strobe signal corresponding to the current correction node to obtain a first sample value sequence and a second sample value sequence; based on the first sample value sequence and the second sample value sequence The two-sample value sequence determines the phase correction value of the gated pulse signal, corrects the initial gated pulse signal based on the phase correction value to obtain the target gated pulse signal, and uses the target gated pulse signal as the current correction The gate pulse signal corresponding to the node.

The device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in One location, or it can be distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Persons of ordinary skill in the art can understand and implement the method without any creative effort.

Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions can be embodied in the form of software products in essence or in part that contribute to the existing technology. The computer software products can be stored in computer-readable storage media, such as ROM, disks, Optical disc, etc., including a number of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims (6)

1. A method for correcting gate pulse signals in DRAM, characterized in that the method includes: Determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset; The initial gating pulse signal is phase adjusted based on the phase adjustment step to obtain the first gating pulse signal set and the second gating pulse signal set; the initial gating pulse signal is the gating corresponding to the previous correction node. Pulse signal; Sampling the data strobe signal corresponding to the current correction node based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set respectively to obtain the first sampling value sequence and the second sampling value sequence; Determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, correct the initial gate pulse signal based on the phase correction value to obtain the target gate pulse signal, and The target gate pulse signal is used as the gate pulse signal corresponding to the current correction node; The maximum phase offset is the phase offset corresponding to half of the clock cycle of the DRAM. Correspondingly, the phase adjustment step is the quotient of the maximum phase offset and the preset number of phase adjustment gears; The phase adjustment of the initial gating pulse signal based on the phase adjustment step to obtain the first gating pulse signal set and the second gating pulse signal set specifically includes: The initial gate pulse signal is shifted to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and the initial gate pulse signal is shifted to the right N times based on the phase adjustment step to obtain the first gate pulse signal set. Obtain a second set of gated pulse signals; where N is the preset number of phase adjustment gears; The data strobe signal corresponding to the current correction node is sampled based on the gate pulse signal in the first gate pulse signal set and the second gate pulse signal set respectively to obtain the first sample value sequence and the first sample value sequence. Two sample value sequences, including: Based on the rising edges of N gate pulse signals in the first gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding first sample value set, and based on the first The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting the sample values in the first sample value set to obtain the first sample value sequence; Based on the rising edges of N gate pulse signals in the second gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding second sample value set, and based on the second The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting each sample value in the second sample value set to obtain a second sample value sequence; Determining the phase correction value of the gated pulse signal based on the first sample value sequence and the second sample value sequence specifically includes: Determine the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence; The phase correction value of the gate pulse signal is determined based on the current phase offset direction and phase offset amount of the initial gate pulse signal. 2. The method for correcting gate pulse signals in DRAM according to claim 1, wherein the first gate pulse signal set includes N gate pulse signals corresponding to N times of leftward shift, so The second gating pulse signal set includes N gating pulse signals corresponding to N rightward shifts. 3. The method for correcting gate pulse signals in DRAM according to claim 1, wherein the current phase of the initial gate pulse signal is determined based on the first sample value sequence and the second sample value sequence. Offset direction and phase offset, including: When the sampled values in the first sampled value sequence are all 0 and the sampled values in the second sampled value sequence are all 1, it is determined that the initial gating pulse signal has no offset; In the case where the sample values in the first sample value sequence and the second sample value sequence both include 0 and 1, the determination is based on the positions and numbers of 0 and 1 in the first sample value sequence and the second sample value sequence. The current phase offset direction and phase offset amount of the initial gating pulse signal. 4. A device for correcting gate pulse signals in DRAM, characterized in that the device includes: A first determination module, configured to determine the maximum phase offset based on the clock cycle of the DRAM, and determine the phase adjustment step based on the maximum phase offset; A gated pulse signal set generation module, configured to perform phase adjustment on the initial gated pulse signal based on the phase adjustment step to obtain a first gated pulse signal set and a second gated pulse signal set; the initial gated pulse The signal is the gate pulse signal corresponding to the previous correction node; A sampling value sequence generating module, configured to sample the data strobe signal corresponding to the current correction node based on the gating pulse signal in the first gating pulse signal set and the second gating pulse signal set respectively to obtain the first a sequence of sampled values and a second sequence of sampled values; A signal correction module, configured to determine the phase correction value of the gate pulse signal based on the first sample value sequence and the second sample value sequence, and correct the initial gate pulse signal based on the phase correction value to obtain the target gate control pulse signal, and use the target gate pulse signal as the gate pulse signal corresponding to the current correction node; The maximum phase offset is the phase offset corresponding to half of the clock cycle of the DRAM. Correspondingly, the phase adjustment step is the quotient of the maximum phase offset and the preset number of phase adjustment gears; The phase adjustment of the initial gating pulse signal based on the phase adjustment step to obtain the first gating pulse signal set and the second gating pulse signal set specifically includes: The initial gate pulse signal is shifted to the left N times based on the phase adjustment step to obtain the first gate pulse signal set, and the initial gate pulse signal is shifted to the right N times based on the phase adjustment step to obtain the first gate pulse signal set. Obtain a second set of gated pulse signals; where N is the preset number of phase adjustment gears; The data strobe signal corresponding to the current correction node is sampled based on the gate pulse signal in the first gate pulse signal set and the second gate pulse signal set respectively to obtain the first sample value sequence and the first sample value sequence. Two sample value sequences, including: Based on the rising edges of N gate pulse signals in the first gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding first sample value set, and based on the first The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting the sample values in the first sample value set to obtain the first sample value sequence; Based on the rising edges of N gate pulse signals in the second gate pulse signal set, the data strobe signal corresponding to the current correction node is sampled respectively to obtain the corresponding second sample value set, and based on the second The phase offset of the gate pulse signal corresponding to each sample value in the sample value set relative to the initial gate pulse signal, and sorting each sample value in the second sample value set to obtain a second sample value sequence; Determining the phase correction value of the gated pulse signal based on the first sample value sequence and the second sample value sequence specifically includes: Determine the current phase offset direction and phase offset amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence; The phase correction value of the gate pulse signal is determined based on the current phase offset direction and phase offset amount of the initial gate pulse signal. 5. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that when the processor executes the program, it implements claim 1 Go to the steps of the method for correcting the gate pulse signal in DRAM described in any one of 3. 6. A non-transitory computer-readable storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, the gating pulse in the DRAM according to any one of claims 1 to 3 is realized. Signal correction method steps.