CN116555904A - Base and device for epitaxial growth of silicon wafer - Google Patents

Abstract

The embodiment of the present invention discloses a base and a device for silicon wafer epitaxial growth; the base includes: an annular area not in contact with the silicon wafer, and the annular area is located A circular area where the sheets are in contact, the circular area is on the radial inner side of the annular area; wherein, the circular area is divided into a circular sub-area and a plurality of annular sub-areas, and in the circular area Holes with different distribution densities are provided in the sub-region and the plurality of annular sub-regions to change the temperature distribution of the surface area of the silicon wafer through the holes.

Description

A base and device for silicon wafer epitaxial growth

technical field

Embodiments of the present invention relate to the technical field of epitaxial growth of silicon wafers, and in particular to a base and a device for epitaxial growth of silicon wafers.

Background technique

The epitaxial growth process of silicon wafers is an important process in the semiconductor chip manufacturing process. This process refers to growing a layer of crystal-free primary particles (Crystal Originated Particles, COP) defect and oxygen-free precipitated silicon single crystal layer. The epitaxial growth methods of silicon wafers mainly include vacuum epitaxial deposition, vapor phase epitaxial deposition, and liquid phase epitaxial deposition. Among them, vapor phase epitaxial deposition is the most widely used. This method is to react silicon source gas with hydrogen in a high temperature environment A silicon single crystal is generated and deposited on the surface of a polished silicon wafer to obtain an epitaxial layer, and at the same time, a dopant, such as B ₂ H ₆ or PH ₃ , is introduced to dope the epitaxial layer to obtain the required resistivity. If not otherwise stated, the epitaxial growth mentioned in the present invention refers to the epitaxial growth accomplished by vapor phase epitaxial deposition.

For the epitaxial growth of silicon wafers, flatness is an important index to measure the quality of epitaxial silicon wafers, and the flatness of epitaxial silicon wafers is directly related to the thickness of the epitaxial layer. During the epitaxial growth process, the temperature in the reaction chamber generated by the heating bulb, the concentration of the silicon source gas, the flow rate of the silicon source gas, etc. will all have a very obvious impact on the thickness of the epitaxial layer. In addition, the crystal orientation of the silicon wafer is another important factor affecting the thickness of the epitaxial layer and thus the flatness of the epitaxial silicon wafer. The following is a detailed introduction to the crystal orientation of the silicon wafer and the influence of the crystal orientation on the thickness of the epitaxial layer.

Referring to FIG. 1 , FIG. 1 shows the crystal orientation of the silicon wafer by taking the silicon wafer W of the (100) crystal plane as an example. As shown in Figure 1, if the three o'clock direction of the silicon wafer W is the radial direction of 0°/360° and is the <110> crystal orientation, the clockwise rotation relative to the radial direction of 0°/360° The radial directions of 90°, 180° and 270° are also the <110> crystal orientation of the silicon wafer W, while the 45°, 135°, 225° and 315 The radial direction of ° is the <100> crystal orientation of the silicon wafer W. That is to say, for the silicon wafer W, the four <110> crystal orientations correspond to the four radial directions distributed at 90° intervals along the circumference of the silicon wafer, and the four <100> crystal orientations also correspond to the four radial directions along the silicon wafer. The four radial directions distributed at intervals of 90° in the circumferential direction of the wafer correspond to each other, while the adjacent <110> crystal directions and <100> crystal directions are separated by 45° along the circumferential direction of the silicon wafer.

Referring to FIG. 2, it shows the edge of a silicon wafer W having a diameter of 300 mm as shown in FIG. Edge Site Frontsurface-referenced least sQuares/Range (ESFQR) results. In Fig. 2, the abscissa represents the angle in the radial direction of the silicon wafer W shown in Fig. 1, and the ordinate represents the ESFQR value (in nm) of the silicon wafer W at the corresponding angular position, which can reflect the growth The thickness of the epitaxial layer. As shown in Figure 2, in the radial directions of 0°/360°, 90°, 180° and 270°, the thickness of the epitaxial layer grown on the silicon wafer W is at a peak value, that is, the thickness of the silicon wafer W is <110 >The growth rate is greatest for the crystallographic directions; from the radial directions of 0°, 90°, 180° and 270° to the radial directions of 45°, 135°, 225° and 315° and from the radial directions of 90°, 180°, 270° From the radial direction of 360° to the radial direction of 45°, 135°, 225° and 315°, the thickness of the epitaxial layer grown on the silicon wafer W gradually decreases, that is to say, the growth rate of the silicon wafer W changes from < The 110> crystal orientation gradually decreases from the <100> crystal orientation, which is also shown by the arrowed arc in Fig. 1, where the arrow direction indicates the direction of growth rate decrease; at 45°, 135°, 225° and 315° ° in the radial direction, the thickness of the epitaxial layer grown on the silicon wafer W is a valley value, that is to say, the growth rate of the silicon wafer W in the <100> crystal direction is the smallest, and as known in the prior art, The above thickness difference is more obvious in the region closer to the radial edge of the silicon wafer. Since the thickness of the epitaxial layer is directly related to the resistivity, it is of great significance to control the thickness uniformity of the epitaxial layer of the silicon wafer.

Contents of the invention

In view of this, the embodiment of the present invention expects to provide a susceptor and device for epitaxial growth of a silicon wafer; the uniformity of the thickness of the epitaxial layer and the uniformity of the resistivity can be adjusted by changing the temperature distribution of each area of the silicon wafer, Further, the flatness and product yield of the epitaxial silicon wafer are improved.

The technical scheme of the embodiment of the present invention is realized like this:

In a first aspect, an embodiment of the present invention provides a base for epitaxial growth of a silicon wafer, the base includes:

an annular area not in contact with the silicon wafer, said annular area being located at the peripheral edge of the susceptor;

A circular area in contact with the silicon wafer, the circular area is at the radial inner side of the annular area; wherein,

The circular area is divided into a circular sub-area and a plurality of annular sub-areas, and holes with different distribution densities are provided in the circular sub-area and the plurality of annular sub-areas to change the silicon wafer through the holes. The temperature distribution of the surface area.

Optionally, the multiple annular subareas include: a first annular subarea, a second annular subarea, a third annular subarea, and a fourth annular subarea; wherein,

The first annular sub-area is located radially inward of and adjacent to the annular area;

The second annular subregion is radially adjacent to the first annular subregion;

The third annular subregion is radially adjacent to the second annular subregion;

The fourth annular subarea is located between the circular subarea and the third annular subarea in the radial direction.

Optionally, the third annular sub-region has a diameter ranging from 50 mm to 75 mm.

Optionally, the distribution density of holes provided on the third annular sub-region is 4.8 ea/cm ² .

Optionally, the diameter of the second annular sub-region ranges from 75 mm to 90 mm.

Optionally, the distribution density of holes provided on the second annular sub-region is 4.0 ea/cm ² .

Optionally, the fourth ring-shaped sub-region has a diameter ranging from 40 mm to 50 mm.

Optionally, the distribution density of holes provided on the fourth annular sub-region is 4.0 ea/cm ² .

Optionally, the hole distribution density of the circular sub-region and the first annular sub-region is 3.0 ea/cm ² -3.5 ea/cm ² .

In a second aspect, an embodiment of the present invention provides a device for epitaxial growth of a silicon wafer, the device comprising

According to the base described in the first aspect, the base is used to carry a silicon chip;

a pedestal support frame, the pedestal support frame is used to support the pedestal and drive the pedestal to rotate around the central axis X at a certain speed during epitaxial growth;

an upper bell jar and a lower bell jar, the upper bell jar and the lower bell jar together enclose a reaction chamber containing the base;

an air inlet for sequentially delivering cleaning gas and silicon source gas into the reaction chamber;

an exhaust port, the exhaust port is used to discharge the respective reaction tail gases of the cleaning gas and the silicon source gas out of the reaction chamber;

A plurality of heating bulbs are arranged on the periphery of the upper quartz bell jar and the lower quartz bell jar and are used to provide a high temperature environment for vapor phase epitaxy deposition in the reaction chamber through the upper bell jar and the lower bell jar.

Embodiments of the present invention provide a base and a device for epitaxial growth of silicon wafers; Holes with different distribution densities are set in different areas of the circular area. Since the distribution density of the holes on the circular area is not the same, the heat received by the corresponding silicon wafer surface will also be different, and the temperature distribution of each area on the silicon wafer surface will also be different. Therefore, the uniformity of the thickness of the epitaxial layer on the surface of the silicon wafer can be controlled by changing the temperature distribution in different regions on the surface of the silicon wafer, thereby improving the uniformity of the resistivity of the epitaxial layer.

Description of drawings

Fig. 1 is the schematic diagram of <110> crystal direction and <100> crystal direction of the silicon chip of (100) crystal plane that the embodiment of the present invention provides;

Fig. 2 is the ESFQR result of the silicon wafer shown in Fig. 1 in the case of using a conventional susceptor for epitaxial growth of silicon wafer provided by the embodiment of the present invention;

3 is a schematic diagram of an existing device for silicon wafer epitaxial growth provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of changes in the thickness of the epitaxial layer at different regions of the silicon wafer provided by the embodiment of the present invention;

Fig. 5 is a schematic diagram of the epitaxial layer thickness distribution morphology of each region of the silicon wafer corresponding to Fig. 4;

Fig. 6 is a schematic diagram of the resistivity change of the epitaxial layer at different regions of the silicon wafer provided by the embodiment of the present invention;

Fig. 7 is a schematic diagram of the resistivity distribution morphology of the epitaxial layer in each region of the silicon wafer corresponding to Fig. 6;

FIG. 8 is a schematic structural view of a susceptor for epitaxial growth of a silicon wafer provided by an embodiment of the present invention;

Fig. 9 is a schematic diagram of the base structure provided by the comparative example;

FIG. 10 is a schematic diagram of the surface morphology of an epitaxial silicon wafer obtained by epitaxial growth of the pedestal shown in FIG. 9;

Fig. 11 is a schematic diagram of changes in the thickness of the epitaxial layer before and after changing the base provided by the embodiment of the present invention;

Fig. 12 is a schematic diagram of the change in resistivity of the epitaxial layer before and after changing the base provided by the embodiment of the present invention;

FIG. 13 is a schematic diagram of the composition of a device for epitaxial growth of a silicon wafer provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention.

Referring to FIG. 3 , it shows a schematic diagram of an existing device 1 for epitaxial growth of a silicon wafer W. Referring to FIG. As shown in Figure 3, the device 1 may include:

A base 10', the base 10' is used to carry a silicon wafer W;

The base support frame 20 is used to support the base 10' and drive the base 10' to rotate around the central axis X at a certain speed during the epitaxial growth; wherein during the rotation of the base 10', the silicon The wafer W rotates with the base 10' around the central axis X, that is to say the silicon wafer W remains stationary relative to the base 10', thus requiring the radial edges of the base 10' to be in contact with the adjacent parts 10A (usually There is a small gap G between them for the preheating ring;

The upper quartz bell jar 30A and the lower quartz bell jar 30B, the upper quartz bell jar 30A and the lower quartz bell jar 30B together enclose the reaction chamber RC in which the base 10' and the base support frame 20 are accommodated; wherein the base 10 'The reaction chamber RC is divided into an upper reaction chamber RC1 and a lower reaction chamber RC2, and the silicon wafer W is placed in the upper reaction chamber RC1; usually, the air pressure in the upper reaction chamber RC1 is slightly greater than that in the lower reaction chamber RC2 The gas pressure in the upper reaction chamber RC1 will enter the lower reaction chamber RC2 through the gap G;

An air inlet 40, which is used to deliver reaction gas to the upward reaction chamber RC1, such as silicon source gas such as SiHCl ₃ , hydrogen, dopant gas such as B ₂ H ₆ or PH ₃ , so that silicon atoms are generated by reacting silicon source gas with hydrogen and deposited on the silicon wafer W to grow an epitaxial layer on the silicon wafer W, while doping the epitaxial layer with a dopant gas to obtain the required resistivity;

Exhaust port 50, the exhaust port 50 is used to discharge the reaction tail gas out of the reaction chamber RC;

A plurality of heating bulbs 60 provided on the peripheries of the upper quartz bell jar 30A and the lower quartz bell jar 30B and for providing in the reaction chamber RC through the upper bell jar 30A and the lower quartz bell jar 30B for vapor phase epitaxial deposition high temperature environment;

Mounting part 70 for assembling the individual elements of device 1 .

It should be noted that due to the influence of the temperature field structure in the chamber RC, in the actual process of epitaxial growth, although the uniformity of the thickness of the epitaxial layer can be improved by adjusting the relevant process steps and process parameters (recipe) to increase the resistivity Uniformity; however, there are still problems of epitaxial layer thickness and resistivity non-uniformity. For example, as shown in FIG. 4 , it shows a schematic diagram of the variation of the thickness of the epitaxial layer at different regions of the silicon wafer W. It should be noted that during the specific implementation process, it can be found that the epitaxial layer in the region with a high surface temperature of the silicon wafer W The thickness of the epitaxial layer is relatively large, and on the contrary, the thickness of the epitaxial layer is small in the area where the surface temperature of the silicon wafer W is low; at the same time, it can be seen from Figure 5 that the thickness of the epitaxial layer in each area of the silicon wafer is distributed in a ring shape; The resistivity of the epitaxial layer is shown in Figure 6, which shows a schematic diagram of the change of the resistivity of the epitaxial layer at different regions of the silicon wafer W. It should be noted that during the specific implementation process, it can be found that the surface temperature of the silicon wafer W is high The resistivity of the epitaxial layer in the region is small, and on the contrary, the resistivity of the epitaxial layer in the region with low surface temperature of the silicon wafer W is relatively large; at the same time, it can be seen from Figure 7 that the resistivity of the epitaxial layer is distributed in a ring; During the epitaxial growth process, the thickness and resistivity of the epitaxial layer are distributed in a ring shape. At the same time, the thickness of the epitaxial layer is large and the resistivity is low in the area where the surface temperature of the silicon wafer W is high; on the contrary, the thickness of the epitaxial layer is small in the area where the surface temperature of the silicon wafer W is low. High resistivity.

It should be noted that, in FIG. 7 , the part of the pattern with a light color indicates that the resistivity of the epitaxial layer in this region is relatively low.

It should be noted that the phenomenon and problems of uneven epitaxial layer thickness and resistivity appearing above are difficult to be improved or eliminated by changing the process steps and process parameters (recipe): this is mainly due to the fact that, for example, the epitaxial layer in the central area of the silicon wafer W The high layer thickness affects the uniformity of the epitaxial layer thickness. If the thickness of the epitaxial layer in the central area of the silicon wafer W is reduced, the resistivity of the corresponding position will decrease, but the resistivity of the epitaxial layer in the central area of the silicon wafer W is already lower than that of other Therefore, if the resistivity of the central region is further reduced, the resistivity uniformity of the epitaxial layer will become worse; similarly, if the resistivity uniformity of the epitaxial layer is increased, the thickness uniformity of the epitaxial layer will become worse.

Based on the above description, the embodiment of the present invention expects to improve the structure of the base 10 ′, so as to adjust the uniformity of the epitaxial layer thickness and resistivity of the silicon wafer W by changing the temperature distribution in different regions of the silicon wafer W. Therefore, referring to FIG. 8 , it shows a pedestal 10 for epitaxial growth of a silicon wafer W provided by an embodiment of the present invention, the pedestal 10 includes:

An annular area 81 not in contact with the silicon wafer W, said annular area 81 is located at the peripheral edge of the base 10;

A circular area 82 in contact with the silicon wafer W, the circular area 82 is located radially inside the annular area 81; wherein,

The circular area 82 is divided into a circular sub-area 821 and a plurality of annular sub-areas 822, and in the circular sub-area 821 and a plurality of annular sub-areas 822 are provided with holes of different distribution densities (Fig. 8 (shown by black dots in ) to change the temperature distribution of the surface area of the silicon wafer W through the holes.

It should be noted that although the annular area 81 includes two sub-areas, the two sub-areas are considered as an integral annular area 81 in the embodiment of the present invention for convenience of description.

Understandably, it can be seen from FIG. 5 and FIG. 7 that the thickness and resistivity of the epitaxial layer are distributed in a ring shape. Therefore, in view of this situation, the surface of the base 10 is compared with the silicon wafer W in the embodiment of the present invention. The contact circular area 82 is divided into different areas, and holes with different distribution densities are set in the different divided areas, so that the heat provided by the heating bulb 60 can be directly transferred to the silicon wafer W through the holes distributed on the circular area 82. surface. Since the distribution density of the holes on the circular area 82 is different, the heat received by the corresponding surface of the silicon wafer W will also be different, so that the temperature of each area on the surface of the silicon wafer W will also be different. Based on this, in combination with the distribution rules of epitaxial layer thickness and resistivity shown in FIG. 5 and FIG. And holes with different distribution densities are set in the plurality of annular sub-regions 822, which can change the temperature distribution in different regions on the surface of the silicon wafer W, thereby controlling the thickness of the epitaxial layer on the surface of the silicon wafer W, so as to improve the uniformity of the thickness of the epitaxial layer, and then also improve the thickness of the epitaxial layer. The uniformity of the resistivity of the epitaxial layer is improved.

For the technical solution shown in FIG. 8 , in some possible implementations, the plurality of annular subareas specifically include: a first annular subarea 8221 , a second annular subarea 8222 , a third annular subarea 8223 and a fourth annular subarea 8223 . Ring sub-region 8224; where,

The first annular sub-area 8221 is located radially inside the annular area 81 and adjacent to the annular area 81;

The second annular subregion 8222 is adjacent to the first annular subregion 8221 in the radial direction;

The third annular subregion 8223 is radially adjacent to the second annular subregion 8222;

The fourth annular subregion 8224 is located between the circular subregion 821 and the third annular subregion 8223 in the radial direction.

It can be understood that, in the specific implementation process, the annular area 81, the circular sub-area 821, the first annular sub-area 8221, the second annular sub-area 8222, the third annular sub-area 8223 and the fourth annular sub-area 8224 are all related to the basic Seat 10 have the same circle center.

In addition, it can be understood that according to the annular distribution of the thickness of the epitaxial layer and the resistivity of the epitaxial layer in FIG. 5 and FIG. There are multiple different areas, so that the divided circular area 821 and each annular sub-area 822 can receive different heat through holes with different distribution densities to change the temperature of the surface of the silicon wafer W by setting holes with different distribution densities. distribution, thereby improving the problems of non-uniform epitaxial layer thickness and non-uniform resistivity shown in Fig. 5 and Fig. 7 .

Regarding the above-mentioned implementation manners, in some examples, the diameter of the third annular sub-region 8223 is in a range of 50 mm to 75 mm.

Optionally, in some examples, the distribution density of holes provided on the third annular sub-region 8223 is 4.8 ea/cm ² .

Regarding the above-mentioned implementation manners, in some examples, the diameter of the second annular sub-region 8222 is in a range of 75 mm to 90 mm.

Optionally, in some examples, the hole distribution density set on the second annular sub-region 8222 is 4.0 ea/cm ² .

Regarding the above-mentioned implementation manners, in some examples, the diameter of the fourth annular sub-region 8224 is in a range of 40mm˜50mm.

Optionally, in some examples, the hole distribution density set on the fourth annular sub-region 8224 is 4.0 ea/cm ² .

For the above-mentioned implementation manners, in some examples, the hole distribution density of the circular sub-region 821 and the first annular sub-region 8221 is 3.0 ea/cm ² -3.5 ea/cm ² .

It should be noted that, the above-mentioned diameter ranges refer to calculation from the center of the base 10 along the radial direction of the base 10 .

It can be understood that, in the embodiment of the present invention, the hole distribution density on the third annular sub-region 8223 is higher than other regions, and its corresponding position is a region on the surface of the silicon wafer W with a small epitaxial layer thickness and high resistivity, so During the epitaxial growth process, since the hole distribution density on the third annular sub-region 8223 is large, the thickness of the epitaxial layer at the corresponding position on the surface of the silicon wafer W will increase, and the resistivity will decrease, so that the epitaxial layer on the surface of the silicon wafer W The layer thickness uniformity and resistivity uniformity will be improved; in addition, as the second annular sub-region 8222 and the fourth annular sub-region 8224 are regions adjacent to the third annular sub-region 8223, the distribution density of holes gradually changes transitionally, the effect is to avoid Generation of unusual patterns. This is mainly because, as shown in FIG. 9 , when holes are provided only in a local ring-shaped sub-region close to the center of the base 10, a sudden change in the distribution density of the holes will cause pattern abnormalities at corresponding positions on the silicon wafer W to occur. Specifically shown in Figure 10. Therefore, in the embodiment of the present invention, in order to improve the uniformity of the thickness of the epitaxial layer and the uniformity of the resistivity, holes with a high distribution density are set in the third annular sub-region 8223, and at the same time, in order to avoid abnormalities on the surface of the silicon wafer W during the epitaxial growth process Similarly, holes with a lower distribution density will be set in the circular sub-region 821, the first annular sub-region 8221, the second annular sub-region 8222 and the fourth annular sub-region 8224, so that the heat transferred to the surface of the silicon wafer W A transitional change is formed to make the temperature distribution on the surface of the silicon wafer W as uniform as possible, so as to improve the thickness uniformity and resistivity uniformity of the epitaxial layer of the silicon wafer W, and at the same time suppress the generation of abnormal patterns.

In addition, as shown in Figure 11 and Figure 12, Figure 11 shows a schematic diagram of changes in the thickness of the epitaxial layer before and after the base is changed, and the solid arrows in Figure 11 indicate the thickness of the epitaxial layer in each area of the silicon wafer before the base is changed , the dotted arrow indicates the change curve of the thickness of the epitaxial layer in each region of the silicon wafer after the base is changed; Figure 12 shows the schematic diagram of the change of the resistivity of the epitaxial layer before and after the base is changed, and the solid arrow in Figure 12 indicates is the change curve of the resistivity of the epitaxial layer in each region of the silicon wafer before the base is changed, and the dotted arrow indicates the change curve of the resistivity of the epitaxial layer in each region of the silicon wafer after the change of the base. It can be seen from FIG. 11 and FIG. 12 that the base 10 provided by the embodiment of the present invention can improve the uniformity of the thickness of the epitaxial layer and the resistivity.

Referring to FIG. 13, the embodiment of the present invention also provides a device 2 for epitaxial growth of a silicon wafer W. The device 2 replaces the pedestal 10' shown in FIG. 3 with the pedestal 10 provided by the embodiment of the present invention get. Specifically, the device 2 may include:

The base 10 provided by the embodiment of the present invention, the base 10 is used to carry the silicon wafer W;

a base support frame 20, the base support frame 20 is used to support the base 10 and drive the base 10 to rotate around the central axis X at a certain speed during epitaxial growth;

an upper bell jar 30A and a lower bell jar 30B, the upper bell jar 30A and the lower bell jar 30B together enclose a reaction chamber RC for accommodating the base 10;

an air inlet 40, the air inlet 40 is used to sequentially deliver cleaning gas and silicon source gas into the reaction chamber RC;

The exhaust port 50 is used for exhausting the respective reaction tail gases of the cleaning gas and the silicon source gas out of the reaction chamber RC.

A plurality of heating bulbs 60 are provided on the periphery of the upper quartz bell jar 30A and the lower quartz bell jar 30B and are used to provide the vapor phase epitaxial deposition in the reaction chamber through the upper bell jar 30A and the lower bell jar 30B. high temperature environment;

In addition, the same as the existing device 1 for the epitaxial growth of silicon wafer W, the device 2 may also include a mounting component 70 and so on, which will not be repeated here.

It should be noted that: the technical solutions described in the embodiments of the present invention can be combined arbitrarily if there is no conflict.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A susceptor for epitaxial growth of silicon wafers, the susceptor comprising:

an annular region not in contact with the silicon wafer, the annular region being located at a circumferential edge of the susceptor;

a circular region in contact with the silicon wafer, the circular region being radially inward of the annular region; wherein,,

the circular area is divided into a circular subarea and a plurality of annular subareas, and holes with different distribution densities are arranged in the circular subarea and the annular subareas so as to change the temperature distribution of the surface area of the silicon wafer through the holes.

2. The susceptor of claim 1, wherein the plurality of annular subregions comprises: a first annular subregion, a second annular subregion, a third annular subregion, and a fourth annular subregion; wherein,,

the first annular sub-region is located radially inward of and adjacent to the annular region;

the second annular subregion is adjacent to the first annular subregion in a radial direction;

the third annular subregion is adjacent to the second annular subregion in the radial direction;

the fourth annular subregion is located between the circular subregion and the third annular subregion in the radial direction.

3. A susceptor according to claim 2, wherein said third annular sub-region has a diameter ranging from 50mm to 75mm.

4. A susceptor according to claim 3, wherein said third annular sub-region has a hole distribution density of 4.8ea/cm ² 。

5. A susceptor according to claim 2, wherein said second annular sub-region has a diameter ranging from 75mm to 90mm.

6. The susceptor of claim 5, wherein the holes provided in said second annular subregion have a distribution density of 4.0ea/cm ² 。

7. A susceptor according to claim 2, wherein said fourth annular sub-region has a diameter ranging from 40mm to 50mm.

8. The susceptor of claim 7, wherein the fourth annular subregionThe distribution density of the holes arranged on the upper surface is 4.0ea/cm ² 。

9. The susceptor of claim 2, wherein the circular subregion and the first annular subregion are provided with a hole distribution density of 3.0ea/cm ² ～3.5ea/cm ² 。

10. An apparatus for epitaxial growth of a silicon wafer, the apparatus comprising:

a susceptor according to any one of claims 1 to 9 for carrying a silicon wafer;

a susceptor support frame for supporting the susceptor and driving the susceptor to rotate about the central axis X at a certain speed during epitaxial growth;

an upper bell jar and a lower bell jar that together enclose a reaction chamber that houses the base;

a gas inlet for sequentially delivering a cleaning gas and a silicon source gas into the reaction chamber;

the exhaust port is used for exhausting the reaction tail gas of each of the cleaning gas and the silicon source gas out of the reaction chamber;

a plurality of heating bulbs disposed at the periphery of the upper and lower quartz bells and configured to provide a high temperature environment for vapor phase epitaxial deposition in the reaction chamber through the upper and lower bells.