CN116525418B - Silicon epitaxial wafer preparation method based on 111 crystal orientation, silicon epitaxial wafer and semiconductor device - Google Patents

Abstract

The invention provides a method for preparing a silicon epitaxial wafer based on the 111 crystal orientation, a silicon epitaxial wafer and a semiconductor device. The method includes: performing high-rate 111 crystal direction epitaxial growth on the surface of a silicon wafer to obtain a first epitaxial layer; etching the first epitaxial layer; and performing low-rate 111 crystal direction growth on the surface of the etched first epitaxial layer. Epitaxial growth is performed to obtain a second epitaxial layer. The silicon wafer, the etched first epitaxial layer and the second epitaxial layer constitute a silicon epitaxial wafer based on the 111 crystal orientation. The present invention first grows the first epitaxial layer on the surface of the silicon wafer at a high rate, which is more efficient than the conventional growth rate, and then etches the first epitaxial layer to remove the part with fog defects on the surface of the first epitaxial layer. Finally, low-rate growth is performed on the surface of the first epitaxial layer to ensure that the final silicon epitaxial wafer surface is smooth and stable, and has higher production efficiency than the entire slow-rate growth process, and solves the problem of fog on the surface of high-rate growth silicon epitaxial wafers. Defect problem.

Description

Silicon epitaxial wafer preparation method, silicon epitaxial wafer and semiconductor device based on 111 crystal orientation

Technical field

The invention relates to the field of semiconductor technology, and in particular to a method for preparing a silicon epitaxial wafer based on the 111 crystal orientation, a silicon epitaxial wafer and a semiconductor device.

Background technique

Silicon epitaxial wafers based on the 111 crystal orientation are widely used in power devices such as Schottky, transistors, and fast recovery diodes. As customers gradually increase their requirements for process and product quality, large-size silicon epitaxial wafers (diameter 200mm and above) ) puts forward higher uniformity requirements. Therefore, silicon epitaxial wafer manufacturers usually use monolithic silicon epitaxial furnaces for production. Compared with multi-wafer silicon epitaxial furnaces, there is no doubt that monolithic silicon epitaxial wafers have absolute advantages in product uniformity. At the same time, monolithic silicon epitaxial wafers are also The production efficiency of epitaxial furnaces has put forward higher requirements, requiring higher growth rates to be achieved.

For monolithic silicon epitaxial furnaces, when conventional processes are used for 111 crystalline silicon epitaxial growth, if the growth rate is higher than 3.6 μm/min, fog defects will appear on the surface of the silicon epitaxial wafer, causing the product to fail.

Contents of the invention

Embodiments of the present invention provide a method for preparing a silicon epitaxial wafer based on the 111 crystal orientation, a silicon epitaxial wafer and a semiconductor device to solve the problem of fog defects on the surface of high-rate growth silicon epitaxial wafers.

In a first aspect, embodiments of the present invention provide a method for preparing silicon epitaxial wafers based on the 111 crystal orientation, including:

Perform high-rate 111 crystalline epitaxial growth on the surface of the silicon wafer to obtain the first epitaxial layer;

Etching the first epitaxial layer;

A low-rate 111 crystalline epitaxial growth is performed on the surface of the etched first epitaxial layer to obtain a second epitaxial layer. The silicon wafer, the etched first epitaxial layer and the second epitaxial layer are formed based on the 111 crystal. Oriented silicon epitaxial wafer.

In one possible implementation, high-rate 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer, which includes:

Epitaxial growth is performed on the surface of the silicon wafer in the 111 crystal direction with a growth rate of 5.4-6.4 μm/min to obtain the first epitaxial layer.

In a possible implementation, the thickness of the first epitaxial layer is 5-8 μm.

In one possible implementation, high-rate 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer, which includes:

Under the conditions of 990-1090℃, flow TCS gas into the reaction chamber of the monolithic epitaxial furnace where the silicon wafer is located at a gas flow rate of 12-16L/min, and flow it into the reaction cavity at a gas flow rate of 30-270mL/min. Doping gas is added, and high-speed 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer.

In a possible implementation, etching the first epitaxial layer includes:

Under conditions of 990-1090°C, HCl gas is introduced into the reaction chamber of the monolithic epitaxial furnace where the silicon wafer is located at a gas flow rate of 0.5-2L/min to etch the first epitaxial layer.

In a possible implementation, etching the first epitaxial layer includes:

The first epitaxial layer is etched to a thickness of 0.5-2 μm.

In one possible implementation, low-rate 111 crystalline epitaxial growth is performed on the surface of the etched first epitaxial layer to obtain the second epitaxial layer, which includes:

On the surface of the etched first epitaxial layer, epitaxial growth is performed in the 111 crystal direction with a growth rate of 2.8-3.6 μm/min to obtain a silicon epitaxial wafer based on the 111 crystal direction.

In a possible implementation, the thickness of the second epitaxial layer is 1-2 μm.

In a second aspect, embodiments of the present invention provide a silicon epitaxial wafer, which is obtained based on the steps of the above first aspect or any possible implementation method of the first aspect.

In a third aspect, embodiments of the present invention provide a semiconductor device, including the silicon epitaxial wafer of the second aspect.

The embodiments of the present invention provide a silicon epitaxial growth method based on the 111 crystal orientation. The beneficial effects are:

The present invention first grows the first epitaxial layer on the surface of the silicon wafer at a high rate, which is more efficient than the conventional growth rate, and then etches the first epitaxial layer to remove the part with fog defects on the surface of the first epitaxial layer. Finally, low-rate growth is performed on the surface of the first epitaxial layer to ensure that the final silicon epitaxial wafer surface is smooth and stable, and has higher production efficiency than the entire slow-rate growth process, and solves the problem of fog on the surface of high-rate growth silicon epitaxial wafers. Defect problem.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are only illustrative of the present invention. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is an implementation flow chart of a silicon epitaxial wafer preparation method based on the 111 crystal orientation provided by an embodiment of the present invention;

FIG. 2 is an implementation flow chart of a silicon epitaxial wafer preparation method based on the 111 crystal orientation provided by another embodiment of the present invention.

Detailed ways

In the following description, specific details such as specific system structures and technologies are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the present invention in unnecessary detail.

In order to make the purpose, technical solutions and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

Referring to Figure 1, it shows an implementation flow chart of a silicon epitaxial wafer preparation method based on the 111 crystal orientation provided by an embodiment of the present invention. The details are as follows:

Step 101: Perform high-speed 111 crystalline epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer.

In this embodiment, compared with the multi-chip silicon epitaxial furnace, the single-chip silicon epitaxial furnace has an absolute advantage in product uniformity. When using conventional processes for 111 crystalline silicon epitaxial growth, if the growth rate is higher than 3.6 μm/min, fog defects will appear on the surface of the silicon epitaxial wafer. For the silicon epitaxial wafer with fog defects, after etching for 5 minutes by Sirtl method, Swirl defects appear on the surface under a microscopic microscope. It is analyzed that the cause of fog defects is mainly related to the micro-roughness of the surface in the <111> crystal direction. After high-rate growth, micro-voids will appear on the surface of the silicon epitaxial wafer. If a low growth rate process is used, it can effectively suppress the occurrence of fog defects on the surface of silicon epitaxial wafers, but at the same time, it will also lead to a reduction in production efficiency.

Based on the above reasons, in this embodiment, by growing the first epitaxial layer at a high rate, the epitaxial layer can be obtained at a faster speed, thereby meeting the production efficiency requirements for silicon epitaxial wafers.

Step 102: Etch the first epitaxial layer.

In this embodiment, since the first epitaxial layer adopts a high-rate growth process and has fog defects on the surface, etching the first epitaxial layer at this time can make the surface of the first epitaxial layer smooth and solve the problem of fog defect problem.

Step 103: Perform low-rate epitaxial growth in the 111 crystal direction on the surface of the etched first epitaxial layer to obtain a second epitaxial layer. The silicon wafer, the etched first epitaxial layer and the second epitaxial layer are formed based on the 111 crystal direction. of silicon epitaxial wafers.

In this embodiment, the surface of the etched first epitaxial layer is smooth and does not have fog defects, but the surface activity of the etched epitaxial layer is high. At this time, another layer is grown on the surface of the etched first epitaxial layer. The epitaxial layer can cover the highly active part of the surface of the first epitaxial layer to ensure the stability of the final prepared silicon epitaxial wafer. At the same time, since step 101 has improved the production efficiency of the epitaxial wafer, there is sufficient time for epitaxial layer growth in step 103, and the epitaxial growth can be performed at a low rate to ensure that the surface of the epitaxial layer grown this time does not have fog defects.

In the embodiment of the present invention, the first epitaxial layer is first grown on the surface of the silicon wafer at a high rate, which is more efficient than the conventional growth rate, and then the first epitaxial layer is etched to remove fog defects on the surface of the first epitaxial layer. part, and finally perform low-rate growth on the surface of the first epitaxial layer to ensure that the final silicon epitaxial wafer surface is smooth and stable, and has higher production efficiency than the entire slow-rate growth process, solving the problem of high-rate growth of the silicon epitaxial wafer surface. There is a problem with fog defects.

In one possible implementation, high-rate 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer, which includes:

Epitaxial growth is performed on the surface of the silicon wafer in the 111 crystal direction with a growth rate of 5.4-6.4 μm/min to obtain the first epitaxial layer.

In this embodiment, the growth rate of the first epitaxial layer can be 5.4-6.4 μm/min, which can greatly improve the production efficiency compared with the conventional growth rate (not higher than 3.6 μm/min) that does not produce fog defects.

In a possible implementation, the thickness of the first epitaxial layer is 5-8 μm.

In this embodiment, on the silicon epitaxial wafer used for power devices, the thickness of the epitaxial layer is usually 4-10 μm. In the actual production process, the thicker the thickness of the first epitaxial layer, the greater the proportion of high-rate growth time, that is, the higher the production efficiency. The thickness of the first epitaxial layer can be determined according to actual requirements of epitaxial layer thickness and production efficiency.

In one possible implementation, high-rate 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer, which includes:

Under the conditions of 990-1090℃, flow TCS gas into the reaction chamber of the monolithic epitaxial furnace where the silicon wafer is located at a gas flow rate of 12-16L/min, and flow it into the reaction cavity at a gas flow rate of 30-270mL/min. Doping gas is added, and high-speed 111 crystalline epitaxial growth is performed on the surface of the silicon wafer to obtain the first epitaxial layer.

In this embodiment, TCS (trichlorosilicon, SiHCl3) gas is the growth raw material of the epitaxial layer, and the doping gas can be phosphane, borane, etc. The type of doping gas is selected according to actual needs to adjust the electrical properties of the epitaxial layer.

In a possible implementation, etching the first epitaxial layer includes:

Under conditions of 990-1090°C, HCl gas is introduced into the reaction chamber of the monolithic epitaxial furnace where the silicon wafer is located at a gas flow rate of 0.5-2L/min to etch the first epitaxial layer.

In this embodiment, HCl gas is a commonly used gas for etching, and a gas flow rate of 0.5-2L/min can control the etching speed in a lower range to ensure that the etching thickness meets production requirements.

In a possible implementation, etching the first epitaxial layer includes:

The first epitaxial layer is etched to a thickness of 0.5-2 μm.

In this embodiment, the thickness of the fog defect on the surface of the epitaxial layer based on the 111 crystal orientation is usually 0.5-2 μm. Based on this thickness range, selecting the etching thickness to etch the first epitaxial layer can ensure that the first epitaxial layer after etching The surface is smooth and has no fog defects, and the problem of insufficient epitaxial layer thickness is avoided as much as possible.

In one possible implementation, low-rate 111 crystalline epitaxial growth is performed on the surface of the etched first epitaxial layer to obtain the second epitaxial layer, which includes:

On the surface of the etched first epitaxial layer, epitaxial growth is performed in the 111 crystal direction with a growth rate of 2.8-3.6 μm/min to obtain a silicon epitaxial wafer based on the 111 crystal direction.

In this embodiment, when the growth rate is 2.8-3.6 μm/min, there are no fog defects on the surface of the epitaxial layer obtained, and the growth rate is relatively high, which will not affect the production efficiency.

In a possible implementation, the thickness of the second epitaxial layer is 1-2 μm.

In this embodiment, the sum of the thickness of the first epitaxial layer and the thickness of the second epitaxial layer after etching is the thickness of the epitaxial layer on the silicon epitaxial wafer. The second epitaxial layer can not only ensure the stability of the epitaxial layer on the silicon epitaxial wafer, but also It can ensure that the thickness of the epitaxial layer on the silicon epitaxial wafer meets production requirements. The thickness of the second epitaxial layer can be preset according to the actual situation, or can be adjusted according to the thickness of the etched first epitaxial layer after etching to adjust the thickness of the epitaxial layer on the silicon epitaxial wafer.

In a specific embodiment, the specific process for preparing silicon epitaxial wafers based on the 111 crystal orientation based on the steps in the above embodiment is as follows:

During the entire process, a constant flow of carrier gas (hydrogen) is continuously introduced into the cavity, with a flow rate of 40-80L/min, to keep the pressure in the reaction chamber constant, generally 750-755Torr. The name of each step and reaction conditions as shown in picture 2.

The first step: Purge 1, the process temperature is 650-700℃;

Step 2: Heating, the process temperature rises to 1000-1100℃;

Step 3: Bake, maintain the temperature at 1000-1100°C, pass in 0.5-2L/min HCl gas, and air blast the silicon wafer surface;

Step 4: Deposition 1, lower the process temperature to 990-1090°C, pass in 12-16L/min TCS gas and 30-270mL/min doping gas, and perform high-rate growth. The growth rate is 5.4-6.4μm/ min;

Step 5: Purge 2, the process temperature is maintained at 990-1090°C;

Step 6: HCl etching, pass in 0.5-2L/min HCl gas, air blast the surface of the epitaxial wafer to remove surface fog defects;

Step 7: Purge 3, the process temperature is maintained at 990-1090°C;

Step 8: Deposition 2, pass in 4-8L/min TCS gas and 30-270mL/min doping gas to perform low-rate growth, with a growth rate of 2.8-3.6μm/min;

Step 9: Purge 4, the process temperature is maintained at 990-1090°C;

Step 10: Cool down, and the process temperature is reduced to 650-700°C.

Embodiments of the present invention provide a silicon epitaxial wafer, which is obtained based on the steps of the above first aspect or any possible implementation method of the first aspect.

An embodiment of the present invention provides a semiconductor device, including the silicon epitaxial wafer of the second aspect.

It should be understood that the sequence number of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

The above-described embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still implement the above-mentioned implementations. The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present invention, and should be included in within the protection scope of the present invention.

Claims (7)

1. The preparation method of the silicon epitaxial wafer based on the 111 crystal orientation is characterized by comprising the following steps of:

carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer;

etching the first epitaxial layer;

carrying out low-speed 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer to obtain a second epitaxial layer, wherein the silicon wafer, the etched first epitaxial layer and the second epitaxial layer form a silicon epitaxial wafer based on the 111 crystal orientation;

and performing high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer, wherein the step of obtaining the first epitaxial layer comprises the following steps of:

carrying out 111 crystal orientation epitaxial growth with the growth rate of 5.4-6.4 mu m/min on the surface of the silicon wafer to obtain a first epitaxial layer;

and performing high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer, wherein the step of obtaining the first epitaxial layer comprises the following steps of:

introducing trichlorosilane gas into a reaction cavity of a monolithic epitaxial furnace where a silicon wafer is positioned at the temperature of 990-1090 ℃ at the gas flow of 12-16L/min, introducing doping gas into the reaction cavity at the gas flow of 30-270mL/min, and carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer;

and carrying out low-rate 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer, wherein the second epitaxial layer comprises:

and carrying out 111 crystal orientation epitaxial growth with the growth rate of 2.8-3.6 mu m/min on the surface of the etched first epitaxial layer to obtain the silicon epitaxial wafer based on the 111 crystal orientation.

2. The method for preparing a 111 crystal orientation based silicon epitaxial wafer according to claim 1, wherein the thickness of the first epitaxial layer is 5-8 μm.

3. The method for preparing a 111 crystal orientation-based silicon epitaxial wafer according to claim 1, wherein the etching the first epitaxial layer comprises:

and under the condition of 990-1090 ℃, HCl gas is introduced into a reaction cavity of the monolithic epitaxial furnace where the silicon wafer is positioned at the air flow of 0.5-2L/min, and the first epitaxial layer is etched.

4. The method for preparing a 111 crystal orientation-based silicon epitaxial wafer according to claim 1, wherein the etching the first epitaxial layer comprises:

and etching the first epitaxial layer with the thickness of 0.5-2 mu m.

5. The method for preparing a 111 crystal orientation based silicon epitaxial wafer according to claim 1, wherein the thickness of the second epitaxial layer is 1-2 μm.

6. A silicon epitaxial wafer, characterized in that it is obtained on the basis of the steps of the method according to any one of claims 1 to 5.

7. A semiconductor device comprising the silicon epitaxial wafer according to claim 6.