CN116525415B - Preparation method of silicon epitaxial wafer and silicon epitaxial wafer - Google Patents

Abstract

The invention provides a preparation method of a silicon epitaxial wafer and the silicon epitaxial wafer. The preparation method of the silicon epitaxial wafer comprises the following steps: arranging a silicon substrate in a cavity, continuously introducing carrier gas with constant flow into the cavity, and keeping the pressure of the cavity constant; performing epitaxial growth on the silicon substrate at least twice in the cavity to prepare a silicon epitaxial wafer with a flattened silicon epitaxial layer; and (5) carrying out primary purging and cooling on the silicon epitaxial wafer. According to the invention, chemical mechanical polishing is not needed, and the flattened silicon epitaxial wafer can be obtained only by carrying out deposition at least twice when the epitaxial layer is prepared, so that the steps are simple, the operation is cheap, and the manufacturing difficulty and cost of the silicon epitaxial wafer are effectively reduced.

Description

Preparation method of silicon epitaxial wafer and silicon epitaxial wafer

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a silicon epitaxial wafer and a silicon epitaxial wafer.

Background technique

As a substrate material for semiconductor devices, silicon epitaxial wafers form an epitaxial layer on the surface of a silicon substrate and are used to manufacture high-quality, high-reliability semiconductor devices.

In the prior art, when the surface of the silicon substrate is uneven, chemical mechanical polishing is usually required to obtain a fully planarized silicon wafer surface. However, the chemical mechanical polishing process is complicated, requiring chemical corrosion and mechanical friction to be alternately performed multiple times, and a wide variety of polishing materials are used, which is costly.

Contents of the invention

Embodiments of the present invention provide a method for preparing silicon epitaxial wafers and silicon epitaxial wafers to solve the problems of complex surface smoothing process and high cost of silicon substrates during the production of silicon epitaxial wafers.

In a first aspect, embodiments of the present invention provide a method for preparing a silicon epitaxial wafer, including:

Arrange the silicon substrate in the cavity, continuously pass a constant flow of carrier gas into the cavity, and keep the cavity pressure constant;

Perform epitaxial growth on the silicon substrate at least twice in the cavity to prepare a silicon epitaxial wafer with a planarized silicon epitaxial layer;

Perform a purge and cooling of the silicon epitaxial wafer.

Optionally, before the silicon substrate is placed in the cavity, a constant flow of carrier gas is continuously introduced into the cavity, and the cavity pressure is constant, the above method further includes:

Perform electrochemical etching on the silicon polished wafer to prepare a nanoporous silicon layer on the surface of the silicon polished wafer;

The silicon polished sheet prepared with the nanoporous silicon layer is exposed to the air, and a uniform strong gettering center is formed on the polished sheet to obtain a silicon substrate.

Optionally, perform electrochemical etching on the silicon polished wafer to prepare a nanoporous silicon layer on the surface of the silicon polished wafer, including:

The positive electrode is connected to the positive pole of the DC power supply through a wire, and the negative electrode is connected to the negative pole of the DC power supply through a wire;

The positive electrode, negative electrode and polished silicon wafer are immersed in the electrolyte, and a DC power supply is connected for electrochemical etching to form a nanoporous silicon layer on the surface of the polished silicon wafer.

Optional, the electrolyte is 50% hydrofluoric acid solution;

The voltage of the DC power supply is 24V~36V;

The current density during electrochemical corrosion is 10mA/cm ² ~ 100mA/cm ² ;

The power-on time of the DC power supply is 5min~20min.

Optionally, the surface depth of the nanoporous silicon layer is 1um to 5um, and the size of the pores in the nanoporous silicon layer is 10nm to 30nm.

Optionally, after electrochemically etching the silicon polished wafer to prepare a nanoporous silicon layer on the surface of the silicon polished wafer, the above method also includes:

Clean the silicon polished wafer prepared with the nanoporous silicon layer in a megasonic cleaning machine;

Put the cleaned silicon wafer into a spin dryer and spin it dry.

Optionally, perform at least two epitaxial growths on the silicon substrate, including:

Secondary purge: temperature 650℃～700℃;

Heating: increase the temperature to 1000℃~1100℃;

Baking: The temperature is maintained at 1000°C to 1100°C, and HCl gas is introduced to air blast the silicon substrate;

Three purges: temperature 990℃～1090℃;

Deposition; temperature is 990℃~1090℃, TCS gas and doping gas are introduced to perform silicon epitaxial growth;

Repeat the three purge to deposition steps at least twice.

Optional, the number of depositions is two;

The velocity of the first deposition is greater than the velocity of the second deposition.

Optionally, during the first deposition, the TCS gas is introduced at a rate of 2 standard liters/min to 3 standard liters/min, and the doping gas is introduced at a rate of 30 standard ml/min to 100 standard ml/min;

During the second deposition, the TCS gas flow rate is 6 standard liters/min to 10 standard liters/min, and the doping gas flow rate is 50 standard ml/min to 200 standard ml/min.

In a second aspect, an embodiment of the present invention provides a silicon epitaxial wafer, which is prepared by using the method for preparing a silicon epitaxial wafer provided in the first aspect of the embodiment of the present invention.

Embodiments of the present invention provide a method for preparing a silicon epitaxial wafer and a silicon epitaxial wafer. The preparation method of the above-mentioned silicon epitaxial wafer includes: arranging the silicon substrate in a cavity, continuously passing a constant flow of carrier gas into the cavity, and the cavity pressure is constant; performing epitaxial growth on the silicon substrate at least twice in the cavity, and preparing a silicon epitaxial wafer having a constant flow rate. The silicon epitaxial wafer with the planarized silicon epitaxial layer; the silicon epitaxial wafer is purged and cooled once. In the embodiments of the present invention, there is no need to perform chemical mechanical polishing, and only two or more depositions are required when preparing the epitaxial layer to obtain a planarized silicon epitaxial wafer. The steps are simple, the operation is cheap, and the manufacturing cost of the silicon epitaxial wafer is effectively reduced. Difficulty and cost.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are only illustrative of the present invention. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic flow diagram of a method for preparing a silicon epitaxial wafer provided by an embodiment of the present invention;

Figure 2 is a schematic diagram of the effect of two depositions provided by an embodiment of the present invention;

Figure 3 is a schematic diagram of a preparation device for a nanoporous silicon layer provided by an embodiment of the present invention;

FIG. 4 is a schematic flowchart of epitaxial growth provided by an embodiment of the present invention.

Detailed ways

In order to enable those in the technical field to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are part of this solution embodiments, not all embodiments. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of this solution.

The term "including" and any other variations in the description and claims of this solution and the above-mentioned drawings mean "including but not limited to", which is intended to cover non-exclusive inclusion and is not limited to the examples listed in the text. In addition, terms such as "first" and "second" are used to distinguish between different objects and are not used to describe a specific order.

The implementation of the present invention is described in detail below with reference to specific drawings:

FIG. 1 is a schematic flow chart of a method for preparing a silicon epitaxial wafer according to an embodiment of the present invention.

Referring to Figure 1, an embodiment of the present invention provides a method for preparing an epitaxial wafer, which includes:

S101: Arrange the silicon substrate in the cavity, continuously pass a constant flow of carrier gas into the cavity, and keep the cavity pressure constant;

S102: Perform at least two epitaxial growths on the silicon substrate in the cavity to prepare a silicon epitaxial wafer with a planarized silicon epitaxial layer;

S103: Perform a purge and cooling of the silicon epitaxial wafer.

For uneven silicon substrates, there is no need to perform chemical mechanical polishing in embodiments of the present invention. Instead, epitaxial growth is performed at least twice during the growth of the silicon epitaxial layer. Referring to Figure 2, during the first epitaxial growth, the surface of the silicon wafer is gradually flattened. ; The second epitaxial growth further improves the surface flatness. If the surface is still uneven, the third epitaxial growth and the fourth epitaxial growth can be performed to obtain a silicon epitaxial wafer with a flattened surface; finally, the surface is purged and cooled to obtain a qualified of silicon epitaxial wafers. The above-mentioned preparation method of silicon epitaxial wafers only needs to be repeated at least twice during the epitaxial growth process, eliminating the complicated chemical mechanical polishing steps, effectively reducing the complexity of preparation, and at the same time, because the chemical mechanical polishing steps are abandoned, Several polishing materials are eliminated and the preparation cost is greatly reduced.

It should be noted that the number of epitaxial growth can be set according to the surface flatness of the silicon substrate, and there is no specific limit.

In a possible implementation, before S101, the above method may also include:

S104: Perform electrochemical etching on the silicon polished wafer to prepare a nanoporous silicon layer on the surface of the silicon polished wafer;

S105: Expose the silicon polished wafer prepared with the nanoporous silicon layer to the air, and form a uniform strong gettering center on the polished wafer to obtain a silicon substrate.

In order to improve the quality of silicon substrates, a gettering center is introduced, and the metal impurities introduced during silicon epitaxial growth and other device processes are "pinned" in the gettering center to reduce the impact of metal impurities on device performance. In the existing technology, after the silicon polished wafer is produced, an annealing process is used to obtain the gettering centers. The density and size of the gettering centers are difficult to control.

Using electrolyte (for example, hydrofluoric acid electrolyte) to electrochemically etch the silicon wafer, when the positive current density is small, a layer of silicon pillars with countless nanometer-sized silicon pillars that is different from the bright polished surface can be obtained. A silicon film with a porous structure and evenly distributed pores. Due to the existence of porous structure, nanoporous silicon has large local stress and high solid solubility, which is conducive to the diffusion of metal impurities into the porous structure and is a good gettering center. Therefore, in the embodiment of the present invention, a nanoporous silicon layer is prepared on the surface of the silicon polishing wafer to obtain a gettering center. Furthermore, the P-type silicon polishing wafer prepared with the nanoporous silicon layer is exposed to the air. The porous structure has a large specific surface area, and the surface The activation energy is high, and when exposed to air, a dense thin oxide layer will be formed on the surface of the nanoporous silicon layer, making the pores become strong gettering centers, thereby obtaining a silicon substrate with excellent performance with strong gettering centers. This method has simple steps, does not require annealing and other operations, and has low cost, which greatly reduces the difficulty and cost of manufacturing the gettering center.

In a possible implementation, S104 may include:

S1041: The positive electrode is connected to the positive pole of the DC power supply through a wire, and the negative electrode is connected to the negative pole of the DC power supply through a wire;

S1042: Immerse the positive electrode, negative electrode and silicon polished wafer into the electrolyte, and connect the DC power supply for electrochemical corrosion to form a nanoporous silicon layer on the surface of the silicon polished wafer.

Figure 3 shows a diagram of the preparation device of the nanoporous silicon layer. By adjusting the concentration, current density and energization time of the electrolyte, the surface depth, pore size and pore density of the nanoporous silicon layer can be precisely controlled, so that the size and density of the gettering center can be precisely controlled.

In a possible implementation, the electrolyte can be a 50% hydrofluoric acid solution;

The voltage of the DC power supply can be 24V~36V;

The current density during electrochemical corrosion can be 10mA/cm ² ~ 100mA/cm ² ;

The power-on time of the DC power supply can be 5min~20min.

Based on the above process, in a possible implementation, the surface depth of the nanoporous silicon layer is 1um-5um, and the size of the pores in the nanoporous silicon layer is 10nm-30nm.

Specifically, the depth and pore size of the nanoporous silicon layer can be adjusted by adjusting the concentration of the electrolyte, the voltage of the DC power supply, the current density, and the duration of the power supply, thereby obtaining nanoporous silicon layers of different specifications.

In a possible implementation, after S104, the above method may further include:

S106: Clean the silicon polished wafer prepared with the nanoporous silicon layer in a megasonic cleaning machine;

S107: Put the cleaned silicon wafer into a dryer and dry it.

In order to ensure the quality of the silicon wafer, the nano-porous silicon layer can be rinsed and dried after the preparation is completed to remove the nano-silicon particles in the pores of the nano-porous silicon layer without leaving any moisture. The parameters of the megasonic cleaning machine and dryer can be set according to actual application requirements.

For example, the cleaning time can be set according to the thickness of the nanoporous silicon layer. The thicker the nanoporous silicon layer, the deeper the pores may be, and the nano silicon particles can be hidden deeper, requiring longer cleaning time to remove deep impurities. Other parameters will not be described here.

It should be noted that during the rinsing and drying process, the silicon polished wafer can be placed in a test flower basket made of polytetrafluoroethylene, and then placed in a megasonic cleaning machine and dryer to avoid damaging the silicon wafer.

In a possible implementation, referring to Figure 4, S102 may include:

1. Secondary purge: temperature 650℃~700℃;

2. Heating: increase the temperature to 1000℃~1100℃;

3. Baking: The temperature is maintained at 1000°C to 1100°C, and HCl gas is introduced to air blast the silicon substrate;

4. Three purges: temperature 990℃～1090℃;

5. Deposition; the temperature is 990°C ~ 1090°C, and TCS gas and doping gas are introduced to perform silicon epitaxial growth;

6. Repeat the three purge to deposition steps at least twice.

The first purge, second purge and third purge that need to be explained are only used to distinguish different steps and do not limit the order of execution.

Refer to Figure 4 for the specific process. The settings of each parameter in the above process can be set according to actual application requirements. There are no restrictions here and are only used to obtain a planarized silicon substrate with good performance.

In a possible implementation, the number of depositions may be two times;

The velocity of the first deposition is greater than the velocity of the second deposition.

Referring to Figure 2, the deposition speed of the first deposition can be slightly slower, which is beneficial to conformal deposition, flattening the uneven areas on the silicon wafer surface, and improving surface flatness. During the second deposition, the surface of the silicon wafer has become flat. In order to further flatten it, the deposition speed can be increased and the efficiency improved.

Furthermore, in order to improve the flatness of the silicon wafer surface, the third and fourth depositions can also be performed. The number of depositions can be adjusted according to actual application requirements or the flatness of the silicon wafer surface.

In a possible implementation, during the first deposition, the rate at which the TCS gas is introduced can be 2 to 3 standard liters/min, and the rate at which the doping gas is introduced can be between 30 and 30 standard milliliters/min. 100 standard ml/min;

During the second deposition, the TCS gas flow rate can be 6 standard liters/min to 10 standard liters/min, and the doping gas flow rate can be 50 standard ml/min to 200 standard ml/min.

Specific parameters can be set according to actual application requirements.

The above method will be described in detail below with reference to specific embodiments.

1. Preparation of nanoporous silicon layer

Referring to Figure 3, the electrolytic cell is a container made of polytetrafluoroethylene, the electrolyte is a hydrofluoric acid solution with a solubility of 50%, and the voltage of the DC power supply is 36V. The positive electrode of the DC power supply passes through the wire, and a clip made of PTFE connects the copper wire contact to the first graphite electrode; the negative electrode of the DC power supply passes through the wire, and a clip made of PTFE connects the wire contact copper The sheet is connected to a second graphite electrode. Place the silicon polished wafer on a support table made of polytetrafluoroethylene and immerse it in the electrolyte. Turn on the DC power supply with a current density of 50mA/cm ² and energize it for 15 minutes. A nanoporous silicon layer with a surface depth of 3um and pores will be obtained on the surface of the silicon polished wafer. The size is 20nm and evenly distributed.

2. Rinse

Put the polished silicon wafer with the nanoporous silicon layer into a test flower basket made of polytetrafluoroethylene, and put the flower basket and the silicon wafer into a megasonic cleaning machine with a deionized water circulation system for cleaning. The deionized water circulation flow is 5L/min, the megasonic generator frequency is 850kHz, the water temperature is 25°C, and the cleaning time is 30min.

3. Spin dry

Take out the test flower basket and silicon wafer and put them into a dryer to dry them. The rotation speed of the dryer is 360r/min, and the drying time is 8 minutes.

4. Epitaxial growth

Referring to Figure 4, a constant flow rate of carrier gas (H2) is continuously introduced into the cavity, the flow rate is 50 standard liters/min, and the cavity pressure is constant at 752Torr. (1) Purge at 670°C; (2) Raise the temperature to 1070°C; (3) Pour in HCl gas at 0.8 standard liters/min and bake at 1070°C; (4) Purge at 1060°C; (5) Pour in 2 standard L/min TCS gas and 40 standard ml/min doping gas, epitaxial growth at 1060°C, growth rate 1μm/min, lasting 60s; (6) 1060°C purge; (7) 8 standard liters/min TCS gas and 150 standard ml/min doping gas, epitaxial growth at 1060°C, with a growth rate of 3.5μm/min, lasting 120s; (8) purging at 1060°C; (9) cooling to 670°C to obtain silicon epitaxial wafers .

Embodiments of the present invention also provide a silicon epitaxial wafer, which is prepared by using the silicon epitaxial wafer preparation method provided in the above embodiments. The steps are simple, the finished product is of good quality, and the cost is low.

The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions of the foregoing embodiments. The recorded technical solutions may be modified, or some of the technical features thereof may be equivalently replaced; however, these modifications or substitutions shall not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims (6)

1. The preparation method of the silicon epitaxial wafer is characterized by comprising the following steps of:

carrying out electrochemical corrosion on a silicon polishing sheet, and preparing a nano porous silicon layer on the surface of the silicon polishing sheet;

exposing the silicon polishing sheet with the nano porous silicon layer to air, and forming uniform strong gettering center on the silicon polishing sheet to obtain a silicon substrate;

arranging the silicon substrate in a cavity, continuously introducing carrier gas with constant flow rate into the cavity, and keeping the pressure of the cavity constant;

performing at least two epitaxial growth on the silicon substrate in the cavity to prepare a silicon epitaxial wafer with a flattened silicon epitaxial layer;

carrying out primary purging and cooling on the silicon epitaxial wafer;

the performing at least two epitaxial growth on the silicon substrate comprises:

and (3) secondary purging: the temperature is 650-700 ℃;

heating: raising the temperature to 1000-1100 ℃;

baking: maintaining the temperature at 1000-1100 ℃, and introducing HCl gas to perform gas polishing on the silicon substrate;

three times of purging: the temperature is 990-1090 ℃;

depositing; introducing TCS gas and doping gas at 990-1090 ℃ to perform silicon epitaxial growth;

repeating the step of purging to the deposition three times at least twice;

the number of times of deposition is two;

during the first deposition, the speed of introducing TCS gas is 2-3 standard liters/min, and the speed of introducing doping gas is 30-100 standard milliliters/min;

in the second deposition, the speed of introducing TCS gas is 6-10 standard liters/min, and the speed of introducing doping gas is 50-200 standard milliliters/min.

2. The method for preparing a silicon epitaxial wafer according to claim 1, wherein the step of performing electrochemical etching on the silicon polished wafer to prepare a nanoporous silicon layer on the surface of the silicon polished wafer comprises the steps of:

the positive electrode is connected with the positive electrode of the direct current power supply through a wire, and the negative electrode is connected with the negative electrode of the direct current power supply through a wire;

immersing the positive electrode, the negative electrode and the silicon polished wafer into electrolyte, and switching on the direct current power supply to carry out electrochemical corrosion, so as to form the nano porous silicon layer on the surface of the silicon polished wafer.

3. The method for producing a silicon epitaxial wafer according to claim 2, wherein,

the electrolyte is 50% hydrofluoric acid solution;

the voltage of the direct current power supply is 24V-36V;

the current density at the time of electrochemical corrosion was 10mA/cm ² ~100mA/cm ² ；

The energizing time of the direct current power supply is 5 min-20 min.

4. The method for preparing a silicon epitaxial wafer according to claim 3, wherein the surface depth of the nano-porous silicon layer is 1um to 5um, and the size of the pores in the nano-porous silicon layer is 10nm to 30nm.

5. The method for preparing a silicon epitaxial wafer according to claim 1, wherein after the electrochemical etching of the silicon polished wafer and the preparation of the nanoporous silicon layer on the surface of the silicon polished wafer, the method further comprises:

placing the silicon polishing sheet with the nano porous silicon layer in a megasonic cleaner for cleaning;

and putting the cleaned silicon wafer into a spin dryer for spin-drying.

6. A silicon epitaxial wafer, characterized in that it is prepared by the method for preparing a silicon epitaxial wafer according to any one of claims 1 to 5.