CN116524981A - Test system and test method - Google Patents

Abstract

The invention provides a test system, which comprises a plurality of memory circuits and a test circuit. The test circuit is coupled to the memory circuits. The test circuit is used for executing a read-write operation on the memory circuits, and each memory circuit has a read-write starting time point corresponding to the read-write operation. The test circuit is also used for controlling the read-write starting time points of the memory circuits to be different from each other.

Description

Test system and test method

technical field

The invention relates to a testing technology, in particular to a testing system and a testing method for testing memory circuits.

Background technique

With the development of technology, the number of memories in electronic devices is increasing. However, due to process or other factors, memory may have defects. In some related technologies, a test circuit can be used to test the memory to confirm whether there is a defect in the memory.

Contents of the invention

Some embodiments of the invention relate to a testing system. The test system includes multiple memory circuits and a test circuit. A test circuit is coupled to the memory circuits. The test circuit is used to perform a read and write operation on the memory circuits, and each of the memory circuits has a read and write start time point corresponding to the read and write operation. The test circuit is also used to control the read and write start time points of the memory circuits to be different from each other.

Some embodiments of the invention relate to a testing method. The testing method includes the following operations: performing a read and write operation on a plurality of memory circuits by a test circuit, wherein each of the memory circuits has a read and write start time point corresponding to the read and write operation; and controlling the memory circuits by the test circuit These reading and writing start time points are different from each other.

To sum up, in the present invention, a single test circuit is used to test multiple memory circuits, and the test circuit can stagger the read and write start time points of these memory circuits. Accordingly, the present invention can avoid excessive instantaneous voltage drop without (or a small amount of) increasing the circuit area occupied by the test circuit and without increasing the test time, so as to ensure the normal operation of the circuit.

Description of drawings

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

Fig. 1 is a schematic diagram of a test system shown according to some embodiments of the present invention;

FIG. 2 is a timing diagram of the test system in FIG. 1 shown according to some embodiments of the present invention;

FIG. 3 is a schematic diagram of an offset circuit according to some embodiments of the present invention; and

Fig. 4 is a flowchart of a testing method according to some embodiments of the present invention.

Explanation of reference signs:

100: Test system 120: Test circuit 121: Enable signal generating circuit

122: Address generation circuit 123, 124: Offset circuit 300: Offset circuit

310: Multiplexer 320: Register 400: Test Method

M1, M2, M3: memory circuits

ST1, ST2, ST3: read and write start time point ET1, ET2, ET3: read and write end time point

CLK: clock signal EN1, EN2, EN3: enable signal

AD: address signal DS1, DS2: offset signal

OFFSET1, OFFSET2, OFFSET3, OFFSET4: Candidate offset values

OF1, OF2: offset value SS: selection signal S410, S420: operation

Detailed ways

As used herein, the term "coupled" may also refer to "electrically coupled", and the term "connected" may also refer to "electrically connected". "Coupled" and "connected" may also mean that two or more elements cooperate or interact with each other.

Refer to Figure 1. FIG. 1 is a schematic diagram of a testing system 100 according to some embodiments of the present invention.

Taking FIG. 1 as an example, the test system 100 includes memory circuits M1 - M3 and a test circuit 120 . The test circuit 120 is coupled to the memory circuits M1-M3. In some embodiments, the testing circuit 120 is implemented by using a memory built-in self-test (MBIST) circuit, and is integrated with the memory circuits M1-M3 on one chip.

In some embodiments, the storage capacities of the memory circuits M1-M3 are different from each other. In some other embodiments, the storage capacities of the memory circuits M1-M3 are not different from each other.

For easy understanding, it will be described below as an example that the storage capacities of the memory circuits M1 - M3 are different from each other, but the present invention is not limited thereto. Taking FIG. 1 as an example, the memory circuit M1 has Q entries, the memory circuit M2 has P entries, and the memory circuit M2 has N entries, wherein Q, P, and N are positive integers, and Q is greater than P and P is greater than N. In other words, the storage capacity of the memory circuit M1 is greater than the storage capacity of the memory circuit M2, and the storage capacity of the memory circuit M2 is greater than the storage capacity of the memory circuit M3.

It is particularly noted here that the number of memory circuits in FIG. 1 is only an example, and various applicable numbers are within the scope of the present invention.

The test circuit 120 can be understood as a memory access controller for performing a read and write operation on the memory circuits M1-M3 to test the memory circuits M1-M3. For the same read and write operation, all entries in the memory circuits M1-M3 will be read or written. That is to say, for the same read and write operation, the total working time interval of the memory circuit M1 (largest storage capacity) with the most entries will be the longest, and the total working time interval of the memory circuit M3 (smallest storage capacity) with the fewest entries will be the shortest.

Refer to FIG. 1 and FIG. 2 together. FIG. 2 is a timing diagram of the test system 100 shown in FIG. 1 according to some embodiments of the present invention. The test circuit 120 can control the read/write start time points ST1-ST3 of the memory circuits M1-M3 to be different from each other based on the clock signal CLK. Taking FIG. 2 as an example, for the same read and write operation, the test circuit 120 can control the memory circuit M1 to perform the read and write operation at the read and write start time point ST1 based on the clock signal CLK, and control the memory circuit M2 to perform the read and write operation based on the clock signal CLK. The read/write operation is performed at the start time point ST2, and the memory circuit M3 is controlled to perform the read/write operation at the read/write start time point ST3 based on the clock signal CLK.

Taking FIG. 1 as an example, the testing circuit 120 may include an enable signal generating circuit 121 , an address generating circuit 122 , an offset circuit 123 and an offset circuit 124 .

The enable signal generating circuit 121 is used for generating and outputting enable signals EN1-EN3. The enable signals EN1-EN3 are mainly used to enable or disable the memory circuits M1-M3. The address generating circuit 122 is used for generating and outputting address signals AD. The address signal AD is mainly used to decide which entry in the memory circuits M1-M3 is to be read or written.

In FIG. 1 , the enable signal generating circuit 121 and the address generating circuit 122 are coupled to the memory circuit M1 . The memory circuit M1 can receive the enable signal EN1 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122 . Accordingly, if the enable signal EN1 has an enable level at the read/write start time point ST1 , the memory circuit M1 can perform read/write operations at the read/write start time point ST1 according to the enable signal EN1 and the address signal AD.

On the other hand, the enable signal generating circuit 121 and the address generating circuit 122 are coupled to the offset circuit 123, and the offset circuit 123 is coupled to the memory circuit M2. The offset circuit 123 can receive the enable signal EN2 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122 . Next, the offset circuit 123 can generate the offset signal DS1 according to the enable signal EN2 and the address signal AD. The memory circuit M2 can be read and written according to the offset signal DS1 at the read and write start time point ST2.

In some embodiments, the offset circuit 123 may include a comparator. The comparator can compare the address value carried by the address signal AD with the first offset value (for example: 256). The address value carried by the address signal AD can count down from an initial address value (for example: 0). When the current address value carried by the address signal AD (for example: 256) is equal to the first offset value (for example: time point ST2), the enable signal EN2 has an enable level. At this time, the offset circuit 123 can generate the offset signal DS1 to enable the memory circuit M2 at the read/write start time point ST2 and according to the difference between the current address value and the first offset value (for example: 256-256=0) It is decided which entry (for example: entry 0) in the memory circuit M2 is to be read or written.

Similarly, the enable signal generating circuit 121 and the address generating circuit 122 are coupled to the offset circuit 124, and the offset circuit 124 is coupled to the memory circuit M3. The offset circuit 124 can receive the enable signal EN3 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122 . Next, the offset circuit 124 can generate the offset signal DS2 according to the enable signal EN3 and the address signal AD. The memory circuit M3 can be read and written according to the offset signal DS2 at the read and write start time point ST3.

Similarly, in some embodiments, the offset circuit 124 may include a comparator. The comparator can compare the address value carried by the address signal AD with the second offset value (for example: 128). As mentioned above, the address value carried by the address signal AD can count down from the initial address value (for example: 0). When the current address value carried by the address signal AD (for example: 128) is equal to the second offset value (for example: time point ST3), the enable signal EN3 has an enable level. At this time, the offset circuit 124 can generate the offset signal DS2 to enable the memory circuit M3 at the read/write start time point ST3 and according to the difference between the current address value and the second offset value (for example: 128-128=0) It is decided which entry (for example: entry 0) in the memory circuit M3 is to be read or written.

Taking FIG. 2 as an example, the read-write start time point ST1 is earlier than the read-write start time point ST3, and the read-write start time point ST3 is earlier than the read-write start time point ST2. That is, the reading and writing start time point ST1 of the memory circuit M1 having the largest storage capacity is the earliest. There is a first delay time interval (marked with dots) between the read-write start time point ST3 and the read-write start time point ST1, and there is a first delay time interval between the read-write start time point ST2 and the read-write start time point ST1. Two delay time intervals (also marked with dots), and the second delay time interval is longer than the first delay time interval. It is particularly noted here that although the read-write start time point ST3 is earlier than the read-write start time point ST2 in FIG. 2 , the present invention is not limited thereto. In some other embodiments, the read-write start time point ST3 may also be later than the read-write start time point ST2.

The time interval (working time interval) between the read-write start time point of a memory circuit and the read-write end time point is directly related to the storage capacity of the memory circuit. Taking FIG. 2 as an example, since the storage capacity of the memory circuit M1 is the largest, the time interval covered between the read/write start time point ST1 and the read/write end time point ET1 of the memory circuit M1 is the longest. Since the storage capacity of the memory circuit M3 is the smallest, the time interval covered between the read-write start time point ST3 and the read-write end time point ET3 of the memory circuit M3 is the shortest.

In some embodiments, the test circuit 120 can control the read/write end time point ET2 of the memory circuit M2 and the read/write end time point ET3 of the memory circuit M3 to be no later (same as or earlier) than the memory circuit M1 with the largest storage capacity read and write end time point ET1. Accordingly, additional testing time can be avoided. In the example of FIG. 2 , the test circuit 120 controls the read/write end time ET1 of the memory circuit M1 , the read/write end time ET2 of the memory circuit M2 , and the read/write end time ET3 of the memory circuit M3 to be different from each other.

In some embodiments, the disabling time point of a memory circuit is the end time point of reading and writing of the memory circuit. Taking FIG. 1 and FIG. 2 as an example, the enable signal EN1 may have a disable level at the end time point ET1 of reading and writing to disable the memory circuit M1. The enable signal EN2 can have a disable level at the read/write end time point ET2 so that the corresponding generated offset signal DS1 can be used to disable the memory circuit M2. The enable signal EN3 can have a disable level at the read/write end time point ET3 so that the corresponding generated offset signal DS2 can be used to disable the memory circuit M3. Accordingly, the power saving effect can be achieved.

In some other embodiments, the disabling time point of all memory circuits M1-M3 is the end time point of reading and writing of the memory circuit M1 with the largest storage capacity. That is to say, the enable signals EN1-EN3 all have the disable level at the end time point ET1 of reading and writing to disable the memory circuits M1-M3. The period between the reading and writing end time point ET2 of the memory circuit M2 and the reading and writing end time point ET1 of the memory circuit M1 is the idle period of the memory circuit M2, and the reading and writing end time point ET3 of the memory circuit M3 is different from the reading and writing end time point ET1 of the memory circuit M1. The period between the end time points ET1 is an idle period of the memory circuit M3.

In some related technologies, in order to save the circuit area occupied by the memory test circuit, a single test circuit is used to test multiple memory circuits. In this case, when the test starts (transition from idle state to test state), a very large current will be generated. This extremely large current will cause insufficient power supply, causing the instantaneous voltage drop to be too large and causing the circuit to fail.

In some related technologies, in order to avoid excessive instantaneous voltage drop, multiple test circuits are used to test multiple memory circuits respectively. However, this will increase the circuit area occupied by the test circuit and thus increase the size of the entire chip. In other related technologies, in order to avoid excessive instantaneous voltage drop, these memory circuits are divided into multiple groups for time-sharing testing. However, this increases test time.

Compared with the above-mentioned related technologies, in the present invention, a single test circuit 120 is used to test multiple memory circuits M1-M3, and the test circuit 120 can stagger the read and write start time points ST1-ST3 of the memory circuits M1-M3 . Accordingly, the present invention can avoid the excessive instantaneous voltage drop caused by the extremely high current without increasing the circuit area occupied by the test circuit and without increasing the test time, thereby ensuring the normal operation of the circuit. The less overlapping the working time intervals of the memory circuits M1-M3 are, the better the effect of avoiding extremely large currents is.

Refer to Figure 3. FIG. 3 is a schematic diagram of an offset value generation circuit 300 according to some embodiments of the present invention. In some embodiments, the delay circuit 123 or 124 of FIG. 1 may also include an offset value generation circuit 300, and the offset value generation circuit 300 may be used to generate the aforementioned first offset value (marked by OF1 in FIG. 3 ). or the second offset value (marked by OF2 in FIG. 3 ).

Taking FIG. 3 as an example, the offset circuit 300 includes a multiplexer 310 and a register 320 . Multiplexer 310 includes multiple input terminals. One input terminal of the multiplexer 310 is coupled to the register 320 , and the other input terminals of the multiplexer 310 are respectively used to receive the candidate offset value OFFSET1 , the candidate offset value OFFSET2 and the candidate offset value OFFSET3 . The register 320 can generate the candidate offset value OFFSET4 based on system requirements or application scenarios and according to a user operation or a command from a control circuit.

The multiplexer 310 can output one of the candidate offset value OFFSET1, the candidate offset value OFFSET2, the candidate offset value OFFSET3 and the candidate offset value OFFSET4 according to the selection signal SS to generate the aforementioned first offset value OF1 or the first offset value OF1. Two offset values OF2. The selection signal SS can be generated based on system requirements or application scenarios and according to a user operation or a command from a control circuit. Then, as mentioned above, the delay circuit 123 or 124 can further generate the offset signal DS1 or DS2 according to the first offset value OF1 or the second offset value OF2.

Since the candidate offset value OFFSET4 or the selection signal SS can be adjusted based on system requirements or application scenarios, this structure has greater application flexibility and is applicable to more usage environments.

It is particularly noted here that the number of candidate offset values or registers in FIG. 3 is only an example, and various applicable numbers are within the scope of the present invention.

Refer to Figure 4. Fig. 4 is a flowchart of a testing method 400 according to some embodiments of the present invention. Taking FIG. 4 as an example, the testing method 400 includes operation S410 and operation S420.

In some embodiments, the testing method 400 can be applied to the testing system 100 in FIG. 1 , but the invention is not limited thereto. However, for ease of understanding, the testing method 400 will be described in conjunction with the testing system 100 in FIG. 1 .

In operation S410 , a read and write operation is performed on the memory circuits M1 - M3 by the test circuit 120 . Each of the memory circuits M1-M3 has a read/write start time point corresponding to the read/write operation. Taking FIG. 2 as an example, the memory circuit M1 corresponds to the read/write start time point ST1 , the memory circuit M2 corresponds to the read/write start time point ST2 , and the memory circuit M3 corresponds to the read/write start time point ST3 .

In operation S420, the test circuit 120 controls the reading and writing start time points ST1-ST3 of the memory circuits M1-M3 to be different from each other. In some embodiments, the read/write start time point ST1 of the memory circuit M1 with the largest storage capacity is the earliest, while the read/write start time points ST2-ST3 of the other memory circuits M2-M3 are later than the read/write start time points Time point ST1.

To sum up, in the present invention, a single test circuit is used to test multiple memory circuits, and the test circuit can stagger the read and write start time points of these memory circuits. Accordingly, the present invention can avoid excessive instantaneous voltage drop without (or a small amount of) increasing the circuit area occupied by the test circuit and without increasing the test time, so as to ensure the normal operation of the circuit.

Although the embodiments of the present invention are disclosed above, these are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention should be defined according to the claims of the present invention.

Claims (10)

1. A test system comprising: a plurality of memory circuits; and A test circuit, coupled to the plurality of memory circuits, wherein the test circuit is used to perform a read and write operation on the plurality of memory circuits, and each of the plurality of memory circuits has a corresponding to the read and write operation A reading and writing start time point, Wherein the test circuit is further used to control the multiple read/write start time points of the multiple memory circuits to be different from each other. 2. The test system according to claim 1, wherein the plurality of memory circuits comprise a first memory circuit and a second memory circuit, wherein a storage capacity of the first memory circuit is greater than that of the first memory circuit A storage capacity of two memory circuits, and the read/write start time point of the first memory circuit is earlier than the read/write start time point of the second memory circuit. 3. The test system according to claim 2, wherein a read-write end time point corresponding to the read-write operation of the second memory circuit is the same as or earlier than that corresponding to the read-write operation of the first memory circuit Describes a reading and writing end time point of the reading and writing operation. 4. The test system according to claim 2, wherein the test circuit comprises: An enabling signal generating circuit, used to generate a first enabling signal and a second enabling signal; an address generating circuit for generating an address signal; and a first offset circuit, configured to generate a first offset signal according to the second enable signal and the address signal, wherein the first memory circuit performs the read and write operations according to the first enable signal and the address signal, Wherein the second memory circuit performs the read and write operations according to the first offset signal. 5. The test system according to claim 4, wherein the first offset circuit is used for comparing an address value carried by the address signal with an offset value, wherein when the address value is equal to the When the offset value is specified, the first offset circuit generates the first offset signal according to the second enable signal and the address signal to perform the read and write operations on the second memory circuit. 6. The test system according to claim 5, wherein the first offset circuit comprises: a multiplexer, configured to receive a plurality of candidate offset values, and output one of the plurality of candidate offset values according to a selection signal as the offset value; and A register is coupled to the multiplexer, wherein the register is used to generate one of the plurality of candidate offset values. 7. The test system according to claim 4, wherein the second memory circuit has a read-write end time point corresponding to the read-write operation, and the second enable signal is at the first The reading and writing end time points of the two memory circuits have a disable level. 8. The test system according to claim 4, wherein the first memory circuit has a read-write end time point corresponding to the read-write operation, and the second enable signal is at the first The reading and writing end time point of a memory circuit has a disable level. 9. The test system according to claim 4, wherein the plurality of memory circuits further comprises a third memory circuit, wherein the enable signal generating circuit is also used to generate a third enable signal, wherein The test circuit also includes: a second offset circuit, configured to generate a second offset signal according to the third enable signal and the address signal, Wherein the third memory circuit is executed according to the second offset signal to read and write operations. 10. A test method comprising: performing a read/write operation on a plurality of memory circuits by a test circuit, wherein each of the plurality of memory circuits has a read/write start time point corresponding to the read/write operation; and The multiple reading and writing start time points of the multiple memory circuits are controlled by the testing circuit to be different from each other.