CN116488622A - Low-power consumption dynamic comparator - Google Patents
Low-power consumption dynamic comparator Download PDFInfo
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- CN116488622A CN116488622A CN202310351312.6A CN202310351312A CN116488622A CN 116488622 A CN116488622 A CN 116488622A CN 202310351312 A CN202310351312 A CN 202310351312A CN 116488622 A CN116488622 A CN 116488622A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a low-power consumption comparator, comprising: the device comprises a pre-amplification stage and a latch stage, wherein an A1 end of the pre-amplification stage is connected with an A2 end of the latch stage, and a B1 end of the pre-amplification stage is connected with a B2 end of the latch stage; the upper polar plate of the capacitor C1 of the latch stage is connected with the source electrode of the MOS tube M5, the lower polar plate of the capacitor C1 is grounded, the upper polar plate of the capacitor C2 is connected with the source electrode of the MOS tube M6, the lower polar plate of the capacitor C2 is grounded, the source electrode of the MOS tube M12 is grounded, the source electrode of the MOS tube M13 is grounded, the VOP2 end of the transmission gate I2 is connected with the VOP1 of the latch stage, and the VON2 end of the transmission gate I2 is connected with the VON1 of the latch stage. According to the low-power consumption comparator, a group of capacitors and switches are introduced into the output end in the reset phase of the dynamic comparator, so that the voltage of the output end in the reset phase is not ground any more, the power consumption can be reduced, and the output end in the latch phase does not need to be charged from the ground, so that the latch output speed can be greatly improved.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a low-power consumption dynamic comparator.
Background
The comparator is one of extremely important analog circuit modules of an analog integrated circuit, and is widely applied to the fields of AD/DA conversion systems, automobile electronics, biomedical and the like. The comparator is used as an indispensable component module of the analog-to-digital converter, and the power consumption of the comparator is a main source of the power consumption of the whole analog-to-digital converterOne, the increase in the latching speed of the comparator will also greatly improve the analog-to-digital converter performance. Fig. 1 shows a conventional dynamic comparator, which can be operated in two stages, reset and latch. When the clock is at a low level, the pre-amplification circuit and latch both complete the reset operation, at which time the A, B node is charged to VDD and the nodes VOP, VON are discharged to ground; when the clock is changed to a high level, the pre-amplifier part has different discharge speeds at two points A, B due to the existence of a differential mode of an input signal, a small voltage difference exists, and a stable output result is latched through positive feedback by a later stage latch. The conventional dynamic amplifier has two problems, namely, when the comparator is reset, the output terminals VOP and VOP are both discharged to the ground, and one end of the output terminal must be charged to VDD in the latch stage, and the consumed power consumption is 0.5CVDD 2 C is the equivalent capacitance of the node, so that the power consumption of the comparator is relatively large; and secondly, the comparator charges the output terminals VOP and VON at different charging speeds according to the magnitude of the input signal in a comparison stage, and once one terminal exceeds the threshold voltage of the later stage latch, the latch latches one terminal of the output to VDD through positive feedback and latches the other terminal to ground. However, since the output ends of the reset stage are all discharged to the ground, the latch stage needs to be charged from the ground until one end exceeds the threshold voltage, and the process of charging the output ends from the ground to the threshold voltage reduces the speed of latching output of the comparator.
Disclosure of Invention
The invention aims to provide a low-power-consumption comparator which can greatly improve the latch output speed.
A low power dynamic comparator comprising: the device comprises a pre-amplification stage and a latch stage, wherein the A1 end of the pre-amplification stage is connected with the A2 end of the latch stage, and the B1 end of the pre-amplification stage is connected with the B2 end of the latch stage;
the upper polar plate of the capacitor C1 of the latch stage is connected with the source electrode of the MOS tube M5, the lower polar plate of the capacitor C1 is grounded, the upper polar plate of the capacitor C2 is connected with the source electrode of the MOS tube M6, the lower polar plate of the capacitor C2 is grounded, the MOS tube M12 is grounded, the MOS tube M13 is grounded, the VOP2 end of the transmission gate I2 is connected with the VOP1 of the latch stage, and the VON2 end of the transmission gate I2 is connected with the VON1 of the latch stage.
The pre-amplification stage comprises:
MOS tube M0, MOS tube M1, MOS tube M2, MOS tube M3 and MOS tube M4;
the grid electrode of the MOS tube M0 is connected with an input signal VIP, the source electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M1 is connected with the input signal VIN, the source electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M4 is connected with a clock signal CLK, and the source electrode of the MOS tube M4 is grounded;
the drain electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M2, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the grid electrode of the MOS tube M2 is connected with the clock signal CLK, the source electrode of the MOS tube M2 is connected with the VDD, the grid electrode of the MOS tube M3 is connected with the clock signal CLK, and the source electrode of the MOS tube M3 is connected with the VDD.
The latch stage includes:
MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, capacitor C1, capacitor C2, inverter I1 and transmission gate I2;
the grid electrode of the MOS tube M5 is connected with the output end A2 of the pre-amplification stage, the grid electrode of the MOS tube M6 is connected with the output end B2 of the pre-amplification stage, the source electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M12 and the upper polar plate of the capacitor C1, the source electrode of the MOS tube M6 is connected with the MOS tube M13 and the upper polar plate of the capacitor C2, the source electrode of the MOS tube M12 is grounded, the source electrode of the MOS tube M13 is grounded, the lower polar plate of the capacitor C1 is grounded, the grid electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M10, the grid electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M10, the grid of the MOS tube M10 is connected with the drain electrode of the MOS tube M8, the grid of the MOS tube M9 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M11 is connected with the source electrode of the MOS tube M7 and the source electrode of the MOS tube M10, the source electrode of the MOS tube M11 is connected with VDD, the grid of the MOS tube M11 is connected with the output CLKB of the inverter I1, the input of the inverter I1 is connected with a clock signal CLK, the VOP2 of the transmission gate I2 is connected with the VOP1 of the latch stage, the VON2 of the transmission gate I2 is connected with the VON1 of the latch stage, the NMOS control end of the transmission gate I2 is connected with CLKB, and the PMOS control end of the transmission gate I2 is connected with CLK.
A low power consumption dynamic comparator control method comprising: a low power dynamic comparator is used for reset and latching.
Resetting using a low power dynamic comparator includes:
in the reset stage, the clock signal CLK is low level, the MOS transistor M4 is closed, the MOS transistor M2 and the MOS transistor M3 are conducted, and the output ends A1 and B1 of the pre-amplification stage are reset to VDD. The method comprises the steps of carrying out a first treatment on the surface of the
Input tubes M5 and M6 of the latch stage are conducted, MOS tubes M12 and M13 are closed, a transmission gate I2 is conducted, output ends VOP and VON are communicated, charges stored in the equivalent capacitors of the output ends VOP and VON in the last working stage are shared with capacitors C1 and C2, and the voltages of the output ends VOP and VON in the reset stage are reset to 0.3VDD.
Latching using a low power dynamic comparator includes:
in the latch stage, the clock signal CLK is high level, the clock signal CLKB is low level, the MOS transistors M2 and M3 are closed, the MOS transistor M4 is conducted, and the input transistors M0 and M1 discharge the output ends A1 and B1 at different speeds according to the magnitude of the input signal;
MOS tubes M11, M12 and M13 of the latch stage are conducted, output ends VOP and VON are charged on the basis of 0.3VDD until one end of the MOS tubes is charged to a threshold voltage, a latch positive feedback effect is triggered, one end of the MOS tubes is pulled up to VDD, and the other end of the MOS tubes is pulled down to ground, and output results are latched.
An electronic device employing a low power dynamic comparator as claimed in any one of the preceding claims.
A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements a low power dynamic comparator control method as defined in any one of the preceding claims when executing the computer program.
A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements a low power dynamic comparator control method as defined in any one of the claims.
The invention adds two capacitors and three switches in the latch stage, so that the output end of the comparator is not directly reset to the ground through the switch conduction in the reset stage, but the charge sharing occurs between the switch and the added capacitor, and the output end is reset to about 0.3VDD, thusThe power consumption consumed in the comparator during the latch phase is from 0.5CVDD 2 Reduced to (1-0.3) x 0.5CVDD 2 The power consumption of the comparator is significantly reduced.
The invention can reduce the power consumption and increase the latch output speed of the comparator because the output end of the latch stage does not need to be charged from the ground, but is from 0.3VDD 2 And the latch positive feedback latch output result of the later stage latch can be triggered after the latch is charged to the threshold voltage, so that the latch output speed of the comparator is greatly improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a pre-amp stage of the present invention;
FIG. 2 is a schematic diagram of a latch stage of the present invention;
FIG. 3 is a circuit diagram of the present invention;
fig. 4 is a graph showing the output waveforms and clocks of the conventional comparator of the present invention and the comparator of the present invention over time.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Because the traditional comparator resets, the output terminals VOP and VOP are all discharged to the ground, one end of the output terminal must be charged to VDD in the latching stage, the consumed power consumption is 0.5CVDD2, C is the equivalent capacitance of the node, so that the power consumption of the comparator is relatively large, the output terminal in the resetting stage is all discharged to the ground, the latching result of the comparator can be obtained only after one end of the output terminal exceeds the threshold voltage in the latching stage, and the process of charging the output terminal from the ground to the threshold voltage reduces the latching output speed of the comparator.
In order to overcome the disadvantages of the conventional comparator, the invention introduces a group of capacitors and switches at the output end in the reset stage of the dynamic comparator, so that the voltage at the output end of the reset stage is not ground but approximately equal to 0.3VDD, thus the power consumption of the dynamic comparator in the latch stage is reduced to (1-0.3) x 0.5CVDD 2 About 30% lower power consumption compared to conventional dynamic comparators. The latch phase output also does not need to be charged from ground, but from 0.3VDD 2 And the latch positive feedback latch output result of the later stage latch can be triggered after the latch is charged to the threshold voltage, so that the latch output speed of the comparator is greatly improved.
Example 1
A low power dynamic comparator, as in fig. 1, comprising: the device comprises a pre-amplification stage and a latch stage, wherein the A1 end of the pre-amplification stage is connected with the A2 end of the latch stage, and the B1 end of the pre-amplification stage is connected with the B2 end of the latch stage;
the upper polar plate of the capacitor C1 of the latch stage is connected with the source electrode of the MOS tube M5, the lower polar plate of the capacitor C1 is grounded, the upper polar plate of the capacitor C2 is connected with the source electrode of the MOS tube M6, the lower polar plate of the capacitor C2 is grounded, the MOS tube M12 is grounded, the MOS tube M13 is grounded, the VOP2 end of the transmission gate I2 is connected with the VOP1 of the latch stage, and the VON2 end of the transmission gate I2 is connected with the VON1 of the latch stage.
The pre-amplification stage is as in fig. 2, comprising:
MOS tube M0, MOS tube M1, MOS tube M2, MOS tube M3 and MOS tube M4;
the grid electrode of the MOS tube M0 is connected with an input signal VIP, the source electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M1 is connected with the input signal VIN, the source electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M4 is connected with a clock signal CLK, and the source electrode of the MOS tube M4 is grounded;
the drain electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M2, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the grid electrode of the MOS tube M2 is connected with the clock signal CLK, the source electrode of the MOS tube M2 is connected with the VDD, the grid electrode of the MOS tube M3 is connected with the clock signal CLK, and the source electrode of the MOS tube M3 is connected with the VDD.
The latch stage is as in FIG. 3, comprising:
MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, capacitor C1, capacitor C2, inverter I1 and transmission gate I2;
the grid electrode of the MOS tube M5 is connected with the output end A2 of the pre-amplification stage, the grid electrode of the MOS tube M6 is connected with the output end B2 of the pre-amplification stage, the source electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M12 and the upper polar plate of the capacitor C1, the source electrode of the MOS tube M6 is connected with the MOS tube M13 and the upper polar plate of the capacitor C2, the source electrode of the MOS tube M12 is grounded, the source electrode of the MOS tube M13 is grounded, the lower polar plate of the capacitor C1 is grounded, the grid electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M10, the grid electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M10, the grid of the MOS tube M10 is connected with the drain electrode of the MOS tube M8, the grid of the MOS tube M9 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M11 is connected with the source electrode of the MOS tube M7 and the source electrode of the MOS tube M10, the source electrode of the MOS tube M11 is connected with VDD, the grid of the MOS tube M11 is connected with the output CLKB of the inverter I1, the input of the inverter I1 is connected with a clock signal CLK, the VOP2 of the transmission gate I2 is connected with the VOP1 of the latch stage, the VON2 of the transmission gate I2 is connected with the VON1 of the latch stage, the NMOS control end of the transmission gate I2 is connected with CLKB, and the PMOS control end of the transmission gate I2 is connected with CLK.
Example 2
A low power consumption dynamic comparator control method comprising: a low power dynamic comparator is used for reset and latching.
Resetting using a low power dynamic comparator includes:
in the reset stage, the clock signal CLK is low level, the MOS transistor M4 is closed, the MOS transistor M2 and the MOS transistor M3 are conducted, and the output ends A1 and B1 of the pre-amplification stage are reset to VDD. The method comprises the steps of carrying out a first treatment on the surface of the
Input tubes M5 and M6 of the latch stage are conducted, MOS tubes M12 and M13 are closed, a transmission gate I2 is conducted, output ends VOP and VON are communicated, charges stored in the equivalent capacitors of the output ends VOP and VON in the last working stage are shared with capacitors C1 and C2, and the voltages of the output ends VOP and VON in the reset stage are reset to 0.3VDD.
Latching using a low power dynamic comparator includes:
in the latch stage, the clock signal CLK is high level, the clock signal CLKB is low level, the MOS transistors M2 and M3 are closed, the MOS transistor M4 is conducted, and the input transistors M0 and M1 discharge the output ends A1 and B1 at different speeds according to the magnitude of the input signal;
MOS tubes M11, M12 and M13 of the latch stage are conducted, output ends VOP and VON are charged on the basis of 0.3VDD until one end of the MOS tubes is charged to a threshold voltage, a latch positive feedback effect is triggered, one end of the MOS tubes is pulled up to VDD, and the other end of the MOS tubes is pulled down to ground, and output results are latched.
The working process of the comparator for low power consumption and quick latching can be divided into a reset stage and a latch stage, in the reset stage, a clock signal CLK is low level, a MOS tube M4 is closed, a MOS tube M2 and a MOS tube M3 are conducted, and an output end A, B of the pre-amplification stage is reset to VDD. At this time, the input tubes M5 and M6 of the latch stage are also turned on, the MOS tubes M12 and M13 are turned off, the transmission gate I2 is turned on, the output terminals VOP and VON are turned on, and the charges stored in the equivalent capacitors of the output terminals VOP and VON at the previous stage are shared with the capacitors C1 and C2, so that the voltages of the output terminals VOP and VON at the reset stage are reset to about 0.3VDD, which is different from the voltages of the output terminals VOP and VON at the reset stage of the conventional dynamic comparator.
In the latch stage, the clock signal CLK is high, CLKB is low, the MOS transistors M2 and M3 are turned off, the MOS transistor M4 is turned on, and the input transistors M0 and M1 discharge the output terminal A, B at different speeds according to the magnitude of the input signal. At this time, the MOS transistors M11, M12 and M13 of the latch stage are turned on, the output terminals VOP and VON are charged on the basis of 0.3VDD until one of the terminals is charged to the threshold voltage, the latch positive feedback effect is triggered, one terminal is pulled up to VDD, and the other terminal is pulled down to ground, and the output result is latched. Because the output end of the comparison stage is not charged from the ground, but is charged from about 0.3VDD to the threshold voltage, the positive feedback latch output result of the later stage latch can be triggered, and compared with the traditional dynamic comparator, the latch output speed of the comparator is improved.
In order to further verify the technical effect of the invention, the application adopts a 65nm CMOS process, and the same simulation experiment is carried out on the traditional dynamic comparator and the dynamic comparator with low power consumption and quick latch output of the invention, as shown in fig. 4, the same part of pipes such as input/output pipes adopt the same size and load capacitance. The frequency of the clock signal CLK is 1Mhz, the power supply voltage is 1V, the common mode voltage is 0.5V, the differential input Δv=2mv, and the conventional comparator and the inventive comparator are output waveforms and the time-dependent curves of the clock are shown in fig. 3. It can be seen that the output of the conventional dynamic comparator is reset to ground during the low level clock signal CLK, i.e., the comparator reset phase, whereas the dynamic comparator of the present invention is reset to about 0.3VDD, and the latch output result is obtained earlier than the conventional dynamic comparator during the high level clock signal CLK, i.e., the comparator latch phase, indicating that the dynamic comparator of the present invention has the advantage of fast latch output. The average power consumption of the traditional dynamic comparator and the power consumption of the dynamic comparator in transient simulation are calculated respectively, the power consumption of the traditional dynamic comparator is 1.85uW, the power consumption of the dynamic comparator is 1.35uW, the power consumption is reduced by 27%, and the power consumption is basically consistent with the theoretical reduction by 30%, so that the dynamic comparator has the advantage of low power consumption.
Example 3
An electronic device employing a low power dynamic comparator as claimed in any one of the preceding claims.
Example 4
A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements a low power dynamic comparator control method as defined in any one of the preceding claims when executing the computer program.
Example 5
A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements a low power dynamic comparator control method as defined in any one of the claims.
The invention adds two capacitors and three switches through the latch stage, so that the output end of the comparator is not directly reset to the ground through the switch conduction in the reset stage, but is subjected to charge sharing through the switch and the added capacitor, and the output end is reset to about 0.3VDD, thus the power consumption of the comparator in the latch stage is from 0.5CVDD 2 Reduced to (1-0.3) x 0.5CVDD 2 The power consumption of the comparator is significantly reduced.
The invention can reduce the power consumption and increase the latch output speed of the comparator because the output end of the latch stage does not need to be charged from the ground, but is from 0.3VDD 2 And the latch positive feedback latch output result of the later stage latch can be triggered after the latch is charged to the threshold voltage, so that the latch output speed of the comparator is greatly improved.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A low power dynamic comparator, comprising: the device comprises a pre-amplification stage and a latch stage, wherein an A1 end of the pre-amplification stage is connected with an A2 end of the latch stage, and a B1 end of the pre-amplification stage is connected with a B2 end of the latch stage;
the upper polar plate of the capacitor C1 of the latch stage is connected with the source electrode of the MOS tube M5, the lower polar plate of the capacitor C1 is grounded, the upper polar plate of the capacitor C2 is connected with the source electrode of the MOS tube M6, the lower polar plate of the capacitor C2 is grounded, the source electrode of the MOS tube M12 is grounded, the source electrode of the MOS tube M13 is grounded, the VOP2 end of the transmission gate I2 is connected with the VOP1 of the latch stage, and the VON2 end of the transmission gate I2 is connected with the VON1 of the latch stage.
2. The low power dynamic comparator of claim 1, wherein said pre-amplification stage comprises:
MOS tube M0, MOS tube M1, MOS tube M2, MOS tube M3 and MOS tube M4;
the grid electrode of the MOS tube M0 is connected with an input signal VIP, the source electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M1 is connected with the input signal VIN, the source electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M4 is connected with a clock signal CLK, and the source electrode of the MOS tube M4 is grounded;
the drain electrode of the MOS tube M0 is connected with the drain electrode of the MOS tube M2, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the grid electrode of the MOS tube M2 is connected with the clock signal CLK, the source electrode of the MOS tube M2 is connected with the VDD, the grid electrode of the MOS tube M3 is connected with the clock signal CLK, and the source electrode of the MOS tube M3 is connected with the VDD.
3. The low power dynamic comparator of claim 1, wherein said latch stage comprises:
MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, capacitor C1, capacitor C2, inverter I1 and transmission gate I2;
the grid electrode of the MOS tube M5 is connected with the output end A2 of the pre-amplification stage, the grid electrode of the MOS tube M6 is connected with the output end B2 of the pre-amplification stage, the source electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M12 and the upper polar plate of the capacitor C1, the source electrode of the MOS tube M6 is connected with the MOS tube M13 and the upper polar plate of the capacitor C2, the source electrode of the MOS tube M12 is grounded, the source electrode of the MOS tube M13 is grounded, the lower polar plate of the capacitor C1 is grounded, the grid electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M10, the grid electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M10, the grid of the MOS tube M10 is connected with the drain electrode of the MOS tube M8, the grid of the MOS tube M9 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M11 is connected with the source electrode of the MOS tube M7 and the source electrode of the MOS tube M10, the source electrode of the MOS tube M11 is connected with VDD, the grid of the MOS tube M11 is connected with the output CLKB of the inverter I1, the input of the inverter I1 is connected with a clock signal CLK, the VOP2 of the transmission gate I2 is connected with the VOP1 of the latch stage, the VON2 of the transmission gate I2 is connected with the VON1 of the latch stage, the NMOS control end of the transmission gate I2 is connected with CLKB, and the PMOS control end of the transmission gate I2 is connected with CLK.
4. A method for controlling a low power dynamic comparator, comprising: and resetting and latching by using the low-power dynamic comparator.
5. The method of claim 4, wherein the resetting using the low power dynamic comparator comprises:
in the reset stage, the clock signal CLK is low level, the MOS transistor M4 is closed, the MOS transistor M2 and the MOS transistor M3 are conducted, and the output ends A1 and B1 of the pre-amplification stage are reset to VDD. The method comprises the steps of carrying out a first treatment on the surface of the
Input tubes M5 and M6 of the latch stage are conducted, MOS tubes M12 and M13 are closed, a transmission gate I2 is conducted, output ends VOP and VON are communicated, charges stored in the equivalent capacitors of the output ends VOP and VON in the last working stage are shared with capacitors C1 and C2, and the voltages of the output ends VOP and VON in the reset stage are reset to 0.3VDD.
6. The method of claim 4, wherein said latching using said low power dynamic comparator comprises:
in the latch stage, the clock signal CLK is high level, the clock signal CLKB is low level, the MOS transistors M2 and M3 are closed, the MOS transistor M4 is conducted, and the input transistors M0 and M1 discharge the output ends A1 and B1 at different speeds according to the magnitude of the input signal;
MOS tubes M11, M12 and M13 of the latch stage are conducted, output ends VOP and VON are charged on the basis of 0.3VDD until one end of the MOS tubes is charged to a threshold voltage, a latch positive feedback effect is triggered, one end of the MOS tubes is pulled up to VDD, and the other end of the MOS tubes is pulled down to ground, and output results are latched.
7. An electronic device, characterized in that a low-power dynamic comparator as claimed in any one of claims 1 to 3 is applied.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements a low power dynamic comparator control method according to any one of claims 4 to 6 when executing the computer program.
9. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements a low power consumption dynamic comparator control method according to any of claims 4 to 6.
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