CN116488587B - Double-frequency multiplier based on half-wave rectification superposition - Google Patents
Double-frequency multiplier based on half-wave rectification superposition Download PDFInfo
- Publication number
- CN116488587B CN116488587B CN202310740413.2A CN202310740413A CN116488587B CN 116488587 B CN116488587 B CN 116488587B CN 202310740413 A CN202310740413 A CN 202310740413A CN 116488587 B CN116488587 B CN 116488587B
- Authority
- CN
- China
- Prior art keywords
- field effect
- effect transistor
- type field
- transformer
- push
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004804 winding Methods 0.000 claims abstract description 13
- 230000005669 field effect Effects 0.000 claims description 56
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 230000001629 suppression Effects 0.000 abstract description 4
- 238000004891 communication Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Amplifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a half-wave rectification superposition-based double-frequency multiplier, which relates to the technical field of radio frequency communication and comprises an I-path push-push frequency multiplier, a Q-path push-push frequency multiplier, a transformer TR and a matching network; the I-path push-push frequency multiplier is connected with one end of a primary coil of the transformer TR; the Q-path push-push frequency multiplier is connected with the other end of the primary coil of the transformer TR; the middle tap end of the primary coil of the transformer TR is connected with one end of the matching network; the other end of the matching network is used as a frequency-quadrupling output end; one end of the secondary winding of the transformer TR serves as a frequency doubling output end, and the other end of the secondary winding of the transformer TR is grounded. The double-frequency converter provided by the invention can output the second harmonic wave and the fourth harmonic wave respectively under the condition of not influencing the conversion gain, thereby improving the conversion efficiency and expanding the output bandwidth; the filter has good harmonic suppression degree under the condition of not using the filter, and is suitable for more complex system application.
Description
Technical Field
The invention relates to the technical field of radio frequency communication, in particular to a double-frequency multiplier based on half-wave rectification superposition.
Background
With the rapid development of the internet of things and wireless communication technology, the radio frequency transceiver system needs to meet a series of requirements of higher frequency, smaller size, lower power consumption, higher reliability and the like. Frequency multipliers are one of the cores in rf transceiver modules, and their performance directly affects the accuracy of signal transmission and reception, so frequency multipliers face great demands and challenges. As the frequency multiplication times increase, the conversion gain of the frequency multiplier device may decrease, resulting in a narrowing of the output frequency bandwidth of the frequency multiplier, while the degree of suppression of harmonics may be deteriorated.
In order to solve the problem, researchers put forward a traditional half-wave rectification superposition quadrupler based on a push-push structure, and design is carried out by adopting IQ two paths. The four-frequency multiplier is used for superposing half-wave rectification generated by the IQ two-way push-push frequency multiplier, and then the fourth harmonic wave and the second and sixth low-order harmonic waves are reserved for counteracting. In addition, researchers have proposed a frequency doubler scheme, which also uses IQ two paths for design. After half-wave rectification is generated by the two paths of push-push frequency multipliers of the IQ, the half-wave voltage is converted into two paths of half-wave voltages through a load, and after difference is made, the output power of the second harmonic is improved, and four times of low-order harmonic waves are counteracted. However, both frequency multipliers have the problems of low conversion efficiency and small output bandwidth.
Disclosure of Invention
Aiming at the defects in the prior art, the double-frequency multiplier based on half-wave rectification superposition solves the problems of low efficiency and small output bandwidth of the frequency multiplier in the prior art.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the double-frequency multiplier based on half-wave rectification superposition comprises an I-path push-push frequency multiplier, a Q-path push-push frequency multiplier, a transformer TR and a matching network; the I-path push-push frequency multiplier is connected with one end of a primary coil of the transformer TR; the Q-path push-push frequency multiplier is connected with the other end of the primary coil of the transformer TR; the middle tap end of the primary coil of the transformer TR is connected with one end of the matching network; the other end of the matching network is used as a frequency-quadrupling output end; one end of the secondary winding of the transformer TR serves as a frequency doubling output end, and the other end of the secondary winding of the transformer TR is grounded.
Further, the output of the intermediate tap end of the primary coil of the transformer TR is a common mode signal; the output of the secondary winding of the transformer TR is a differential mode signal.
Further, the I-channel push-push frequency multiplier comprises a metal oxide semiconductor N-type field effect transistor M1N and a metal oxide semiconductor N-type field effect transistor M2N; the drain electrode of the N-type field effect transistor M1N is connected with the drain electrode of the N-type field effect transistor M2N and is connected with one end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M1N is used as a first input terminal V1; the source electrode of the N-type field effect transistor M1N is connected with the source electrode of the N-type field effect transistor M2N and grounded; the gate of the N-type field effect transistor M2N serves as the second input terminal V2.
Further, the Q-channel push-push frequency multiplier comprises a metal oxide semiconductor N-type field effect transistor M3N and a metal oxide semiconductor N-type field effect transistor M4N; the drain electrode of the N-type field effect transistor M3N is connected with the drain electrode of the N-type field effect transistor M4N and is connected with the other end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M3N is used as a third input terminal V3; the source electrode of the N-type field effect transistor M3N is connected with the source electrode of the N-type field effect transistor M4N and grounded; the gate of the N-type field effect transistor M4N serves as the fourth input terminal V4.
Further, the input signal of the first input terminal V1 and the input signal of the second input terminal V2 are differential signals, and the input signal of the first input terminal V1 and the input signal of the third input terminal V3 are orthogonal signals; the input signal of the second input end V2 and the input signal of the fourth input end V4 are orthogonal signals; the input signal of the third input terminal V3 and the input signal of the fourth input terminal V4 are differential signals.
Further, the matching network comprises an inductor L1, an inductor L2 and a capacitor C; one end of the inductor L1 is connected with the voltage end VDD, and the other end of the inductor L1 is respectively connected with one end of the capacitor C and the middle tap end of the primary coil of the transformer TR; the other end of the capacitor C is connected with the grounding inductance L2 and is used as a frequency-multiplied output end.
The beneficial effects of the invention are as follows:
1. the double-frequency converter provided by the invention can respectively output the second harmonic wave and the fourth harmonic wave without influencing the conversion gain, thereby improving the conversion efficiency and expanding the output bandwidth.
2. The double-frequency converter provided by the invention has a good harmonic suppression degree under the condition of not using a filter based on a half-wave rectification superposition principle.
Drawings
FIG. 1 is a circuit diagram of a half-wave rectification superposition-based two-quad frequency converter of the present invention;
FIG. 2 shows drain currents of N-type field effect transistors M1N and M2NA sum waveform diagram;
FIG. 3 shows drain currents of N-type field effect transistor M3N and N-type field effect transistor M4NA sum waveform diagram;
FIG. 4 shows the current of the center tap of the primary winding of the transformer TRA waveform diagram;
fig. 5 shows the current of the secondary winding of the transformer TRA waveform diagram;
FIG. 6 is a graph of the output power of the frequency doubler of the present invention;
fig. 7 is a graph of four-frequency output power of the inventive two-quad-frequency.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, a half-wave rectification superposition-based double-frequency multiplier comprises an I-path push-push frequency multiplier, a Q-path push-push frequency multiplier, a transformer TR and a matching network; the I-path push-push frequency multiplier is connected with one end of a primary coil of the transformer TR; the Q-path push-push frequency multiplier is connected with the other end of the primary coil of the transformer TR; the middle tap end of the primary coil of the transformer TR is connected with one end of the matching network; the other end of the matching network is used as a frequency-quadrupling output end; one end of the secondary winding of the transformer TR serves as a frequency doubling output end, and the other end of the secondary winding of the transformer TR is grounded.
The output of the middle tap end of the primary coil of the transformer TR is a common mode signal; the output of the secondary winding of the transformer TR is a differential mode signal.
The I-path push-push frequency multiplier comprises an N-type field effect transistor M1N of a metal oxide semiconductor and an N-type field effect transistor M2N of the metal oxide semiconductor; the drain electrode of the N-type field effect transistor M1N is connected with the drain electrode of the N-type field effect transistor M2N and is connected with one end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M1N is used as a first input terminal V1; the source electrode of the N-type field effect transistor M1N is connected with the source electrode of the N-type field effect transistor M2N and grounded; the gate of the N-type field effect transistor M2N serves as the second input terminal V2.
The Q-path push-push frequency multiplier comprises an N-type field effect transistor M3N of a metal oxide semiconductor and an N-type field effect transistor M4N of the metal oxide semiconductor; the drain electrode of the N-type field effect transistor M3N is connected with the drain electrode of the N-type field effect transistor M4N and is connected with the other end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M3N is used as a third input terminal V3; the source electrode of the N-type field effect transistor M3N is connected with the source electrode of the N-type field effect transistor M4N and grounded; the gate of the N-type field effect transistor M4N serves as the fourth input terminal V4.
The input signal of the first input end V1 and the input signal of the second input end V2 are differential signals, and the input signal of the first input end V1 and the input signal of the third input end V3 are orthogonal signals; the input signal of the second input end V2 and the input signal of the fourth input end V4 are orthogonal signals; the input signal of the third input terminal V3 and the input signal of the fourth input terminal V4 are differential signals.
The matching network comprises an inductor L1, an inductor L2 and a capacitor C; one end of the inductor L1 is connected with the voltage end VDD, and the other end of the inductor L1 is respectively connected with one end of the capacitor C and the middle tap end of the primary coil of the transformer TR; the other end of the capacitor C is connected with the grounding inductance L2 and is used as a frequency-multiplied output end.
In one embodiment of the invention, the gates of the four metal oxide semiconductor N-type field effect transistors are all biased near the threshold voltage. For N-type field effect transistor M1N and N-type field effect transistor M2N, the drains are connected, and the corresponding grid input signals are respectivelyAnd->The sum of I-path drain current can be obtained>The waveforms are shown in fig. 2, and the corresponding formulas are as follows:
wherein,,representing the current amplitude.
For N-type field effect transistor M3N and N-type field effect transistor M4N, the drains are connected, and the corresponding gate input signals are respectivelyAnd->The sum of the drain currents of the Q paths can be obtained>The waveforms are shown in fig. 3, and the corresponding formulas are as follows:
for the common mode signal output from the center tap of the primary winding of the transformer TR, its current is as shown in fig. 4Is the sum of I-channel drain currents->And Q-way drain current sum +.>The corresponding formula is as follows:
it can be seen that the second order even harmonics, the sixth order even harmonics and the like are all counteracted, and the fourth harmonic is reserved.
For the differential mode signal output from the secondary winding of the transformer TR, the current is as shown in fig. 5Is the sum of I-channel drain currents->And Q-way drain current sum +.>The corresponding formula is as follows:
the direct-current term, the fourth-order low-order even harmonic wave and the like are counteracted, the second harmonic wave is reserved, and the function of doubling frequency is realized. Wherein,,the coil ratio of the primary coil and the secondary coil of the transformer TR is represented.
Simulation is carried out on a double-frequency multiplier based on half-wave rectification superposition, under the condition of ideal matching of input and output, an orthogonal all-pass filter QAF is adopted as an orthogonal generator, and the conditions are set: the input signal frequency is 10GHz and the quadrature generator QAF provides a quadrature signal power of 3dBm. As shown in fig. 6 and 7, the simulation results are: the second harmonic output power was 10dBm and the fourth harmonic output power was-2.5 dBm.
In summary, the two-quad frequency converter provided by the invention can output the second harmonic and the fourth harmonic respectively without affecting the conversion gain, thereby improving the conversion efficiency and expanding the output bandwidth; the double-frequency converter provided by the invention has a good harmonic suppression degree under the condition of not using a filter based on a half-wave rectification superposition principle.
Claims (3)
1. The utility model provides a two quadruplers based on half wave rectification stack which characterized in that: the device comprises an I-path push-push frequency multiplier, a Q-path push-push frequency multiplier, a transformer TR and a matching network; the I-path push-push frequency multiplier is connected with one end of a primary coil of the transformer TR; the Q-path push-push frequency multiplier is connected with the other end of the primary coil of the transformer TR; the middle tap end of the primary coil of the transformer TR is connected with one end of a matching network; the other end of the matching network is used as a frequency-quadrupling output end; one end of the secondary coil of the transformer TR is used as a doubling output end, and the other end of the secondary coil of the transformer TR is grounded;
the I-path push-push frequency multiplier comprises an N-type field effect transistor M1N of a metal oxide semiconductor and an N-type field effect transistor M2N of the metal oxide semiconductor; the drain electrode of the N-type field effect transistor M1N is connected with the drain electrode of the N-type field effect transistor M2N and is connected with one end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M1N is used as a first input terminal V1; the source electrode of the N-type field effect transistor M1N is connected with the source electrode of the N-type field effect transistor M2N and grounded; the gate of the N-type field effect transistor M2N is used as a second input terminal V2;
the Q-channel push-push frequency multiplier comprises an N-type field effect transistor M3N of a metal oxide semiconductor and an N-type field effect transistor M4N of the metal oxide semiconductor; the drain electrode of the N-type field effect transistor M3N is connected with the drain electrode of the N-type field effect transistor M4N and is connected with the other end of the primary coil of the transformer TR; the gate of the N-type field effect transistor M3N is used as a third input terminal V3; the source electrode of the N-type field effect transistor M3N is connected with the source electrode of the N-type field effect transistor M4N and grounded; the gate of the N-type field effect transistor M4N is used as a fourth input terminal V4;
the input signal of the first input end V1 and the input signal of the second input end V2 are differential signals, and the input signal of the first input end V1 and the input signal of the third input end V3 are orthogonal signals; the input signal of the second input end V2 and the input signal of the fourth input end V4 are orthogonal signals; the input signal of the third input terminal V3 and the input signal of the fourth input terminal V4 are differential signals.
2. The half-wave rectification superposition based doubler of claim 1, wherein: the output of the middle tap end of the primary coil of the transformer TR is a common mode signal; the output of the secondary winding of the transformer TR is a differential mode signal.
3. The half-wave rectification superposition based doubler of claim 1, wherein: the matching network comprises an inductor L1, an inductor L2 and a capacitor C; one end of the inductor L1 is connected with the voltage end VDD, and the other end of the inductor L1 is respectively connected with one end of the capacitor C and the middle tap end of the primary coil of the transformer TR; the other end of the capacitor C is connected with the grounding inductance L2 and is used as a frequency-multiplied output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310740413.2A CN116488587B (en) | 2023-06-21 | 2023-06-21 | Double-frequency multiplier based on half-wave rectification superposition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310740413.2A CN116488587B (en) | 2023-06-21 | 2023-06-21 | Double-frequency multiplier based on half-wave rectification superposition |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116488587A CN116488587A (en) | 2023-07-25 |
| CN116488587B true CN116488587B (en) | 2023-08-29 |
Family
ID=87227228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310740413.2A Active CN116488587B (en) | 2023-06-21 | 2023-06-21 | Double-frequency multiplier based on half-wave rectification superposition |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116488587B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118573121B (en) * | 2024-08-05 | 2024-11-05 | 香港中文大学（深圳） | Complementary inductance-free frequency doubler based on pseudo push-push |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB561729A (en) * | 1943-02-17 | 1944-06-01 | Philip Theobald Hobson | Improvements in and relating to electrical musical instruments |
| WO2016041575A1 (en) * | 2014-09-16 | 2016-03-24 | Telefonaktiebolaget L M Ericsson (Publ) | A power efficient frequency multiplier |
| JP2018067878A (en) * | 2016-10-21 | 2018-04-26 | 株式会社デンソー | Frequency multiplier |
| CN109617530A (en) * | 2018-11-26 | 2019-04-12 | 上海奥令科电子科技有限公司 | A push-push note-lock frequency multiplier circuit |
| CN112615590A (en) * | 2020-12-18 | 2021-04-06 | 电子科技大学 | TSM-PI frequency tripler based on double-balanced frequency mixing |
| CN112671344A (en) * | 2020-12-18 | 2021-04-16 | 电子科技大学 | Transformer-based self-mixing frequency tripler with voltage-controlled capacitor matching |
| CN215344502U (en) * | 2021-07-16 | 2021-12-28 | 成都通量科技有限公司 | Frequency doubler circuit with high harmonic suppression broadband |
| EP4016839A1 (en) * | 2020-12-21 | 2022-06-22 | Intel Corporation | Biasing scheme for constant regulated local oscillator in mm-wave tripler |
| CN114710119A (en) * | 2022-04-19 | 2022-07-05 | 东南大学 | Millimeter wave injection locking frequency tripler |
| CN114759879A (en) * | 2022-05-20 | 2022-07-15 | 成都通量科技有限公司 | Push-push based frequency doubler and frequency tripler |
| CN115483888A (en) * | 2022-09-13 | 2022-12-16 | 成都通量科技有限公司 | High conversion gain quadrupler |
| CN115575900A (en) * | 2022-10-17 | 2023-01-06 | 浙江大学 | Low-power-consumption fully-differential multi-harmonic IQ zero intermediate frequency mixing circuit |
| CN115967356A (en) * | 2022-12-09 | 2023-04-14 | 南京汇君半导体科技有限公司 | Harmonic suppression-based frequency doubling circuit structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10355678B2 (en) * | 2016-12-05 | 2019-07-16 | The Regents Of The University Of California | High-efficiency frequency doubler with a compensated transformer-based input balun |
-
2023
- 2023-06-21 CN CN202310740413.2A patent/CN116488587B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB561729A (en) * | 1943-02-17 | 1944-06-01 | Philip Theobald Hobson | Improvements in and relating to electrical musical instruments |
| WO2016041575A1 (en) * | 2014-09-16 | 2016-03-24 | Telefonaktiebolaget L M Ericsson (Publ) | A power efficient frequency multiplier |
| JP2018067878A (en) * | 2016-10-21 | 2018-04-26 | 株式会社デンソー | Frequency multiplier |
| CN109617530A (en) * | 2018-11-26 | 2019-04-12 | 上海奥令科电子科技有限公司 | A push-push note-lock frequency multiplier circuit |
| CN112615590A (en) * | 2020-12-18 | 2021-04-06 | 电子科技大学 | TSM-PI frequency tripler based on double-balanced frequency mixing |
| CN112671344A (en) * | 2020-12-18 | 2021-04-16 | 电子科技大学 | Transformer-based self-mixing frequency tripler with voltage-controlled capacitor matching |
| EP4016839A1 (en) * | 2020-12-21 | 2022-06-22 | Intel Corporation | Biasing scheme for constant regulated local oscillator in mm-wave tripler |
| CN215344502U (en) * | 2021-07-16 | 2021-12-28 | 成都通量科技有限公司 | Frequency doubler circuit with high harmonic suppression broadband |
| CN114710119A (en) * | 2022-04-19 | 2022-07-05 | 东南大学 | Millimeter wave injection locking frequency tripler |
| CN114759879A (en) * | 2022-05-20 | 2022-07-15 | 成都通量科技有限公司 | Push-push based frequency doubler and frequency tripler |
| CN115483888A (en) * | 2022-09-13 | 2022-12-16 | 成都通量科技有限公司 | High conversion gain quadrupler |
| CN115575900A (en) * | 2022-10-17 | 2023-01-06 | 浙江大学 | Low-power-consumption fully-differential multi-harmonic IQ zero intermediate frequency mixing circuit |
| CN115967356A (en) * | 2022-12-09 | 2023-04-14 | 南京汇君半导体科技有限公司 | Harmonic suppression-based frequency doubling circuit structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116488587A (en) | 2023-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112671344B (en) | Transformer-based self-mixing frequency tripler with voltage-controlled capacitor matching | |
| CN112615590A (en) | TSM-PI frequency tripler based on double-balanced frequency mixing | |
| CN111934629A (en) | Broadband high-linearity power amplifier | |
| CN116488587B (en) | Double-frequency multiplier based on half-wave rectification superposition | |
| CN105897194B (en) | A kind of continuous EF class high efficiency wideband power amplifer and its implementation | |
| CN112671346A (en) | Broadband frequency multiplier with transconductance enhancement technology and double LC matching networks | |
| CN116996023A (en) | Broadband passive frequency multiplier and chip | |
| CN112737363A (en) | Compact high-power microwave rectification circuit | |
| US7672658B2 (en) | Frequency-converting circuit and down converter with the same | |
| Jimenez et al. | Self-biased 2.4 GHz CMOS RF-to-DC converter with 80% efficiency and− 22.04 dBm sensitivity for Wi-Fi energy harvesting | |
| CN219978389U (en) | High-precision sampling circuit for high-frequency current | |
| WO2016041575A1 (en) | A power efficient frequency multiplier | |
| CN215344502U (en) | Frequency doubler circuit with high harmonic suppression broadband | |
| Elazar et al. | Rectifier circuit for 5g mm-wave energy harvesting using capacitor boosted cross-coupled topology in 65nm cmos | |
| CN115733445A (en) | Broadband high-frequency low-frequency-multiplication-loss high-harmonic-suppression frequency doubler chip | |
| CN217849396U (en) | Radio frequency broadband frequency doubling module | |
| Moody | A Double Balanced Frequency Doubler Achieving 70% Drain Efficiency and 25% Total Efficiency | |
| CN205232158U (en) | Full balanced mixer of high linearity | |
| CN114157241B (en) | Millimeter wave reconfigurable frequency multiplier circuit and control method thereof | |
| CN105471391A (en) | High linearity fully-balanced mixer | |
| CN115314056A (en) | a broadband transmitter | |
| CN218570197U (en) | Broadband high-frequency low-frequency-multiplication-loss high-harmonic-suppression frequency doubler chip | |
| CN205647440U (en) | Edge combination formula digital frequency multiplier based on transformer on piece | |
| CN107733370B (en) | Broadband single-balance frequency tripler based on 0.13um SiGeBiCMOS process | |
| CN220139526U (en) | Wide bandwidth mixer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |