CN116471842A - Non-volatile memory device - Google Patents

Abstract

The invention discloses a non-volatile memory element, which comprises at least one memory unit, wherein the memory unit comprises a substrate, an auxiliary gate structure, a tunneling dielectric layer, a floating gate and an upper gate structure. The auxiliary gate structure is disposed on the substrate. The floating gate includes two opposing first uppermost edges disposed along a first direction, two opposing first sidewalls disposed along the first direction, and two opposing second sidewalls disposed along a second direction different from the first direction. The upper gate structure covers the auxiliary gate structure and the floating gate, wherein at least one first uppermost edge of the floating gate is embedded in the upper gate structure. A portion of the upper gate structure extends beyond the second sidewall of the floating gate in the second direction, and the portion of the upper gate structure is disposed on the substrate.

Description

NVM

technical field

The present invention relates to a semiconductor element. More specifically, the present invention relates to non-volatile memory elements.

Background technique

Non-volatile memory has been widely used in personal computers and electronic devices because non-volatile memory can perform operations such as storing, reading, and erasing data repeatedly, and the stored data will not be lost after the non-volatile memory is turned off.

The existing non-volatile memory has a stacked gate structure, including a tunneling oxide layer, a floating gate, a coupling dielectric layer and a control gate sequentially disposed on a substrate. When programming or erasing the flash memory device, appropriate voltages are applied to the source region, the drain region, and the control gate, respectively, so that electrons are injected into the floating gate, or electrons are pulled out of the floating gate.

In the programming and erasing operations of non-volatile memory, a larger gate-coupling ratio (GCR) between the floating gate and the control gate usually means that the operating voltage required for operation is lower, thus significantly improving the operating speed and efficiency of the flash memory. However, during programming or erasing operations, electrons must flow through the tunnel oxide layer disposed under the floating gate to be injected into or taken out from the floating gate. This process usually causes damage to the structure of the tunnel oxide layer, thereby reducing the reliability of the memory device.

In order to improve the reliability of the memory device, an erase gate can be used and integrated into the memory device. By applying a positive voltage to the erase gate, the erase gate can pull electrons out of the floating gate. Therefore, since the electrons in the floating gate flow through the tunnel oxide layer disposed on the floating gate and are pulled out instead of flowing through the tunnel oxide layer disposed under the floating gate, the reliability of the memory element is further improved.

However, even though the incorporation of erase gates into memory devices has been successful in improving the reliability of the memory devices, misalignment of the erase gates often results in significant variations in the coupling ratio between the erase gates and the underlying floating gates, which increases the variation in required erase voltages and thus degrades the electrical consistency between memory devices.

As the demand for high-efficiency memory devices increases, there remains a need to provide an improved memory device that can efficiently erase stored data.

Contents of the invention

It is an object of the present invention to provide a non-volatile memory device capable of effectively erasing stored data with improved electrical consistency.

According to some embodiments of the present invention, a non-volatile memory element is provided. The non-volatile memory element includes at least one memory unit, and the at least one memory unit includes a substrate, an auxiliary gate structure, a tunnel dielectric layer, a floating gate and an upper gate structure. The auxiliary gate structure is disposed on the substrate and includes a gate dielectric layer. The tunnel dielectric layer is disposed on the substrate on one side of the auxiliary gate structure. The floating gate is disposed on the tunnel dielectric layer and includes two first uppermost edges, two first sidewalls and two second sidewalls. The two first uppermost edges are opposite to each other and arranged along the first direction. The two first side walls are opposite to each other and arranged along the first direction, and the two first side walls are respectively connected to the two first uppermost edges. The two second sidewalls are opposite to each other and arranged along a second direction different from the first direction. The upper gate structure covers the auxiliary gate structure and the floating gate, and at least a first uppermost edge of the floating gate is embedded in the upper gate structure. A portion of the upper gate structure extends in the second direction beyond two second sidewalls of the floating gate, and the portion of the upper gate structure is disposed on the substrate.

By using a non-volatile memory device according to an embodiment of the present invention, even if an alignment misalignment occurs between the upper gate structure and the underlying floating gate, the variation in the required voltage applied to the upper gate structure, such as the change in the erase voltage, is reduced or even negligible.

In order to make the above-mentioned features and advantages of the present invention easier to understand, the embodiments are described in detail below in conjunction with the drawings.

The above and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the drawings.

Description of drawings

The following drawings are intended to make the present invention easier to understand, and are incorporated in and constitute a part of the specification. The drawings illustrate embodiments of the invention and, together with the description, illustrate the principle of operation of the invention.

FIG. 1 is a schematic top view of a non-volatile memory device according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of some embodiments of the present invention, wherein the upper gate structure covers the floating gate and the intermediate structure.

FIG. 3 is an enlarged cross-sectional view of the region R1 of the non-volatile memory device shown in FIG. 2 according to some embodiments of the present invention.

4 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of FIG. 1 according to other embodiments of the present invention, wherein the top dielectric layer covers the floating gate.

FIG. 5 is an enlarged cross-sectional view of the region R2 of the non-volatile memory device shown in FIG. 4 according to some embodiments of the present invention.

6 is a cross-sectional schematic diagram of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of other embodiments of the present invention, wherein the floating gate is an L-type floating gate.

FIG. 7 is an enlarged cross-sectional view of the region R3 of the non-volatile memory device shown in FIG. 6 according to some embodiments of the present invention.

FIG. 8 is a schematic top view of a non-volatile memory device according to another embodiment of the present invention.

9 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of some other embodiments of the present invention, wherein the source region is exposed from the intermediate structure.

FIG. 10 is an enlarged cross-sectional view of some other embodiments of the present invention, such as the region R4 of the non-volatile memory element shown in FIG. 9 .

11 to 14 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 1 to 3 according to some embodiments of the present invention.

15-17 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 4-5 according to some embodiments of the present invention.

FIGS. 18-19 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device shown in FIGS. 1-3 according to some other embodiments of the present invention.

20-21 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device shown in FIGS. 4-5 according to some other embodiments of the present invention.

22-26 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 6-7 according to some embodiments of the present invention.

27-30 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 8-10 according to some embodiments of the present invention.

Description of reference numerals: 102-isolating structure; 110-first memory area; 112-second memory area; 114-third memory area; 116-fourth memory area; 200-substrate; 202-gate dielectric layer; 204-auxiliary gate; 206-insulating layer; 6-dielectric layer; 218-tunnel dielectric layer; 220a-patterned conductive layer; 220a_2-sidewall; 220b-patterned conductive layer; 220b_0-top surface; 220b_1-inner surface; 220b_2-outer surface; 220b_3-sidewall; 4a-floating gate; 224a_0-top; 224a_1-sidewall; 224a_2-sidewall; 224b-floating gate; 224b_1-vertical part; 224b_2-horizontal part; 225_0-top; 225_1-inner surface; Gate; 235_0-top surface; 236-upper gate structure; 238-thin dielectric layer; 239-intermediate layer; 239_0-top surface; 240-intermediate structure; 240a-intermediate structure; 240b-intermediate structure; 70b_1-lower layer; 270b_2-upper layer; 272a-spacer; 272b-spacer; R1-region; R2-region; R3-region; R4-region; X-direction; Y-direction; Z-direction.

Detailed ways

The invention provides several different embodiments that can be used to implement the different features of the invention. Examples of specific components and arrangements are also described herein for simplicity of description. These examples are provided for the purpose of illustration only, without any limitation. For example, the following description of "the first feature is formed on or above the second feature" may refer to "the first feature is in direct contact with the second feature", or may refer to "other features exist between the first feature and the second feature", so that the first feature is not in direct contact with the second feature. In addition, the various embodiments of the present invention may use repeated reference signs and/or text notations. The use of these repeated reference signs and notations is to make the description more concise and clear, but not to indicate the relationship between different embodiments and/or configurations.

In addition, for the space-related descriptive words mentioned in the present invention, such as: "below", "lower", "lower", "above", "above", "under", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawing. In addition to the orientations shown in the drawings, these space-related terms are also used to describe possible orientations of semiconductor devices during use and operation. Depending on the orientation of the semiconductor device (rotated by 90 degrees or other orientations), the spatially relative descriptions used to describe its orientation should be interpreted in a similar manner.

Although the invention of the present invention is described below through specific embodiments, the inventive principle of the present invention is defined by the claims, and thus can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details have been omitted, and such omitted details belong to the knowledge of those having ordinary skill in the art.

FIG. 1 is a schematic top view of a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the non-volatile memory element may be a NOR flash memory element, which includes at least one memory unit, such as four memory units accommodated in a first memory area 110, a second memory area 112, a third memory area 114, and a fourth memory area 116, respectively. The structures in the first memory area 110 and the second memory area 112 are mirror images of each other, and the structures in the third memory area 114 and the fourth memory area 116 are mirror images of each other. According to an embodiment of the present invention, the non-volatile memory device includes more than four memory cells, and the memory cells can be arranged in an array with many rows and columns.

Referring to FIG. 1 , a non-volatile memory element includes a substrate 200 and an isolation structure 102 . The substrate 200 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The isolation structure 102 can be made of insulating material and is used to define the active area of the memory cell.

Each memory cell includes a source region 222 and a drain region 242 disposed in an active region defined by the isolation structure 102 . The source region 222 and the drain region 242 may be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 242 is different from that of the substrate 200 or the conductivity type of a doped well (not shown) accommodating the source region 222 and the drain region 242 . The source region 222 may be disposed on one side of the active region, and the drain region 242 may be disposed on the other side of the active region. According to some embodiments of the present invention, the source region 222 is a continuous region extending along the Y direction and shared by memory cells in the same row.

Each memory cell may further include a stack structure disposed on the substrate 200 and adjacent to the drain region 242 . The stack structure can extend along the Y direction and be shared by memory cells in the same row. The stack structure includes the auxiliary gate 204 , the insulating layer 206 and the upper gate structure 236 , which are sequentially stacked upward along the Z direction. The auxiliary gate 204 may be composed of a conductive material such as polysilicon or metal, and may serve as a word line configured to turn on/off a channel region of memory cells disposed in the same row.

A layer of isolation material 212 may be disposed on sidewalls of the auxiliary gate 204 and the insulating layer 206 to insulate the auxiliary gate 204 from other conductive components. The isolation material layer 212 may be a single-layer, double-layer or multi-layer spacer disposed on each sidewall of the auxiliary gate 204, but is not limited thereto.

Each memory cell also includes a floating gate 224 disposed on the substrate 200 adjacent to the source region 222 . Therefore, the floating gate 224 is disposed on one side of the auxiliary gate 204 , and the drain region 242 is disposed on the other side of the auxiliary gate 204 . The floating gate 224 is made of conductive material, such as polysilicon or other semiconductors. The floating gates 224 are separated from each other such that current cannot be transferred directly between the floating gates 224 . Since the floating gates 224 are separated from each other, each floating gate 224 can be programmed or erased independently, thereby determining the state of each memory cell, such as state "1" or state "0".

The intermediate structure 240 is disposed in the gap between adjacent floating gates 224 to surround the floating gates 224 . According to different requirements, the intermediate structure 240 may include an insulating structure configured to prevent leakage current between adjacent floating gates 224, or the intermediate structure 240 may include a control gate structure configured to inject hot carriers (such as electrons) from the channel into the floating gate 224.

2 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of some embodiments of the present invention, wherein the upper gate structure covers the floating gate and the intermediate structure. Referring to the section AA' of FIG. 2 , the drain regions 242 are disposed in the first memory area 110 and the second memory area 112, respectively. The source area 222 is disposed at the boundary of the first memory area 110 and the second memory area 112 .

For the memory cells in the first memory area 110 , the gate dielectric layer 202 is disposed between the substrate 200 and the auxiliary gate 204 . By biasing the auxiliary gate 204 with a predetermined voltage, the carrier channel under the gate dielectric layer 202 can be turned on/off. An insulating layer 206 may be selectively disposed between the auxiliary gate 204 and the upper gate structure 236 to prevent leakage current therebetween.

The upper gate structure 236 includes an upper gate dielectric layer 234 and an upper gate 235 stacked in sequence. The composition of the upper gate dielectric layer 234 is a dielectric layer, which can allow electrons to pass through through the F-N tunneling mechanism (Fowler-Nordheim tunneling mechanism). The upper gate 235 may be made of conductive material, such as polysilicon or metal. The top surface of the upper gate structure 236 (corresponding to the top surface 235_0 of the upper gate 235 ) is higher than the top surface of the floating gate 224a. In addition, the upper gate structure 236 can further extend toward the auxiliary gate 204 , so a part of the upper gate structure 236 can extend beyond the sidewall of the auxiliary gate 204 to cover the top surface 224a_0 of the floating gate 224a.

The floating gate 224a includes two opposite first sidewalls 224a_1 disposed along the X direction. The first sidewall 224a_1 may be a vertical or inclined sidewall instead of a curved surface. The top surface 224a_0 of the floating gate 224a is a flat or slightly inclined surface instead of a curved surface. It should be noted that the floating gate 224a shown in FIG. 2 may be a rectangular floating gate because the outline of the floating gate 224a in section AA' resembles a rectangle.

The tunnel dielectric layer 218 is disposed on the substrate 200 and at least between the substrate 200 and the floating gate 224a. The material of the tunneling dielectric layer 218 is, for example, silicon oxide or other layers that allow hot electrons in the carrier channel to pass through.

As mentioned above, the intermediate structure 240a may include an insulating structure, such as an intermediate base structure, or the intermediate structure 240b may include a control gate structure, such as a control gate structure (the control gate structure may cover the sidewalls 224a_1, 224a_2 of the floating gate 224a to provide additional coupling to the floating gate). An intermediate structure 240 a , 240 b (eg, an intermediate base structure or a control gate structure) includes a thin dielectric layer 238 and an intermediate layer 239 . The thin dielectric layer 238 is disposed on the first sidewall 224a_1 of the floating gates 224a, and the intermediate layer 239 is disposed in the gap between adjacent floating gates 224a. According to some embodiments of the invention, the top surface 239_0 of the intermediate layer 239 of the intermediate structures 240a, 240b is lower than the top surface 224a_0 of the floating gate 224a.

According to different requirements, the upper gate structure 236 may serve as an erase gate structure configured to pull electrons out of the floating gate 224a through the uppermost corner and/or uppermost edge of the floating gate 224a, or not only as an erase gate structure, but also as a control gate structure configured to attract hot carriers from the carrier channel into the floating gate 224a. On the one hand, when the intermediate structure 240b is configured as a control gate structure, the upper gate structure 236 may only serve as an erase gate structure instead of a control gate structure. On the other hand, when the intermediate structure 240a is configured as an insulating structure, the upper gate structure 236 may serve as an erase gate structure and a control gate structure.

Referring to section BB' of FIG. 2 , auxiliary gate 204 , upper gate structure 236 and intermediate structures 240 a , 240 b (eg, intermediate base structures or control gate structures) are also disposed on isolation structure 102 . A portion of the intermediate structure 240 a , 240 b may be disposed between the upper gate structure 236 extending from the sidewall of the auxiliary gate 204 and the isolation structure 102 , or the portion of the intermediate structure may be disposed between the upper gate structure 236 and the substrate 200 .

Referring to section CC' of FIG. 2 , the floating gate 224a includes two opposite second sidewalls 224a_2 disposed along the Y direction. The second sidewall 224a_2 may be a vertical or inclined sidewall. The upper portion of the second sidewall 224a_2 of the floating gate 224a may be covered by the upper gate structure 236, and the lower portion of the second sidewall 224a_2 of the floating gate 224 may be covered by intermediate structures 240a, 240b (eg, intermediate base structures or control gate structures). According to some embodiments of the present invention, 60% to 95% of the surface area of each second sidewall 224a_2 is covered by the intermediate layer 239, so the contact area between the upper gate structure 236 and the second sidewall 224a_2 is relatively small. In addition, the bottom surface of the upper gate structure 236 extending beyond the second sidewall 224a_2 of the floating gate 224 can be separated from the isolation structure 102 , the tunneling dielectric layer 218 and the substrate 200 due to the existence of the intermediate structures 240a, 240b.

According to some embodiments of the present invention, the non-volatile memory element may also include other components, such as via holes, bit lines, interlayer dielectrics, etc., and the structure shown in FIG. 2 may be further modified according to actual needs.

FIG. 3 is an enlarged cross-sectional view of the region R1 of the non-volatile memory device shown in FIG. 2 according to some embodiments of the present invention. Referring to FIG. 3 , the floating gate 224a includes two first uppermost edges 226a_1 that are opposite to each other and disposed along a first direction (eg, X direction). By applying a bias voltage on the upper gate structure 236 , most of the electrons stored in the floating gate 224 a can be pulled out through the first uppermost edge 226 a_1 embedded in the upper gate structure 236 . The first sidewalls 224a_1 of the floating gate 224a are disposed along a first direction such as the X direction, and the first sidewalls 224a_1 are respectively connected to the first uppermost edges 226a_1. The second sidewall (not shown) of the floating gate 224a is disposed along the second direction (for example, the Y direction), and it is covered by a dielectric interlayer 239 made of a dielectric material, or covered by a conductive interlayer 239 as a control gate (ie, a coupling gate). Since 65% to 95% of the second sidewall (that is, the sidewall perpendicular to the Y direction) is covered by the intermediate layer 239, and the two first uppermost edges 226a_1 are higher than the lowest bottom surface of the upper gate 235, even if there is an alignment deviation between the upper gate 235 and the floating gate 224a, the coupling ratio between the upper gate structure 236 and the floating gate 224a below it will not change significantly. Therefore, electrical consistency among nonvolatile memory elements can be improved.

In the following paragraphs, other embodiments of the invention are further described, and for the sake of brevity, only the main differences between the embodiments are described.

4 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of FIG. 1 according to other embodiments of the present invention, wherein the top dielectric layer covers the floating gate. Referring to section AA' of FIG. 4 , the structure shown in FIG. 4 is similar to the structure shown in FIG. 2 , the main difference is that the top dielectric layer 260 is further disposed on the top surface 224a_0 of the floating gate 224a. In the section AA' of FIG. 4 , the top dielectric layer 260 does not extend beyond the first sidewall 224a_1 of the floating gate 224a. In the section CC' of FIG. 4 , the top dielectric layer 260 also does not extend beyond the second sidewall 224a_2 of the floating gate 224a.

FIG. 5 is an enlarged cross-sectional view of the region R2 of the non-volatile memory device shown in FIG. 4 according to some embodiments of the present invention. Referring to FIG. 5 , the first uppermost edges 226a_1 of the floating gates 224a are not covered by the top dielectric layer 260 such that at least one of the first uppermost edges 226a_1 of the floating gates 224a can still be in direct contact with the upper gate structure 236 . In other words, from a plan view, the area of the top surface 260_0 of the top dielectric layer 260 is smaller than the area of the top surface 224a_0 of the floating gate 224a. Due to the existence of the top dielectric layer 260 , a portion of the upper gate structure 236 disposed on the floating gate 224 a is disposed away from the top surface 224 a_0 of the floating gate 224 a. Therefore, the coupling ratio caused by the gate structure 236 disposed on the top dielectric layer 260 can be reduced, thereby improving the electrical consistency between the non-volatile memory elements.

6 is a cross-sectional schematic diagram of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of other embodiments of the present invention, wherein the floating gate is an L-type floating gate. Referring to section AA' of FIG. 6, the structure shown in FIG. 6 is similar to the structure shown in FIG. 2, the main difference is that the floating gate 224b is an L-shaped floating gate including a vertical portion 224b_1 and a horizontal portion 224b_2. The vertical portion 224b_1 and the horizontal portion 224b_2 may have substantially the same thickness and composition. The top surface 225_0 of the vertical portion 224b_1 is higher than the top surface of the intermediate structure 240a, 240b (ie, the intermediate base structure or the control gate structure), or is higher than the top surface 239_0 of the intermediate layer 239 . The horizontal portion 224b_2 is covered by the middle layer 239 .

FIG. 7 is an enlarged cross-sectional view of the region R3 of the non-volatile memory device shown in FIG. 6 according to some embodiments of the present invention. Referring to FIG. 7, the floating gate 224b includes an inner surface 225_1 and an outer surface 225_2 opposite to the inner surface 225_1. The outer surface 225_2 faces the intermediate structures 240a, 240b. The vertical portion 224b_1 of the floating gate 224b includes a top surface 225_0 and two opposite first uppermost edges 226a_1 disposed along a first direction (eg, X direction). The width of the top surface 225_0 in the X direction is 1/20 to 1/3 of the width of the bottom surface of the floating gate 224b. One or both of the first uppermost edges 226a_1 may be covered by the upper gate structure 236 . Because the width of the top surface 225_0 in the X direction is much smaller than the width of the bottom surface of the floating gate 224b, and 65% to 95% of the second sidewall (ie, the sidewall perpendicular to the Y direction) of the floating gate 224b is covered by the intermediate layer 239, so even if there is an alignment deviation between the upper gate 235 and the floating gate 224b, the coupling ratio between the upper gate structure 236 and the lower floating gate 224b will not change significantly. Therefore, electrical consistency among nonvolatile memory elements can be improved.

FIG. 8 is a schematic top view of a non-volatile memory device according to another embodiment of the present invention. Referring to FIG. 8, the structure shown in FIG. 8 is similar to the structure shown in FIG. 1, the main difference is that the floating gate 224 is an L-shaped floating gate instead of a rectangular floating gate along the section line AA', and the source region 222 of the non-volatile memory element is not covered by the intermediate structure 240. Therefore, the intermediate structure 240 in the first memory area 110 is separated from the intermediate structure 240 in the second memory area 112 , and the intermediate structure 240 in the third memory area 114 is separated from the intermediate structure 240 in the fourth memory area 116 .

9 is a schematic cross-sectional view of a non-volatile memory element corresponding to the section line A-A', section line B-B' and section line C-C' of some other embodiments of the present invention, wherein the source region is exposed from the intermediate structure. Referring to section AA' of FIG. 9 , the floating gate 224b is an L-shaped floating gate similar to the floating gate 224b shown in FIG. 6 . The top surface of the horizontal portion 224b_2 of the floating gate 224b is covered by the intermediate structures 240a, 240b, and the end of the horizontal portion 224b_2 is away from the floating gate 224b, the end being exposed from the intermediate structures 240a, 240b. Furthermore, the intermediate structures 240a, 240b have curved surfaces.

Referring to section BB' of FIG. 9 , a portion of the upper gate structure 236 covers the curved surfaces of the intermediate structures 240a, 240b and thus has a curved bottom surface.

FIG. 10 is an enlarged cross-sectional view of some other embodiments of the present invention, such as the region R4 of the non-volatile memory element shown in FIG. 9 . Referring to FIG. 10 , similar to the structure shown in FIG. 7 , the vertical portion 224b_1 of the floating gate 224b includes a top surface 225_0 and two opposite first uppermost edges 226a_1 disposed along a first direction (eg, X direction). The width of the top surface 225_0 in the X direction is 1/20 to 1/3 of the width of the bottom surface of the floating gate 224b. One or both of the first uppermost edges 226a_1 may be covered by the upper gate structure 236 . In addition, the intermediate structures 240a, 240b not only cover the outer surface 225_2 of the floating gate 224b, but also cover the second sidewalls (not shown) of the floating gate 224b arranged along the Y direction. According to some embodiments of the present invention, the uppermost vertices of the intermediate structures 240a, 240b and the top surface 225_0 of the floating gate 224b may be substantially at the same height. Because the width of the top surface 225_0 in the X direction is much smaller than the width of the bottom surface of the floating gate 224b, and more than 95% of the outer surface 225_2 and more than 95% of the second sidewall (ie, the sidewall perpendicular to the Y direction) of the floating gate 224b are covered by the intermediate structures 240a and 240b, so even if there is an alignment deviation between the upper gate 235 and the floating gate 224b, the upper gate structure 236 and the floating gate below it The coupling ratio between 224b also does not change significantly. Therefore, electrical consistency among nonvolatile memory elements can be improved.

11 to 14 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 1 to 3 according to some embodiments of the present invention. In Fig. 11 to Fig. 14, the section AA', the section BB' and the section CC' respectively correspond to the section line A-A', the section line B-B' and the section line C-C' of Fig. 1 .

Referring to section AA', section BB' and section CC' of FIG. 11, the structure formed at this manufacturing stage includes at least a substrate 200, at least one stack structure 210, an isolation material layer 212, a tunneling dielectric layer 218 and a patterned conductive layer 220a.

According to some embodiments of the present invention, the substrate 200 may be a semiconductor substrate with a suitable conductivity type, such as p-type or n-type. The composition of the substrate 200 may include silicon, germanium, gallium nitride or other suitable semiconductor materials, but is not limited thereto.

At least one stack structure 210 is on the substrate 200 . For example, two stack structures 210 are disposed on the substrate 200 and laterally spaced from each other. Each stack structure 210 includes a gate dielectric layer 202 , an auxiliary gate 204 , an insulating layer 206 and a sacrificial layer 208 stacked in sequence. Each stack structure 210 includes a first sidewall 211 and a second sidewall 213 , and the first sidewalls 211 of the stack structures 210 face each other. The auxiliary gate 204 is made of conductive material, and the auxiliary gate 204 is configured such that when an appropriate voltage is applied, the auxiliary gate 204 will open/close the carrier channel in the substrate 200 under the auxiliary gate 204 . The insulating layer 206 is made of insulating material, such as silicon oxide or silicon oxynitride, but not limited thereto, and is used to electrically isolate the auxiliary gate 204 from various layers disposed on the auxiliary gate 204 . The sacrificial layer 208 is the uppermost layer in the stack structure 210 , which is a temporary layer configured to be removed before a subsequent process of forming a gate structure (eg, an upper gate structure) on the auxiliary gate 204 .

The isolation material layer 212 is formed on the sidewalls 211 , 213 of the stack structure 210 . The material of the isolation material layer 212 is, for example, silicon oxide/silicon nitride/silicon oxide or silicon nitride/silicon oxide. The method for forming the isolation material layer 212 includes, for example, firstly forming a dielectric layer 214 and a dielectric layer 216 covering each stack structure 210 on the substrate 200 sequentially, and then removing part of the dielectric layer 214 and the dielectric layer 216 to form the isolation material layer 212 on the sidewall of each stack structure 210. The material of the dielectric layer 214 is, for example, silicon nitride, and the material of the dielectric layer 216 is, for example, silicon oxide. The dielectric layer 214 and the dielectric layer 216 are formed by chemical vapor deposition, for example. The method for removing part of the dielectric layer 214 and the dielectric layer 216 is, for example, anisotropic etching.

The tunnel dielectric layer 218 is formed on the substrate 200 at least between the stack structures 210 , or further formed on the substrate 200 on both sides of the stack structures 210 . The material of the tunneling dielectric layer 218 is, for example, silicon oxide, or other layers that allow hot electrons to penetrate through the tunneling effect. The forming method of the tunneling dielectric layer 218 is, for example, a thermal oxidation method or a deposition method, but not limited thereto.

Referring to section AA' of FIG. The method of forming the patterned conductive layer 220a may include the following steps. First, a conductive layer (not shown) is formed on the substrate 200 , and the material of the conductive layer is, for example, doped polysilicon, polysilicon or other suitable conductive materials. When the material of the conductive layer is doped polysilicon, the forming method includes, for example, performing an ion implantation step after forming the undoped polysilicon layer by chemical vapor deposition; or performing chemical vapor deposition by using an in-situ dopant implantation method. Then, an etching process, such as an anisotropic etching process or an etch-back process, is performed to etch the conductive layer. Therefore, the conductive layer can be patterned to form a plurality of conductive blocks (not shown) arranged along the X direction. At this stage of fabrication, the conductive blocks cover the sidewalls 211 and 213 of each stacked structure 210 . Then, the conductive blocks disposed adjacent to the sidewalls 213 of the stacked structure 210 are removed through lithography and etching processes. In this way, only the patterned conductive layer 220 a disposed on the first sidewall 211 of the stack structure 210 remains. In addition, for the patterned conductive layer 220 a disposed on the first sidewall 211 of the stack structure 210 , the patterned conductive layer 220 a may have a rectangular outline from a top view. The height of the patterned conductive layer 220a can be appropriately controlled by performing an etch-back process.

Referring to section BB' of FIG. 11 , the patterned conductive layer does not exist in a predetermined region on the substrate 200. Referring to FIG. Referring to section CC' of FIG. 11 , the patterned conductive layer 220a may have vertical or inclined sidewalls 220a_2.

12 is a schematic cross-sectional view of some embodiments of the present invention at a fabrication stage following FIG. 11 , wherein spacers are formed on the patterned conductive layer. After the structure shown in FIG. 11 is fabricated, a plurality of spacers 262 composed of a dielectric material are formed to cover the top surface of the patterned conductive layer 220 a and the sidewalls 211 , 213 of the stacked structure 210 .

Figure 13 is a schematic cross-sectional view of some embodiments of the present invention at a fabrication stage subsequent to Figure 12, which forms a floating gate. After the structure shown in FIG. 12 is fabricated, an etch process is performed on the patterned conductive layer using the spacer 262 as an etch mask. Therefore, the patterned conductive layer is further patterned to form a plurality of floating gates 224 a adjacent to the first sidewall 211 of the stack structure 210 . Afterwards, a source region 222 is formed in the substrate 200 between two adjacent floating gates 224a. A method of forming the source region 222 includes, for example, performing an ion implantation process using the spacer 262 as an etch mask. According to the requirements of the device, the implanted dopant can be n-type or p-type dopant. The source region 222 can be considered a shared source region because the source region 222 is shared by two adjacent memory cells. Afterwards, the spacer 262 may be peeled off.

14 is a schematic cross-sectional view of some embodiments of the present invention at a fabrication stage subsequent to FIG. 13 , where an intermediate structure is formed in the gap between two adjacent floating gates. After the structure shown in Figure 13 is fabricated, referring to section AA' of Figure 14, intermediate structures 240a, 240b may be formed in the gap between two adjacent floating gates 224a. The intermediate structure 240 a , 240 b includes a thin dielectric layer 238 and an intermediate layer 239 . The thin dielectric layer 238 is disposed on the first sidewall 224a_1 of the floating gates 224a, and the intermediate layer 239 is disposed in the gap between adjacent floating gates 224a. The thickness of the thin dielectric layer 238 (ie, in the X direction) is less than the thickness of the intermediate layer 239 (ie, in the Z direction). For example, the thickness ratio of the thin dielectric layer 238 and the intermediate layer 239 is 0.01 to 0.2. According to some embodiments of the invention, the top surfaces of the intermediate structures 240a, 240b are lower than the top surface 224a_0 of the floating gate 224a.

Referring to section CC' of FIG. 14 , the floating gate 224a includes two opposite second sidewalls 224a_2 disposed along the Y direction. Each second sidewall 224a_2 may be a vertical or inclined sidewall. The upper portion of the second sidewall 224a_2 of the floating gate 224a may be covered by a subsequently formed upper gate structure, and the lower portion of the second sidewall 224a_2 of the floating gate 224 may be covered by intermediate structures 240a, 240b (eg, intermediate base structures or control gate structures). According to some embodiments of the present invention, 60% to 95% of the surface area of each second sidewall 224a_2 is covered by the intermediate layer 239, so the contact area between the subsequently formed upper gate structure and the second sidewall 224a_2 is small. In addition, due to the existence of the intermediate structure 240 , the bottom surface of the upper gate structure 236 extending beyond the second sidewall 224 a_2 of the floating gate 224 may be separated from the isolation structure 102 , the tunneling dielectric layer 218 and the substrate 200 .

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structures shown in FIGS. 1 to 3 .

15-17 are cross-sectional views of various stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 4-5 according to some embodiments of the present invention. In Figs. 15 to 17, the section AA', the section BB' and the section CC' correspond to the section line A-A', the section line B-B' and the section line C-C' of Fig. 1, respectively. In addition, since the manufacturing process of the embodiment shown in FIGS. 15 to 17 is similar to that of the embodiment shown in FIGS. 11 to 14 , only the main differences between the embodiments are described for the sake of brevity.

Referring to section AA', section BB' and section CC' of Figure 15, the structure formed at this stage of fabrication is similar to the structure shown in Figure 11, the main difference being that the top dielectric layer 260 is disposed on the patterned conductive layer 220a. Since the top dielectric layer 260 is formed after the overall deposition of the conductive layer as shown in FIG. 11 and before patterning the conductive layer to form conductive blocks (not shown), the sidewalls of the patterned conductive layer 220 a are not covered by the top dielectric layer 260 . The thickness of the top dielectric layer 260 is 1/3 to 1/10 of the thickness of the patterned conductive layer 220a.

16 is a schematic cross-sectional view of some embodiments of the present invention at a fabrication stage following FIG. 15 , wherein spacers are formed on the patterned conductive layer. After the structure shown in FIG. 15 is fabricated, a plurality of spacers 262 composed of a dielectric material are formed to cover the top surface of the top dielectric layer 260 and the sidewalls 211 , 213 of the stack structure 210 .

Referring to section AA', section BB' and section CC' of FIG. 17, the structure formed at this stage of fabrication is similar to that shown in FIG. Then, the spacer 262 may be stripped away. After that, the upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structures shown in FIGS. 4 to 5 .

FIGS. 18-19 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device shown in FIGS. 1-3 according to some other embodiments of the present invention. The manufacturing process shown in FIGS. 18 to 19 is similar to the manufacturing process shown in FIGS. 11 to 14 , and for the sake of brevity, only the main differences between the embodiments are described.

Referring to section AA', section BB' and section CC' of FIG. 18, the structure formed at this manufacturing stage is similar to the structure shown in FIG. Due to the presence of the additional stack structure 210 , the additional stack structure 210 may be used to prevent the patterned conductive layer 220 a from being formed in a region already occupied by the additional stack structure 210 .

FIG. 19 is a schematic cross-sectional view of some other embodiments of the present invention at a manufacturing stage subsequent to FIG. 18 . After manufacturing the structure shown in FIG. 18 , the patterned conductive layer disposed on the second sidewall 213 of the stacked structure 210 is stripped, thereby forming the floating gate 224 a.

Thereafter, intermediate structures 240a, 240b shown in FIG. 2 may be fabricated to replace the additional stack structure 210 disposed between two adjacent floating gates 224a. Then, an upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structure shown in FIGS. 1 to 3 .

20-21 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device shown in FIGS. 4-5 according to some other embodiments of the present invention. The manufacturing process shown in FIGS. 20 to 21 is similar to that shown in FIGS. 18 to 19 , and for the sake of brevity, only the main differences between the embodiments are described.

Referring to section AA', section BB' and section CC' of Figure 20, the structure formed at this stage of fabrication is similar to that shown in Figure 18, the main difference being that the top dielectric layer 260 is disposed on the patterned conductive layer 220a. The sidewalls of the patterned conductive layer 220 a are not covered by the top dielectric layer 260 because the top dielectric layer 260 is formed after the overall deposition of the conductive layer (not shown) and before patterning the conductive layer to form conductive blocks (not shown). The thickness of the top dielectric layer 260 is 1/3 to 1/10 of the thickness of the patterned conductive layer 220a.

FIG. 21 is a schematic cross-sectional view of some embodiments of the present invention at a fabrication stage subsequent to FIG. 20 . After manufacturing the structure shown in FIG. 20 , the patterned conductive layer 220 a disposed on the second sidewall 213 of the stacked structure 210 is stripped, thereby forming a floating gate 224 a.

Afterwards, the additional stack structure 210 may be replaced by the intermediate structures 240a, 240b shown in FIG. 4 . Then, an upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structure shown in FIGS. 4-5 .

22-26 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 6-7 according to some embodiments of the present invention. In Fig. 22 to Fig. 26, the section AA', the section BB' and the section CC' correspond to the section line A-A', the section line B-B' and the section line C-C' of Fig. 1, respectively. Furthermore, the manufacturing process shown in FIGS. 22 to 26 can be considered as derived from the manufacturing process shown in FIGS. 11 to 14 , and for the sake of brevity, only the main differences between the embodiments are described.

Referring to the section AA', the section BB' and the section CC' of FIG. 22, a plurality of patterned conductive layers 220b are formed on the substrate 200. In the section AA' of FIG. 22 , the patterned conductive layer 220b is a continuous layer extending along the X direction and covering the stacked structure 210 . The patterned conductive layer 220b includes opposite inner surfaces 220b_1 and outer surfaces 220b_2. In section BB' of Figure 22, there is no patterned conductive layer 220b. Therefore, from a top view, as shown in FIG. 8 , each patterned conductive layer 220 b is strip-shaped and extends in the X direction, and the patterned conductive layers 220 b are separated from each other along the Y direction. Then, after the patterned conductive layer 220b is formed, blanket deposition is performed to form a conformal layer 270a covering the patterned conductive layer 220b and the substrate 200 . In section CC' of Fig. 22, the sidewall 220b_3 of the patterned conductive layer 220b is covered by the conformal layer 270a.

Then, referring to the section AA', the section BB' and the section CC' of FIG. In section CC' of FIG. 22 , the sidewalls of the patterned conductive layer 220b are covered by spacers 272a. The spacer 272a in this embodiment can be formed without performing any lithography process.

Afterwards, referring to section AA' of FIG. 24 , the patterned conductive layer is etched using the spacer 272a as an etching mask, thereby forming an L-shaped patterned conductive layer on the sidewalls 211, 213 of the stacked structure 210. Each L-shaped patterned conductive layer includes a vertical portion 221_1 and a horizontal portion 221_2 . By using the spacer 272a as an etching mask, no additional lithography process is required to define the contour of the L-shaped patterned conductive layer. Then, a source region 222 is formed in the substrate 200 , and the source region 222 is disposed between two adjacent spacers 272 a on the first sidewall 211 of the stack structure 210 .

Afterwards, referring to the section AA', the section BB', and the section CC' of FIG. 25, the spacer and the sacrificial layer are stripped. In this way, the top surface 220b_0 of the vertical portion 221_1 of the patterned conductive layer 220b can protrude from the top surface of the remaining stacked structure 210 . In addition, in the section CC' of FIG. 25 , the sidewall 220b_3 of the patterned conductive layer 220b is exposed.

After that, referring to the section AA', the section BB' and the section CC' of FIG. 26, the patterned conductive layer disposed adjacent to the second sidewall 213 of the stack structure 210 is etched by performing lithography and etching processes. Therefore, the floating gate 224 b is formed on the first sidewall 211 of the stack structure 210 . Then, intermediate structures 240 a , 240 b are formed in the gap between two adjacent stacked structures 210 . In section AA' and section CC', the height of the intermediate structures 240a, 240b can be appropriately controlled to cover 65% to 95% of the sidewalls of the floating gate 224b.

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structures shown in FIGS. 6-7 .

27-30 are cross-sectional views of different stages of the manufacturing method for manufacturing the non-volatile memory device of FIGS. 8-10 according to some embodiments of the present invention. In Figs. 27 to 30, the section AA', the section BB' and the section CC' correspond to the section line A-A', the section line B-B' and the section line C-C' of Fig. 8, respectively. In addition, since the manufacturing process of the embodiment shown in FIGS. 27 to 30 is similar to that of the embodiment shown in FIGS. 22 to 26 , only the main differences between the embodiments are described for the sake of brevity.

Referring to section AA', section BB' and section CC' of Figure 27, the structure formed at this stage of fabrication is similar to the structure shown in Figure 22 with the main difference being the use of a stacked conformal layer 270b comprising a lower layer 270b_1 and an upper layer 270b_2 in place of the conformal layer 270a shown in Figure 22. According to some embodiments of the present invention, the lower layer 270b_1 is a composite dielectric layer including silicon oxide/silicon nitride/silicon oxide, but is not limited thereto. The upper layer 270b_2 is a conductive layer including polysilicon or metal, but is not limited thereto.

Then, referring to the section AA', the section BB' and the section CC' of FIG. In the section CC' of FIG. 28 , the sidewall 220b_3 of the patterned conductive layer 220b is covered by the spacer 272b. The spacer 272b in this embodiment can be formed without additional lithography process.

Afterwards, referring to section AA' of FIG. 29 , the patterned conductive layer is etched using the spacer 272b as an etching mask, thereby forming an L-shaped patterned conductive layer on the sidewalls 211, 213 of the stacked structure 210. Each L-shaped patterned conductive layer includes a vertical portion 221_1 and a horizontal portion 221_2 . By using the spacer 272b as an etching mask, no additional lithography process is required to define the contour of the L-shaped patterned conductive layer. Then, a source region 222 is formed in the substrate 200 , the source region 222 is located between two adjacent spacers 272 b on the sidewall 211 of the stack structure 210 .

Afterwards, referring to the section AA', the section BB' and the section CC' of FIG. 26, the patterned conductive layer and the spacer disposed adjacent to the second sidewall 213 of the stack structure 210 are etched by performing lithography and etching processes. Therefore, the floating gate 224 b and the intermediate structures 240 a , 240 b are formed on the first sidewall 211 of the stack structure 210 . In other words, the intermediate structures 240a, 240b are formed from the original stack conformal layer 270a, as shown in FIG. 27 . In section AA' and section CC', the height of the intermediate structures 240a, 240b can be appropriately controlled to cover 65% to 95% of the sidewalls of the floating gate 224b.

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structures shown in FIGS. 8 to 10 .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (22)

1. A non-volatile memory element, characterized in that it comprises at least one memory unit, wherein said at least one memory unit comprises: a substrate; an auxiliary gate structure disposed on the substrate and including a gate dielectric layer; a tunneling dielectric layer disposed on the substrate on one side of the auxiliary gate structure; A floating gate is arranged on the tunnel dielectric layer and includes: Two first uppermost edges are opposite to each other and arranged along a first direction; two first side walls, opposite to each other and arranged along the first direction, wherein the two first side walls are respectively connected to the two first uppermost edges; and two second sidewalls are opposite to each other and arranged along a second direction, wherein the second direction is different from the first direction; an upper gate structure covering the auxiliary gate structure and the floating gate, wherein at least one of the two first uppermost edges of the floating gate is embedded in the upper gate structure, Wherein, a portion of the upper gate structure extends in the second direction beyond the two second sidewalls of the floating gate, and the portion of the upper gate structure is disposed on the substrate. 2. The non-volatile memory device according to claim 1, wherein one of the first sidewalls of the floating gate faces the auxiliary gate structure, and the first sidewall facing the auxiliary gate structure is covered by the auxiliary gate structure. 3. The non-volatile memory device as claimed in claim 2, wherein another one of the first sidewalls is opposite to the auxiliary gate structure, and the first sidewall opposite to the auxiliary gate structure is a vertical or inclined sidewall. 4. The non-volatile memory device as claimed in claim 1, wherein the two first uppermost edges of the floating gate are higher than the top surface of the auxiliary gate structure. 5. The non-volatile memory device of claim 1, wherein the two second sidewalls are covered by an intermediate structure, wherein the intermediate structure is disposed between the portion of the upper gate structure and the substrate. 6. The non-volatile memory element according to claim 1, wherein the bottom surface of the portion of the upper gate structure disposed on the substrate is lower than the two first uppermost edges of the floating gate. 7. The non-volatile memory device according to claim 1, wherein the at least one memory cell further comprises a control gate structure, and part of the control gate structure covers the two second sidewalls of the floating gate. 8. The non-volatile memory device of claim 7, wherein the portion of the control gate structure is covered by the portion of the upper gate structure extending beyond the two second sidewalls of the floating gate. 9. The non-volatile memory device as claimed in claim 7, wherein the top surface of the control gate structure is lower than the top surface of the upper gate structure. 10. The non-volatile memory device of claim 9, wherein the top surface of the control gate structure is covered by the upper gate structure. 11. The non-volatile memory device of claim 7, wherein a top surface of the control gate structure is lower than the two first uppermost edges. 12. The non-volatile memory element according to claim 1, wherein the at least one memory cell further comprises a top dielectric layer disposed on the floating gate, wherein a top surface of the top dielectric layer is covered by the upper gate structure. 13. The non-volatile memory device as claimed in claim 12, wherein the area of the top surface of the top dielectric layer is smaller than the area of the top surface of the floating gate. 14. The non-volatile memory device according to claim 1, wherein the floating gate further comprises a vertical portion and a horizontal portion, wherein a top surface of the vertical portion is higher than a top surface of the horizontal portion. 15. The non-volatile memory device of claim 14, wherein the vertical portion of the floating gate comprises the two first uppermost edges. 16. The non-volatile memory device of claim 14, wherein said at least one memory cell further comprises a control gate structure covering said top surface of said horizontal portion of said floating gate. 17. The non-volatile memory element according to claim 1, wherein the at least one memory unit comprises a first memory unit and a second memory unit, the first memory unit and the second memory unit each include the auxiliary gate structure and the floating gate, the non-volatile memory element further comprises a source region, the source region is shared by the first memory unit and the second memory unit, and the source region is covered by the upper gate structure. 18. The non-volatile memory device of claim 17, wherein the first memory cell and the second memory cell are mirror images of each other. 19. The non-volatile memory device of claim 17, wherein the upper gate structure fills up a gap between the floating gate of the first memory unit and the floating gate of the second memory unit. 20. The non-volatile memory device of claim 17, further comprising a control gate structure shared by the first memory unit and the second memory unit, wherein the control gate structure covers the source region. 21. The non-volatile memory device according to claim 20, wherein a part of the control gate structure covers the two second sidewalls of each of the floating gates, and the part of the control gate structure is disposed between the upper gate structure and the substrate. 22. The non-volatile memory device of claim 20, further comprising an isolation structure disposed in the substrate, wherein the portion of the upper gate structure extending beyond the two second sidewalls of the floating gate is disposed on the isolation structure.