CN116470924A - A Broadband Full-Duplex Receiver with Shared Interference Cancellation Circuit - Google Patents

Abstract

The invention belongs to the technical field of radio frequency microwave integrated circuit design, in particular to a broadband full-duplex receiver sharing an interference elimination circuit. The full-duplex receiver of the present invention is composed of a receiver module and an interference elimination circuit; the receiver includes: a transconductance, a frequency mixer, a transimpedance amplifier and a frequency conversion loop; the interference elimination circuit includes an input matching network, an input down-mixer, a quadrature selection phase shifter, and a baseband variable gain low-pass filter. The interference elimination circuit transfers the delay and gain adjustment of the radio frequency domain to the baseband, so that the overall area and power consumption are small, and the delay amount of 3.86-8.33ns can be realized in the wide radio frequency band of 0.5-3.5GHz; at the same time, the elimination circuit performs up-mixing and synthesis through the mixer in the frequency conversion loop of the receiver, forming a dual-path elimination method, avoiding the elimination circuit directly connected to the front end of the receiver module, and the noise figure deterioration of the receiver module is very small, only 0.9-1.2dB.

Description

A Broadband Full-Duplex Receiver with Shared Interference Cancellation Circuit

technical field

The invention belongs to the technical field of radio frequency microwave integrated circuit design, and in particular relates to a broadband full-duplex receiver sharing an interference elimination circuit.

Background technique

With the rapid development of wireless communication standards, the data volume of wireless communication services is increasing explosively, and the wireless spectrum will become very crowded. In order to make better use of frequency bands with better propagation characteristics below Sub-6GHz, simultaneous same-frequency full-duplex communication technology has been proposed. However, although full-duplex has advantages in signal transmission performance over half-duplex, the realization of a full-duplex system is also extremely challenging. Due to the working characteristics of the full-duplex system transmitting and receiving at the same time at the same frequency, in a typical full-duplex transceiver system, the filtering of self-interference signals cannot be filtered out by low-pass filters or band-pass filters like the channel selection method at the front end of the receiver. This also makes the application of self-interference cancellation technology in full-duplex systems inevitable.

With the development of chip-level full-duplex receivers, some difficult problems have emerged. First of all, the design of the cancellation circuit in the full-duplex system is gradually becoming more difficult. It is required that the design should be able to simulate the transmission characteristics of the signal in the channel as completely as possible, so that the leaked interference signal of the transmitter can be completely eliminated after reconstruction. But at the same time, the on-chip cancellation circuit should be kept as adjustable as possible, and there are higher requirements for the precision, range and method of the cancellation circuit adjustment (amplitude, phase, delay). Secondly, the design of the self-interference cancellation circuit requires that while ensuring the depth of cancellation, it can have as little impact on the receiver front end itself as possible (mainly including gain impact, noise impact, etc.), so as to ensure the performance of the overall full-duplex receiving system.

Contents of the invention

The object of the present invention is to provide a broadband full-duplex receiver based on the shared interference cancellation of the higher delay amount cancellation circuit.

The structure of the broadband full-duplex receiver sharing the interference elimination circuit provided by the present invention is shown in Fig. 1 . It is mainly composed of a receiver module and an interference elimination circuit module, among which:

(1) The receiver module mainly includes: a transconductance unit, a mixer, a transimpedance amplifier and a frequency conversion loop, the structure of which is shown in FIG. 2 . in:

The transconductance unit (G _M ) is used to amplify the radio frequency signal and provide a smaller noise figure; specifically, the transconductance unit (G _M ) forms a receiver input amplification stage, which performs broadband amplification on the input radio frequency signal, provides a certain gain while contributing a small noise figure, and the distortion is as small as possible when a large signal is input;

The mixer is used for mixing the radio frequency signal and mixing it down to the baseband;

A transimpedance amplifier (TIA), which is used to filter and amplify the down-mixed baseband signal to finally form an analog baseband signal;

The frequency conversion loop is used to perform input matching on the front end of the receiver;

In the receiver, the low-noise transconductance unit (G _M ) of the front end does not have input matching capability; the frequency conversion loop includes a matching network composed of input resistors and an up-mixer; the anti-phase signal drawn from the transimpedance amplifier (TIA) passes through the matching network, is up-mixed again, and is connected to the input of the receiving front-end, so as to realize the input matching of the receiving front-end.

(2) described interference elimination circuit, comprises the variable gain active low-pass filter unit (LPF) of input matching network and input lower mixer, quadrature selection phase shifter and baseband part, and its concrete composition is as shown in accompanying drawing 3; Wherein:

The two inputs (TX _P , TX _N ) of the interference elimination circuit are a pair of differential input ports, which receive differential input signals converted by an off-chip balun;

The input matching network is composed of a differential resistor _R1 , which is connected between the differential inputs of the elimination circuit, matches the input radio frequency signal, and then transmits the signal to the front of the input down-mixer. The differential radio frequency input signal is divided into IQ two-way orthogonal baseband differential signals after being down-mixed by the passive mixer controlled by the four-phase clock φ0~φ3; a differential capacitor C ₁ is located between the orthogonal differential paths and can be used as the delay adjustment unit of the baseband part. After down-mixing and preliminary delay adjustment, the signal enters the quadrature selection phase shifter. The quadrature selection phase shifter is used for quadrant selection of the IQ quadrature signal after down-mixing; the phase-selected signal enters the baseband variable gain active low-pass filter unit (LPF), and the IQ two-way low-pass filter unit performs gain control and further delay adjustment on the quadrature signal. The adjusted signal is output to the receiver module in the form of an orthogonal differential signal for self-interference cancellation.

The variable-gain active low-pass filter unit (LPF) is used to adjust the amplitude and determine the signal bandwidth; the variable-gain active low-pass filter unit is a Gm-C filter based on an open-loop transconductance amplifier, which is formed by cascading an input differential capacitor C ₂ , a variable-gain fully differential transconductance unit (G _{M_LPF} ) and a variable output differential capacitor _CL . The capacitor _CL is used as one of the capacitors for adjusting the delay of the baseband part, and the transconductance G _{M_LPF} can adjust the gain of the baseband part. The fully differential transconductance unit (G _{M_LPF} ) is composed of a switch-controlled 6-bit complementary CMOS transconductance array, and the specific circuit structure of each unit is shown in Fig. 4 . In the fully differential transconductance unit (G _{M_LPF} ), the gates and drains of the NMOS transistors M ₁ -M ₂ and the PMOS transistors M ₃ -M ₄ are connected in parallel, serving as input and output nodes of the transconductance unit, respectively. The sources of NMOS transistors M ₁ ~ M ₂ are grounded through switches, and the sources of PMOS transistors M ₃ ~ M ₄ are connected to power supply through switches. Through this connection, a complementary form of transconductance array unit is formed, so that the circuit can obtain greater transconductance under a smaller current. The resistor Rf is a feedback type self-biasing resistor, which is connected between the input and output of the transconductance unit, so that the DC level of the common mode of the output and input can be stabilized at 1/2 of the power supply voltage.

The broadband full-duplex receiver designed by the present invention, its connection mode and specific implementation mode are shown in accompanying drawing 1 and accompanying drawing 5 respectively. The interference elimination circuit performs down-mixing on the input signal and reconstructs it in the baseband part, and the reconstructed signal is introduced into the frequency conversion loop in the receiver module for self-interference elimination. Among them, the interference elimination circuit and the up-mixer in the frequency conversion loop form the elimination path I, and the reconstructed signal is introduced into the radio frequency input of the receiver module for self-interference elimination; the interference elimination circuit and the matching network in the frequency conversion loop form the elimination path II, and the reconstructed signal is introduced into the radio frequency input of the receiver module for self-interference elimination. In the interference elimination process, only one elimination circuit module is used to realize two elimination paths, that is, the elimination path I and the elimination path II share an interference elimination circuit, and the present invention is called a broadband full-duplex receiver with a shared interference elimination circuit.

In the full-duplex receiver proposed by the present invention, the delay and amplitude adjustment of the interference elimination circuit are converted to baseband adjustment, so that the overall area and power consumption are small. At the same time, compared with the way of implementing radio frequency delay by using passive RC or active Gm-RC, the elimination circuit in the present invention can realize a larger amount of delay in the radio frequency domain. At the same time, the method of shared cancellation prevents the cancellation circuit from being directly connected to the front end of the receiver module, so that while providing two-way cancellation, the noise figure deterioration of the receiver module is small.

Description of drawings

FIG. 1 is a structural block diagram of a broadband full-duplex receiver sharing an interference elimination circuit according to the present invention.

FIG. 2 is a structural diagram of a receiver module in the full-duplex receiver of the present invention.

FIG. 3 is a schematic diagram of the structure of the interference cancellation circuit module in the full-duplex receiver of the present invention.

FIG. 4 is a schematic diagram of the structure of the active filter in the interference elimination circuit module of the present invention.

FIG. 5 is a specific structural diagram of the broadband full-duplex receiver based on the shared interference elimination circuit of the present invention.

FIG. 6 is a schematic diagram of the principle of the quadrant selection phase shifter in the present invention.

FIG. 7 shows the result of the maximum delay generated by the elimination circuit module in the radio frequency domain in a specific example of the present invention.

Fig. 8 is the performance result of self-interference cancellation in the specific example of the present invention.

Fig. 9 is the result of the noise figure of the receiver module before and after interference cancellation in the specific example of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

As shown in FIG. 1 , it is a block diagram of a wideband full-duplex receiver based on shared cancellation proposed by the present invention. It mainly includes receiver module and elimination circuit module.

The specific implementation of the receiver module is shown in Fig. 2 . The specific composition is: a transconductance unit as an input amplifier stage, a down-mixing unit, a transimpedance amplifier TIA in the baseband part, and a frequency conversion loop. The frequency conversion loop is composed of a matching circuit and an upper mixer, and the matching network is composed of a resistor R _FB . Since the transconductance unit G _M does not provide input matching, its input impedance is very high, so near the local oscillator frequency of the LO, the impedance of the entire receiver can be derived through the mapping effect of the passive mixer in the frequency conversion loop, which can be expressed as:

Among them, R _F and _CF are respectively the feedback resistance value and the feedback capacitance value of the transimpedance amplifier TIA. It can be seen from equation (1) that the impedance of the baseband transimpedance amplifier TIA is mapped to the input of the receiver through the frequency conversion loop, and the gain characteristic of the baseband is a low-pass filter characteristic, so the input port of the receiver will present a low impedance characteristic near the local oscillator frequency. The cutoff frequency of this low impedance is the same as that of the TIA, so it is a narrowband match, but the match can be adjusted with the LO frequency over the entire operating frequency band, showing the characteristic of frequency agility.

The specific implementation of the interference elimination circuit module is shown in Fig. 3 . The specific components are: input matching network, input down-mixer, quadrature selection phase shifter unit and baseband variable gain low-pass filter unit. The input matching network is composed of a differential resistor R1, so that the input RF signal can be well matched within the required frequency band and reduce the return loss of the input signal; the input down-mixer is composed of a passive mixer controlled by a four-phase clock φ0~φ3, which is used to down-mix the input RF signal to the baseband; the quadrature selection phase shifter is composed of a set of switches. The low-pass filter unit is composed of a Gm-C filter composed of an open-loop transconductance amplifier (as shown in Figure 4), which filters the IQ two-way baseband signals and simultaneously performs controllable delay and gain adjustments.

In the full-duplex receiver proposed by the present invention, after the radio frequency signal input to the elimination circuit is matched by the input matching resistor _R1 , the input signal is mixed to the baseband by a four-phase double-balanced down-mixer and then mixed to the input end of the receiver by a synchronous four-phase single-balanced mixer. The circuit of the adjustment part of the baseband is divided into three parts, namely the capacitor C ₁ , the phase shifting part and the active filter. The phase shifting part is implemented by a quadrature selection phase shifter composed of a group of switches. The specific implementation is to use four switch tubes to determine which quadrant the separation and recombination signals of the IQ two-way signals will fall into. The principle of phase shifting combined with the low-pass filter part is shown in Figure 6. The quadrature selection phase shifter selects the polarity of the IQ two-way signal, and at the same time, the variable gain active low-pass unit controls the amplitude of the signal. The phase shift characteristics in different quadrants can be realized through the combination of the two. When both the IQ and IQ channels select in-phase signals, the final composite signal will be in the first quadrant. At this time, the precise phase adjustment can be determined by adjusting the amplitudes of the IQ and IQ channels respectively. The phase modulation range at this time is 0°～90°. When the IQ channel selects the in-phase and anti-phase signals respectively, the final composite signal will be in the fourth quadrant, and the phase modulation range at this time is 270°~360°.

In the cancellation circuit of the full-duplex receiver, the main function of the active filter is to adjust the amplitude and determine the signal bandwidth, and its filtering characteristics determine the out-of-band characteristics of the cancellation circuit. The variable gain filter unit in the elimination circuit proposed by the present invention is based on the Gm-C filter _design of the transconductance amplifier. The structure is as shown in Figure 4. _The transconductance unit G _{M_LPF} is composed of a 6-bit complementary CMOS transconductance array controlled by a switch. If R _sw and R _p are equivalent to the equivalent resistance of the down-mixer and phase shifting part respectively, R _in and C ₂ are the equivalent input resistance and equivalent input capacitance before the transconductance unit in the low-pass filter. C ₁ and C _L are delay control capacitors. The transfer function of the entire cancellation circuit can be expressed as:

It can be seen that the amplitude adjustment of the elimination circuit proposed by the present invention can be realized by adjusting the transconductance value _{Gm_LPF} of the transconductance unit, and the adjustment of the delay can be controlled by the capacitors _C1 and _CL , and its delay can be expressed as:

τ＝R _in R _sw (C ₁ +C ₂ )+R _p (R _sw C ₁ +R _in C ₂ )+R _L C _L ; (3)

There are two items of the delay term of _C1 in formula (3), and part of the delay is generated by the large input resistance of the transconductance unit and the capacitor _C1 . Therefore, the baseband part can use the capacitor _C1 with a large capacitance to realize a large amount of time delay.

The specific implementation of the broadband full-duplex receiver based on the shared interference elimination circuit proposed by the present invention is shown in Fig. 5 . The output of the baseband part of the elimination circuit realizes shared elimination by sharing the upper mixing module with the frequency conversion loop of the receiver. It can be found that the full-duplex receiver in the present invention also forms two cancellation paths after the frequency conversion loop of the cancellation circuit module and the receiver module shares the upper mixer. The first path is the radio frequency domain elimination path formed by the shared elimination circuit module through the up-mixer to the radio frequency input port, which is the blue elimination path I described in FIG. 5 . By adjusting the phase, delay and gain of the baseband part in the shared cancellation circuit, the reconstruction of the self-interference signal in the radio frequency domain can be realized, and then the cancellation can be completed. The other path is the baseband domain elimination path from the shared elimination circuit module through the feedback resistor in the frequency conversion loop to the output of the transconductance amplifier TIA, as shown in the green elimination path II in FIG. 5 . Since the two paths share a cancellation circuit, it can be called a shared cancellation method. In addition to being able to generate dual cancellation paths to increase the cancellation amount of the cancellation circuit, another advantage of using shared cancellation is that this method avoids directly connecting the cancellation circuit in the radio frequency domain to the front end of the receiver, which reduces the strong deterioration of the noise figure of the receiver.

The full-duplex receiver based on the shared cancellation method in the above specific examples can finally work in the frequency band of 0.5-3.5 GHz, and has a wide radio frequency working range. At the same time, in the frequency band of 0.5-3.5 GHz, the elimination circuit can achieve higher delay with smaller power consumption and area. Compared with the previous self-interference cancellation structure based on time-domain reconstruction, the cancellation circuit of the present invention converts the delay adjustment to the baseband domain, so that the maximum delay of the entire module can reach 3.86-8.33ns in the working frequency band, as shown in Figure 7, and overcomes the difficulty that the delay in the middle and high frequency frequencies cannot reach the nanosecond level by relying solely on RC. In terms of full-duplex performance, the elimination method for shared elimination proposed by the present invention uses only one elimination module to achieve dual-path elimination, and the passband can achieve self-interference elimination performance better than 25dB under different carrier frequencies within the 0.5-3.5GHz bandwidth, as shown in Figure 8. At the same time, due to the characteristics of the shared cancellation method, the noise figure degradation caused by the cancellation circuit to the front end of the receiver is only 0.9-1.2dB, as shown in Figure 9.

Claims (3)

1. A broadband full-duplex receiver for shared interference elimination circuit, characterized in that it is made up of receiver module and interference elimination circuit module, wherein: The receiver module includes: a transconductance unit, a mixer, a transimpedance amplifier and a frequency conversion loop, wherein: The transconductance unit (G _M ) is used to amplify the radio frequency signal and provide a smaller noise figure; specifically, the transconductance unit (G _M ) forms a receiver input amplification stage to perform broadband amplification of the input radio frequency signal, and when the amplified signal is input, the distortion is as small as possible; The mixer is used for mixing the radio frequency signal and mixing it down to the baseband; A transimpedance amplifier (TIA), which is used to filter and amplify the down-mixed baseband signal to finally form an analog baseband signal; The frequency conversion loop is used to perform input matching on the front end of the receiver; The frequency conversion loop includes a matching network composed of input resistances and an up-mixer; the inverted signal drawn from the transimpedance amplifier (TIA) passes through the matching network, is up-mixed again, and is connected to the input of the receiving front end, so as to realize the input matching of the receiving front end; The interference elimination circuit includes an input matching network and an input down-mixer, a quadrature selection phase shifter and a variable gain active low-pass filter unit (LPF) of the baseband part, wherein: The two inputs of the interference elimination circuit are a pair of differential input ports, and the differential input ports receive differential input signals converted by an off-chip balun; The input matching network consists of a differential resistor R₁Composition, connected between the differential inputs of the elimination circuit, matching the input RF signal, and then passing the signal to the input down-mixer; the differential RF input signal is divided into IQ two-way orthogonal baseband differential signals after being down-mixed by the passive mixer controlled by the four-phase clock φ0~φ3; a differential capacitor C₁It is located between the quadrature differential channels and acts as the delay adjustment unit of the baseband part; the signal enters the quadrature selection phase shifter after down-mixing and preliminary delay adjustment, and the quadrature selection phase shifter is used for quadrant selection of the IQ quadrature signal after the down-mixing; the signal after phase selection enters the baseband variable gain active low-pass filter unit (LPF), and the low-pass filter unit of the IQ two-way performs gain control and further delay adjustment on the quadrature signal respectively; The form is output to the receiver module for self-interference cancellation. 2. the wideband full-duplex receiver of shared interference elimination circuit according to claim 1, it is characterized in that, described variable gain active low-pass filter unit (LPF), is used for the adjustment of amplitude and the determination of signal bandwidth; This variable gain active low pass filter unit is the Gm-C filter based on open-loop transconductance amplifier, is formed by cascade connection of input differential capacitor C ₂ , variable gain full differential transconductance unit (G _{M_LPF} ) and variable output differential capacitor _CL ; Wherein: Capacitance C_LAs one of the capacitors to adjust the delay of the baseband part, and the fully differential transconductance unit (G_{M_LPF}) is used to adjust the gain size of the baseband part; the fully differential transconductance unit (G_{M_LPF}) consists of a 6-bit complementary CMOS transconductance array controlled by a switch; where, the NMOS transistor M₁~ M₂and PMOS tube M₃~ M₄The gate and drain of the transconductance unit are connected in parallel, respectively as the input and output nodes of the transconductance unit; the NMOS transistor M₁~ M₂The source of the switch is grounded, and the PMOS tube M₃~ M₄The source of the source is connected to the power supply through a switch, and through this connection, a complementary transconductance array unit is formed, so that the circuit can obtain a larger transconductance under a small current; the resistor Rf is a feedback type self-bias resistor, which is connected between the input and output of the transconductance unit, so that the DC level of the output and input common mode can be stabilized at 1/2 of the power supply voltage. 3. the wide-band full-duplex receiver of shared interference elimination circuit according to claim 2, it is characterized in that, interference elimination circuit carries out down-mixing of input signal and carries out reconstruction at baseband part, the signal after reconstruction is introduced into the frequency conversion loop in the receiver module and carries out self-interference elimination; Wherein, the upper mixer in the interference elimination circuit and frequency conversion loop forms elimination path I, the radio frequency input that the signal of reconstruction is introduced into receiver module carries out self-interference elimination; interference elimination circuit and the matching network in the frequency conversion loop form elimination path II, The signal is introduced into the radio frequency input of the receiver module for self-interference elimination; in the interference elimination process, only one interference elimination circuit is used to realize two elimination paths, that is, the elimination path I and the elimination path II share one interference elimination circuit.