CN116454033A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN116454033A CN116454033A CN202310488903.8A CN202310488903A CN116454033A CN 116454033 A CN116454033 A CN 116454033A CN 202310488903 A CN202310488903 A CN 202310488903A CN 116454033 A CN116454033 A CN 116454033A
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- indium
- indium layer
- layer
- chip
- heat dissipation
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 164
- 229910052738 indium Inorganic materials 0.000 claims abstract description 163
- 230000017525 heat dissipation Effects 0.000 claims abstract description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 14
- 230000004927 fusion Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 10
- 238000002844 melting Methods 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000000155 melt Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 9
- 230000004907 flux Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 100
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 150000001768 cations Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging structure and a preparation method thereof, the packaging structure comprises a substrate, a chip and a heat dissipation cover, the chip is inversely arranged on the substrate, the heat dissipation cover is used for wrapping the chip, a nickel layer and a first indium layer are arranged on the inner side of the heat dissipation cover from top to bottom, a second indium layer is arranged on the surface of the chip, the materials of the first indium layer and the second indium layer are the same, and the first indium layer and the second indium layer are combined in a fusion mode. According to the chip packaging structure disclosed by the invention, the first indium layer and the second indium layer which are made of the same material are arranged, and the indium sheet is arranged between the first indium layer and the second indium layer according to the requirement, so that after the combination is realized through melting, the coverage rate on the surface of the chip is high, the heat dissipation effect of a packaging product is ensured, and the yield of the packaging product is increased. No flux is used in the method disclosed by the invention, and no bubbles are generated.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a preparation method thereof.
Background
The traditional packaging needs to be conducted by using the metal radiating fins, the metal radiating fins absorb heat quickly, and meanwhile, the heat dissipation speed is relatively high, so that the effect of quick heat dissipation is achieved through heat transfer. In general, a heat conducting adhesive layer (interface heat conducting material) is coated on the contact surface of an electronic component and a heat sink in use, so that heat emitted by the component is more effectively conducted to the heat sink and then emitted to the surrounding air through the heat sink. The heat transfer capability of the interface heat transfer material determines whether the heat generated by the CPU can be effectively dissipated. For high-end CPUs, a common interface thermal conductive material is an indium sheet, which is composed of pure indium. The heat conductivity coefficient is about 86W/mk, which is the highest in the welding material.
At present, an indium sheet is used as an interface heat conduction material to be welded with a gold-backed chip and a gold-backed radiating sheet through soldering flux. However, in the process of reflow high temperature, the soldering flux is easy to generate bubbles to cause cavities, so that the coverage rate of the indium sheet on the nonfunctional surface of the chip is not high, the heat conduction effect of packaging is reduced, and the yield of packaged products is reduced.
Therefore, a new chip package structure is needed to solve the air bubble and heat dissipation problems.
Disclosure of Invention
In order to solve the problems, the invention discloses a chip packaging structure and a preparation method thereof, which can solve the problems of air bubbles and heat dissipation of the traditional packaging structure.
The invention discloses a first chip packaging structure, which comprises a substrate, a chip and a heat dissipation cover, wherein the chip is inversely arranged on the substrate, the heat dissipation cover is arranged on the substrate, the heat dissipation cover coats the chip, a nickel layer and a first indium layer are arranged on the inner side of the heat dissipation cover from top to bottom, a second indium layer is arranged on the surface of the chip, the materials of the first indium layer and the second indium layer are the same, and the first indium layer and the second indium layer are combined in a fusion mode. According to the invention, the first indium layer and the second indium layer which are made of the same material are arranged at the joint of the heat dissipation cover and the chip, the first indium layer and the second indium layer are fused and combined, the fused first indium layer and second indium layer are combined into one indium layer, and the indium layer can be uniformly covered on the surface of the chip. In the packaging structure, no soldering flux is needed, so that no bubbles are generated, the coverage rate of the indium layer on the surface of the chip is high, the heat dissipation effect of the packaging product can be ensured, and the yield of the packaging product is increased.
The invention also discloses a second chip packaging structure, which is different from the first packaging structure in that: the package structure further comprises an indium sheet, wherein the indium sheet is arranged between the first indium layer and the second indium layer. The material of the indium sheet is the same as that of the first indium layer and the second indium layer, and the first indium layer, the second indium layer and the indium sheet are combined in a melting way. In the invention, the first indium layer, the indium sheet and the second indium layer after melting are combined into one indium layer, and the indium layer can be uniformly covered on the surface of the chip. In this package structure, also because no flux is required, no bubbles are generated; the indium sheet is increased, the coverage rate of the melted indium layer on the surface of the chip is increased, the heat dissipation effect of the packaged product is ensured, and the yield of the packaged product is increased.
On the other hand, the invention also discloses a preparation method of the first chip packaging structure, and the packaging method comprises the following steps:
s1, electroplating a nickel layer on the inner side surface of a heat dissipation cover, and electroplating a first indium layer on the surface of the nickel layer;
s2, arranging a second indium layer on the surface of the chip;
s3, coating the heat dissipation cover on the chip, and enabling the first indium layer and the second indium layer to be combined in a melting mode.
Finally, the invention also discloses a preparation method of the second chip packaging structure, which is different from the preparation method of the first chip packaging structure in that: in the step S3, an indium sheet is disposed between the first indium layer and the second indium layer, and the first indium layer, the second indium layer and the indium sheet are fusion bonded.
Compared with the prior art, the invention has the beneficial effects that:
according to the chip packaging structure disclosed by the invention, the first indium layer and the second indium layer which are made of the same material are arranged, and the indium sheet is arranged between the first indium layer and the second indium layer according to the requirement, so that after the combination is realized through melting, the coverage rate on the surface of the chip is high, the heat dissipation effect of a packaging product is ensured, and the yield of the packaging product is increased. No flux is used in the method disclosed by the invention, and no bubbles are generated.
The preparation method of the chip packaging structure provided by the invention has the advantages of simple process, no bubble in the indium layer, good heat dissipation effect and capability of better supporting the high-density and integrated development of integrated circuit packaging products.
Drawings
Fig. 1 is a schematic structural diagram of a package structure in embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a package structure in embodiment 2 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Example 1
The embodiment discloses a chip 2 packaging structure of an embodiment.
As shown in fig. 1, the package structure includes a substrate 1, a chip 2 and a heat dissipation cover 3, the chip 2 is flip-chip mounted on the substrate 1, the heat dissipation cover 3 is disposed on the substrate 1, the heat dissipation cover 3 covers the chip 2, a nickel layer 30 and a first indium layer 31 are disposed on the inner side of the heat dissipation cover 3 from top to bottom, a second indium layer 20 is disposed on the surface of the chip 2, the materials of the first indium layer 31 and the second indium layer 20 are the same, and the first indium layer 31 and the second indium layer 20 are fused and combined.
In this embodiment, the thicknesses of the first indium layer 31 and the second indium layer 20 are 4-8um; the first indium layer 31 and the second indium layer 20 are fusion bonded by baking or reflow.
In this embodiment, the first indium layer 31 and the second indium layer 20 made of the same material are disposed at the connection position of the heat dissipation cover 3 and the chip 2, and the first indium layer 31 and the second indium layer 20 are fused and combined, the fused first indium layer 31 and second indium layer 20 are combined into one indium layer, and the indium layer uniformly covers the surface of the chip 2. In the packaging structure, no soldering flux is needed, so that no bubbles are generated, the coverage rate of the indium layer on the surface of the chip 2 is high, the heat dissipation effect of the packaging product can be ensured, and the yield of the packaging product is increased.
The preparation method of the chip 2 packaging structure in this embodiment includes the following steps:
s1, electroplating a nickel layer 30 on the inner side surface of a heat dissipation cover 3, and electroplating a first indium layer 31 on the surface of the nickel layer 30;
s2, arranging a second indium layer 20 on the surface of the chip 2;
and S3, coating the heat dissipation cover 3 on the chip 2, and fusing and bonding the first indium layer 31 and the second indium layer 20.
In step S2, a metal layer may be disposed on the nonfunctional surface of the wafer, where the metal layer is the sputtered second indium layer 20, and then back grinding and dicing are performed to form a plurality of chips 2 with the second indium layer 20 disposed on the surfaces. The sputtering principle is that the process gas filled in the chamber of the sputtering machine forms gas plasma under the action of high voltage, cations in the gas plasma impact indium metal at high speed under the action of electric field force, and the cations and the indium metal exchange energy, so that indium atoms obtain enough energy to escape from the surface of the target material, and a second indium layer 20 is formed on the nonfunctional surface of the wafer.
In the present embodiment, the area of the first indium layer 31 is the same as the area of the surface of the chip 2. This also ensures that after fusion bonding, the indium layer uniformly covers the surface of the chip 2.
In step S3, the functional surface of the chip 2 is first flip-chip mounted on the substrate 1, the heat sink is bonded to the chip 2 by soldering, and the first indium layer 31 and the second indium layer 20 are sufficiently melted together by reflow at high temperature. The heat sink may be directly soldered to the back indium surface (surface of the second indium layer 20) of the chip 2, so that the second indium layer 20 and the first indium layer 31 on the inner side of the heat sink are sufficiently melted together.
In this embodiment, the connection manner between the heat dissipation cover 3 and the substrate 1, and the manner in which the chip 2 is flip-chip mounted on the substrate 1 are all conventional techniques, and will not be described herein.
Example 2
The present embodiment discloses another chip 2 package structure, which is different from the package structure disclosed in embodiment 1 above in that: the package structure of the present embodiment further includes an indium sheet 4, where the indium sheet 4 is disposed between the first indium layer 31 and the second indium layer 20. The material of the indium sheet 4 is the same as that of the indium sheet 4 of the first indium layer 31 and the second indium layer 20, and the first indium layer 31, the second indium layer 20 and the indium sheet 4 are fused and bonded.
In this embodiment, the first indium layer 31, the indium sheet 4 and the second indium layer 20 after melting are combined into one indium layer, and the indium layer may be uniformly covered on the surface of the chip 2. In this package structure, also because no flux is required, no bubbles are generated; the indium sheet 4 is added, the coverage rate of the melted indium layer on the surface of the chip 2 is increased, the heat dissipation effect of the packaged product is ensured, and the yield of the packaged product is increased.
In this embodiment, the thicknesses of the first indium layer 31 and the second indium layer 20 are 4-8um, and the thickness of the indium sheet 4 is 50-800um. In the subsequent melting process, the thickness can ensure that the indium layer can be uniformly covered on the surface of the chip 2 after melting.
In this embodiment, the first indium layer 31, the second indium layer 20 and the indium sheet 4 are also fusion bonded by baking or reflow. The reflux temperature is 170-180 ℃.
The packaging structure disclosed in this embodiment differs from the method disclosed in embodiment 1 in that: in step S3, the indium sheet 4 is provided between the first indium layer 31 and the second indium layer 20, and the first indium layer 31, the second indium layer 20, and the indium sheet 4 are fusion bonded.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that other modifications and improvements can be made without departing from the inventive concept of the present invention.
Claims (7)
1. The utility model provides a chip packaging structure, includes base plate, chip and heat dissipation lid, the chip is adorned on the base plate down, the heat dissipation lid is located on the base plate, heat dissipation lid cladding chip, a serial communication port, heat dissipation lid inboard top-down is equipped with nickel layer and first indium layer, the chip surface is equipped with the second indium layer, the material on first indium layer, second indium layer is the same, the fusion bonds between first indium layer and the second indium layer.
2. The chip package structure of claim 1, further comprising an indium sheet disposed between the first indium layer and the second indium layer, wherein the indium sheet is made of the same material as the first indium layer and the second indium layer, and the first indium layer, the second indium layer and the indium sheet are fusion bonded.
3. The chip package structure of claim 2, wherein the thickness of the first indium layer and the second indium layer is 4-8um, and the thickness of the indium sheet is 50-800um.
4. The chip packaging structure according to claim 3, wherein fusion bonding is achieved between the first indium layer and the second indium layer through baking or reflow; and the first indium layer, the second indium layer and the indium sheet are in fusion bonding through baking or reflow.
5. A method of manufacturing a chip package structure according to any one of claims 1 to 4, wherein the packaging method comprises the steps of:
s1, electroplating a nickel layer on the inner side surface of a heat dissipation cover, and electroplating a first indium layer on the surface of the nickel layer;
s2, arranging a second indium layer on the surface of the chip;
s3, coating the heat dissipation cover on the chip, and enabling the first indium layer and the second indium layer to be combined in a melting mode.
6. The method according to claim 5, wherein in the step S3, an indium sheet is disposed between the first indium layer and the second indium layer, and the first indium layer, the second indium layer, and the indium sheet are fusion bonded.
7. The method of claim 5, wherein the melt bonding is achieved by high temperature reflow at a temperature of 170-180 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310488903.8A CN116454033A (en) | 2023-04-28 | 2023-04-28 | Chip packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310488903.8A CN116454033A (en) | 2023-04-28 | 2023-04-28 | Chip packaging structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116454033A true CN116454033A (en) | 2023-07-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310488903.8A Pending CN116454033A (en) | 2023-04-28 | 2023-04-28 | Chip packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116454033A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118263207A (en) * | 2024-05-28 | 2024-06-28 | 甬矽电子(宁波)股份有限公司 | Radiator structure of flip chip ball grid array and manufacturing method thereof |
-
2023
- 2023-04-28 CN CN202310488903.8A patent/CN116454033A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118263207A (en) * | 2024-05-28 | 2024-06-28 | 甬矽电子(宁波)股份有限公司 | Radiator structure of flip chip ball grid array and manufacturing method thereof |
| CN118263207B (en) * | 2024-05-28 | 2024-08-30 | 甬矽电子(宁波)股份有限公司 | Radiator structure of flip chip ball grid array and manufacturing method thereof |
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