CN116450430A - Verification method, verification system and storage medium for processor - Google Patents
Verification method, verification system and storage medium for processor Download PDFInfo
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- CN116450430A CN116450430A CN202310358598.0A CN202310358598A CN116450430A CN 116450430 A CN116450430 A CN 116450430A CN 202310358598 A CN202310358598 A CN 202310358598A CN 116450430 A CN116450430 A CN 116450430A
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- 238000012795 verification Methods 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 60
- 238000003860 storage Methods 0.000 title claims abstract description 14
- 238000012544 monitoring process Methods 0.000 claims abstract description 52
- 238000004088 simulation Methods 0.000 claims abstract description 45
- 238000012545 processing Methods 0.000 claims description 14
- 238000004590 computer program Methods 0.000 claims description 4
- 238000010200 validation analysis Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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Abstract
The invention provides a verification method, a verification system and a storage medium of a processor. In the verification method of the processor, the processor is provided with a kernel and a pipeline monitoring unit, and comprises the following steps: configuring the kernel and the pipeline monitoring unit; the kernel and the pipeline monitoring unit are integrated; performing simulation verification on the processor; wherein the emulation verification comprises hardware-based emulation verification. The verification method of the invention enables the pipeline monitoring unit to be integrated with the processor core at the same time, is compatible with software-based simulation and hardware-based simulation verification, and improves the efficiency and accuracy of the simulation and verification of the processor.
Description
Technical Field
The present invention relates to a method for verifying a processor, and more particularly, to a method for verifying a hardware-based processor, a verification system, and a storage medium.
Background
In existing large scale integrated circuits, such as processors (CPU, GPU, RISC-V), pipelining is often employed to improve instruction execution performance of the processor.
During the design of a processor, the processor core is written using register transfer level (RTL: register Transfer Level) code. In performing emulation verification of a processor, it is necessary to compare the results of instruction execution in the processor core RTL with the results of instruction execution in the instruction set emulator (ISS: instruction Set Simulator). Instructions in the processor core are typically executed out-of-order in parallel, and there is no way to obtain the full state of the architecture register (architectural registers) and control status register (CSR: control Status Register) after execution of an instruction at a certain time via signals in RTL, so a pipeline monitor unit (pipeline monitor) is required to sample and collect the results of execution of the instructions in the processor core from the processor pipeline, and reorder the results according to the instruction order and issue them. And comparing the instruction execution result of the processor core with the execution result in the Instruction Set Simulator (ISS), and further judging whether the instruction execution in the processor core RTL is correct.
Existing pipeline monitoring units are implemented in software and integrated into a processor, and typically cannot be integrated. Therefore, when hardware-based emulation, verification, or testing of a processor is performed, the processor core and the pipeline monitoring unit cannot be performed simultaneously. It is necessary to develop a different pipeline monitoring unit at the time of software-based or hardware-based simulation verification (simulator or FPGA), or to discard the use of the pipeline monitoring unit at the time of hardware-based simulation verification.
Therefore, how to provide a method for simultaneously compatible software-based simulation and hardware-based simulation verification, and improving the efficiency and accuracy of simulation and verification of a processor is one of the problems to be solved.
Disclosure of Invention
The embodiment of the invention provides a verification method and a storage medium for a processor, which can be compatible with software-based simulation and hardware-based simulation verification, and improve the efficiency and accuracy of the simulation and verification of the processor.
The verification method of the processor provided by the embodiment of the invention comprises the following steps of: configuring the kernel and the pipeline monitoring unit; the kernel and the pipeline monitoring unit are integrated; performing simulation verification on the processor; wherein the emulation verification comprises hardware-based emulation verification.
The verification method, wherein the step of configuring the core and the pipeline monitoring unit includes configuring the core and the pipeline monitoring unit using RTL level code.
The verification method, wherein the RTL level code comprises code written in a hardware description language.
The verification method, wherein the hardware description language comprises VHDL or Verilog.
The verification method comprises the step of performing simulation verification through a hardware simulation platform or an FPGA.
The verification method, wherein the verification method further comprises the following steps:
EDA simulation is performed on the processor prior to integrating the core and the pipeline monitoring unit.
The verification method described above, wherein, the EDA simulation further includes:
comparing the instruction execution result captured by the pipeline monitoring unit in the pipeline with the instruction execution result in the instruction set simulator through the instruction set architecture checking unit;
and printing the instruction execution result grabbed in the pipeline by the pipeline monitoring unit into a tracking log file through a table format.
According to the verification method, the pipeline monitoring unit collects instruction processing information of the kernel in a hierarchical reference mode.
The verification method, wherein the instruction processing information comprises instruction distribution information, instruction submission information and instruction write-back information.
In the verification method, the pipeline monitoring unit temporarily stores and reorders the instruction processing information, and after the instruction write-back is completed, the instruction execution result is sent out according to the order of the instruction stream.
The verification method, wherein the verification method further comprises the following steps:
and displaying the instruction execution result in a waveform form, and positioning errors in the simulation verification process according to the instruction execution result.
The processor verification system according to an embodiment of the present invention is configured to execute any one of the above-described processor verification methods.
The storage medium according to an embodiment of the present invention is configured to store a computer program for executing the authentication method of any one of the processors described above.
The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.
Drawings
FIG. 1 is a schematic diagram of a processor according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a pipeline architecture according to an embodiment of the present invention.
FIG. 3 is a flow chart of a verification method of a processor according to an embodiment of the invention.
FIG. 4 is a schematic diagram of an architecture of a verification system of a processor according to an embodiment of the invention.
FIG. 5 is a schematic diagram of an architecture of a verification system of a processor according to another embodiment of the present invention.
Wherein, the reference numerals:
10: processor and method for controlling the same
11: arithmetic logic unit
12: control unit
13: cache memory
14: register
15: bus line
100: verification method
S101-S104: step (a)
200. 200': verification system
201. 201': processor and method for controlling the same
202. 202': processor core
203. 203': pipeline monitoring unit
204. 204': verification device
2041. 2041': instruction level architecture checking unit
2042. 2042': instruction set emulator
205: display unit
Detailed Description
The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of a processor according to an embodiment of the invention. As shown in fig. 1, the processor 10 includes an arithmetic logic unit (ALU arithmetic and logic unit) 11, a control unit (CU control unit) 12, a cache 13, and a register 14. Among them, the arithmetic logic unit 11, the control unit 12, the cache 13 and the register 14 perform data transmission via the bus 15, and of course, the processor 10 performs data transmission between external devices (not shown in the figure), such as an input/output device, a storage device and a display device, via the bus 15.
In the present invention, the cache 13 may be a level one cache or a multi-level cache. Registers 14 may include data registers, address registers, instruction registers, and other types of registers, and the bus may be an address bus, a data bus, a control bus, or the like. The invention is not limited thereto.
The application program is processed by a compiler into machine code for execution, and the application program is translated into a piece of instructions (Instruction). FIG. 2 is a schematic diagram of a pipeline architecture according to an embodiment of the present invention. As shown in fig. 2, taking a 5-stage pipeline as an example, the operation of a processor for one instruction generally includes: (1) Instruction fetch IF (IF, instruction Fetch) stage, fetching an instruction from storage device to register 14; (2) An instruction decoding ID (ID, instruction Decode) stage, wherein the instruction decoder splits and interprets the fetched instructions according to a preset instruction format, and identifies different instruction categories and various operand fetching methods; (3) The instruction executes EX (Execute) stage to complete various operations specified by the instruction and realize the function of the instruction; (4) A Memory access number MEM (Memory) stage, according to instruction requirement, it is possible to access the storage device to read the operand, according to instruction address code, obtain the address of operand in the storage device, and read the operand from the storage device for operation; (5) A Writeback (WB) stage writes execution result data of the execution instruction stage back into the storage device.
The pipelining technique of the processor 10 is a technique that decomposes instructions into multiple steps and allows the operations of the different instructions to overlap, thereby implementing parallel processing of several instructions to speed up the program execution process. As shown in fig. 2, each of the stages of the instruction 1, the instruction 2, and the instruction 3 is sequentially executed, and the instruction 1, the instruction 2, and the instruction 3 may be executed in parallel.
In order to obtain the execution state of an instruction, a pipeline monitoring unit is required to sample and collect the result of instruction execution from a pipeline, obtain the position of the pipeline where the instruction is located, whether an exception occurs, whether write back is performed, and so on.
FIG. 3 is a flow chart of a verification method of a processor according to an embodiment of the invention. As shown in fig. 3, the verification method 100 of the processor of the present invention includes the steps of:
step S101, configuring a processor core and a pipeline monitoring unit. The processor cores and pipeline monitoring units are implemented using hardware description languages commonly used including VHDL and Verilog. In the invention, the processor core and the pipeline monitoring unit in the processor are realized by adopting hardware description language, and the processor core and the pipeline monitoring unit are preferably realized by adopting RTL (real time digital hierarchy) level codes.
Step S103, the processor core and the pipeline monitoring unit are integrated.
Synthesis (Synthesis) is a method commonly used in integrated circuit design, and refers to the process of designing an integrated circuit, the process of transcoding the register transfer level description (RTL register transfer level) to the gate level netlist (Gate Level Netlist) is called logic Synthesis (LogicSynthesis).
RTL code is just a description of the implementation of the logic functions of the circuit and is an ideal state. In an actual circuit, due to different production processes, the delay of logic gates, the delay of wiring, the delay of clocks, and the like are necessarily present in the circuit. Therefore, in order to optimize the circuit, it is necessary to convert the RTL code into a gate level netlist, and the synthesis tool selects and adjusts the circuit structure of various devices in the circuit by using the circuit information (logic functions, areas, timing relationships, etc.) provided by the process library.
Because the processor core and the pipeline processing unit are realized by adopting synthesizable hardware description language, when the processor is subjected to hardware-based simulation verification, for example, the processor core and the pipeline monitoring unit are synthesized when the processor is subjected to the hardware-based simulation verification through a hardware simulation platform (simulator) or through an FPGA, so that the hardware of the processor core and the pipeline monitoring unit is realized. In the invention, the pipeline monitoring unit collects instruction processing information of the processor core, wherein the instruction processing information mainly comprises instruction distribution information, instruction submission information, instruction write-back information and the like. The instruction processing information is temporarily stored in a buffer in the pipeline monitoring unit, the instruction processing information is reordered according to the order of the instruction streams, and after the execution of the instructions is completed and the write-back is performed, the pipeline monitoring unit sends out the instruction execution results according to the order of the instruction streams.
Step S104, performing simulation verification on the processor. Simulation verification is performed by a hardware simulation platform (simulator) or by an FPGA. In the simulation verification process, comparing the instruction execution result sent by the pipeline monitoring unit or the instruction execution result grabbed from the pipeline with the instruction execution result in the instruction set simulator through the instruction set architecture (ISA: instruction SetArchitecture) checking unit; and further determine whether the instruction execution in the processor core is correct.
In the present invention, in order to better browse the instruction execution result and assist in Debug, the instruction execution result sent by the pipeline monitoring unit may also be printed into the Trace (Trace) log file in a table format. Or displaying the instruction execution result in a waveform form through a display unit in the verification device, and positioning errors in the simulation verification process according to the instruction execution result. Therefore, the error can be quickly corrected, and the efficiency and the accuracy of simulation verification are greatly improved.
The verification method 100 of the processor of the present invention may further include:
step S102, EDA simulation is conducted on the processor. I.e. the processor is subjected to EDA simulation before the core and the pipeline monitoring unit are integrated. Since the processor core and the pipeline monitoring unit are not hardware yet at this time, the pipeline monitoring unit collects instruction processing information of the processor core by means of hierarchical referencing. The hierarchical reference mode does not need a module in the pipeline to transmit relevant instruction processing information to the pipeline monitoring unit through a special interface, so that the expandability of the pipeline monitoring unit and the stability of a code of the pipeline module are greatly enhanced.
Similarly, when EDA simulation is performed, the instruction execution result sent by the pipeline monitoring unit or the instruction execution result grabbed from the pipeline is compared with the instruction execution result in the instruction set architecture checking unit and the instruction set simulator; and further determine whether the instruction execution in the processor core is correct. Of course, the steps of EDA simulation may be performed or omitted as needed, and the invention is not limited thereto.
FIG. 4 is a schematic diagram of an architecture of a verification system of a processor according to an embodiment of the invention. As shown in FIG. 4, the verification system 200 of the present invention includes a processor 201 and a verification device 204, the processor 201 further including a processor core 202 and a pipeline monitoring unit 203. The instruction execution result of the processor core 202 is transmitted to the verification device 204 through the pipeline monitoring unit 203, and the verification device 204 may be integrated with the instruction level architecture checking unit 2041 and the instruction set simulator 2042, where the verification device 204 compares the instruction execution result transmitted by the pipeline monitoring unit 203 with the instruction execution result in the instruction set simulator through the instruction level architecture checking unit to determine whether the instruction execution in the processor core is correct when performing EDA simulation or simulation verification through a hardware simulation platform (simulator) and an FPGA.
FIG. 5 is a schematic diagram of an architecture of a verification system of a processor according to another embodiment of the present invention. As shown in fig. 5, as with the verification system 200 shown in fig. 3, the verification system 200 'includes a processor 201' and a verification device 204', the processor 201' further including a processor core 202 'and a pipeline monitoring unit 203'. Instruction execution results of the processor core 202 'are transferred by the pipeline monitoring unit 203' to the verification device 204', and the verification device 204' may be integrated with the instruction level architecture checking unit 2041 'and the instruction set emulator 2042'. In addition, the verification system 200 'of the present invention further includes a display unit 205' for displaying the instruction execution result in the form of a waveform and locating an error occurring in the simulation verification process according to the instruction execution result.
The present invention also provides a storage medium storing a computer program for executing the authentication method of any one of the processors as described above.
In summary, according to the embodiment of the invention, the hardware of the processor kernel and the pipeline monitoring unit can be integrated, so that software-based simulation and hardware-based simulation verification can be compatible, and the efficiency and accuracy of simulating and verifying the processor are improved.
Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention, as will be apparent to those skilled in the art, without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A method of validating a processor having a core and a pipeline monitoring unit, comprising the steps of:
configuring the kernel and the pipeline monitoring unit;
the kernel and the pipeline monitoring unit are integrated;
performing simulation verification on the processor; wherein the method comprises the steps of
The simulation verification includes hardware-based simulation verification.
2. The method of validation of claim 1, wherein the step of configuring the core and the pipeline monitoring unit comprises configuring the core and the pipeline monitoring unit using RTL level code.
3. The authentication method of claim 2, wherein the RTL level code comprises code written using a hardware description language.
4. A verification method as claimed in claim 3 wherein said hardware description language comprises VHDL or Verilog.
5. The method of verification of claim 1, wherein the simulation verification comprises simulation verification by a hardware simulation platform or FPGA.
6. The authentication method of claim 1, wherein the authentication method further comprises:
EDA simulation is performed on the processor prior to integrating the core and the pipeline monitoring unit.
7. The authentication method of claim 1, wherein the simulated authentication further comprises:
comparing the instruction execution result captured by the pipeline monitoring unit in the pipeline with the instruction execution result in the instruction set simulator through the instruction set architecture checking unit;
and printing the instruction execution result grabbed in the pipeline by the pipeline monitoring unit into a tracking log file through a table format.
8. The validation method of claim 6 wherein the pipeline monitoring unit gathers instruction processing information of the core by way of hierarchical referencing.
9. The authentication method of claim 8, wherein the instruction processing information includes instruction dispatch information, instruction commit information, and instruction write back information.
10. The method of claim 8, wherein the pipeline monitor unit temporarily stores and reorders the instruction processing information, and issues the instruction execution results in the order of instruction stream after the instruction write back is completed.
11. The authentication method of claim 10, wherein the authentication method further comprises:
and displaying the instruction execution result in a waveform form, and positioning errors in the simulation verification process according to the instruction execution result.
12. A processor verification system, characterized by:
the processor verification system is configured to perform the verification method of any one of the processors as claimed in claims 1-11.
13. A storage medium storing a computer program, characterized by:
the computer program for performing the authentication method of any of the processors as claimed in claims 1-11.
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| CN202310358598.0A CN116450430A (en) | 2023-03-30 | 2023-03-30 | Verification method, verification system and storage medium for processor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117827563A (en) * | 2023-12-29 | 2024-04-05 | 深圳博瑞晶芯科技有限公司 | Processor function verification method, device and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117827563A (en) * | 2023-12-29 | 2024-04-05 | 深圳博瑞晶芯科技有限公司 | Processor function verification method, device and medium |
| CN117827563B (en) * | 2023-12-29 | 2024-11-05 | 深圳博瑞晶芯科技有限公司 | Processor function verification method, device and medium |
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