CN116435276A

CN116435276A - Semiconductor packaging structure and manufacturing method thereof

Info

Publication number: CN116435276A
Application number: CN202211643021.6A
Authority: CN
Inventors: 万亮
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2022-09-27
Filing date: 2022-12-20
Publication date: 2023-07-14
Also published as: CN116130440A

Abstract

A semiconductor package structure and a method of fabricating the same are disclosed. The semiconductor package structure has a conductive rewiring layer, a soldering layer, a corrosion barrier layer and an insulating layer. The corrosion barrier layer is used to completely cover the solder layer and the conductive rewiring layer and form a dense contact. An insulating layer is formed on the top surface of the passivation layer for separating the corresponding corrosion barrier under each conductive bump from the corrosion barrier under other adjacent conductive bumps. Because the top surface of the corrosion barrier layer is not coated with the insulating layer, the area for manufacturing the conductive salient points on the corrosion barrier layer is large, and the requirement of larger current can be met. In addition, the corrosion barrier layer can also be used as a welding adhesive layer during conductive convex point welding, so that the process steps are reduced.

Description

Semiconductor packaging structure and manufacturing method thereof

Technical Field

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor package structure and a method of manufacturing the same that improve reliability and a soldering area of the semiconductor device.

Background

Along with the continuous increase of the power density of the power chip, the current capability requirement of the single chip to be carried is higher and higher, and correspondingly, the diameter of the bonding wire is required to be thickened continuously so as to meet the requirements of high current and low resistance.

The introduction of the rewiring layer improves the flexibility of the welding position well, and solves the welding quality problems caused by the thick wire diameter, such as the cracking of the aluminum layer and the substrate crater. However, in the high-temperature and high-humidity environment, copper metal of the rewiring layer is easy to form copper dendritic bulges due to electrochemical corrosion, so that electric leakage and even short circuit are caused, and serious reliability risks exist.

The insulating layer covers the surface of the rewiring layer, so that the electrochemical corrosion risk can be effectively reduced, but the insulating layer can cover part of the surface of the rewiring layer, the solderable area is reduced, and meanwhile, the measurement effect of ball pushing projects in solder ball quality inspection can be influenced.

Disclosure of Invention

The present invention is directed to one or more of the problems of the prior art, and provides a semiconductor package structure and a method of manufacturing the same.

A first aspect of the present invention proposes a semiconductor package structure, comprising: a semiconductor substrate including at least one conductive pad formed thereon; a passivation layer covering the semiconductor substrate; a plurality of vias, each via passing through the passivation layer until a portion of the conductive pad is exposed; a conductive rewiring layer filling the plurality of through holes and covering a portion of the passivation layer; a soldering layer formed on the top surface of the conductive rewiring layer; and a corrosion barrier layer completely covering the top surface and the side surface of the soldering layer and the side surface of the conductive rewiring layer, and extending outwards from the root of the side surface of the conductive rewiring layer to cover the top surface of a part of the passivation layer, wherein the width of the corrosion barrier layer extending outwards on the top surface of the passivation layer is a first width.

A second aspect of the present application proposes a method for manufacturing a semiconductor device, including: manufacturing a passivation layer on a semiconductor substrate; manufacturing a plurality of through holes in the passivation layer; forming a conductive rewiring layer filling the plurality of through holes and covering a portion of the passivation layer; manufacturing a welding layer on the top surface of the conductive rewiring layer; and forming an etch stop layer on the top and side surfaces of the solder layer, the side surface of the conductive rewiring layer, and the top surface of the passivation layer adjacent to the side root portion of the conductive rewiring layer, wherein the etch stop layer has a first width extending outwardly from the side root portion of the conductive rewiring layer on the top surface of the passivation layer.

The semiconductor packaging structure provided by the invention has the advantages of high reliability, large welding area, convenience for use in high-current occasions, high reliability and simple process steps.

Drawings

Fig. 1 illustrates a semiconductor package structure 100 according to one embodiment of the invention.

Fig. 2A-2O are flow diagrams illustrating a packaging method for fabricating the semiconductor device 100 according to one embodiment of the present disclosure.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings are provided for the purpose of illustrating embodiments, concepts, etc. and are not drawn to scale.

Icon: 100-a semiconductor package structure; 101-comprising a semiconductor substrate; 102-conductive pads; 103-a passivation layer; 104-through holes; 105-an under bump metallization layer; 106-rewiring layer; 107-a corrosion barrier; 108-an insulating layer; a solder layer 112 and a conductive bump 113.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention. The terms "first," "second," and the like, if any, are used solely for distinguishing between descriptions and should not be construed as indicating or implying a relative importance.

Furthermore, references to "one embodiment," "an embodiment," "one example," or "an example" throughout this specification mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

Fig. 1 provides a semiconductor package structure 100 according to one embodiment of the present invention. Fig. 1 is a schematic cross-sectional view of a semiconductor package 100. The semiconductor package 100 includes a semiconductor substrate 101, a plurality of conductive pads (top metal) 102, a passivation layer 103, a via 104, a conductive under bump metallization (Under Bump Metallization, UBM) 105, a conductive rewiring layer (Redistribution Layer, RDL) 106, a solder layer 112, a corrosion barrier layer 107, and an insulating layer 108. In one embodiment, the semiconductor package 100 further includes conductive bumps 113 made by wire bonding.

Included in the semiconductor substrate 101 is an integrated circuit chip that contains active and passive circuit elements that may include transistors, resistors, diodes, capacitors, inductors, current sources, voltage sources, and other suitable circuit elements. The transistors may include, for example, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), bipolar Junction Transistors (BJTs), junction Field Effect Transistors (JFETs), insulated Gate Bipolar Transistors (IGBTs), double diffused metal oxide semiconductor transistors (DMOS), and the like. These circuit elements are coupled to each other to form integrated circuit chips having different functions, such as logic circuits, power conversion circuits, memory circuits (e.g., random access memory circuits, static random access memory circuits, etc.), input/output circuits, integrated systems on chip, and other suitable circuits.

The semiconductor substrate 101 may be referred to as a substrate comprising a semiconductor material including, but not limited to, bulk silicon, doped silicon, silicon germanium (SiGe), silicon-on-insulator (SOI), and other suitable semiconductor materials.

Isolation structures may also be fabricated in the semiconductor substrate 101 for isolating different circuit elements or integrated circuits of different functions in the semiconductor substrate 101.

The semiconductor substrate 101 also includes a top metal layer overlying the integrated circuit chip formed in the semiconductor substrate 101. The top metal layer may be patterned to form a plurality of conductive pads 102. The conductive pads 102 are for coupling to different circuit elements and/or different circuit nodes in the integrated circuit chip in the semiconductor substrate 101 so that these different circuit elements and/or different circuit nodes can receive or transmit signals or be coupled to a supply node or ground, etc. The material used to make the top layer metal may include one or a combination of metals such as aluminum, copper, silver, gold, nickel, tungsten, and the like. Each conductive pad 102 may have an exposed surface that may be subjected to a planarization process (e.g., a mechanochemical polishing process), if necessary.

Those skilled in the art will appreciate that hundreds or thousands or even more conductive pads 102 may be fabricated on the semiconductor substrate 101. Conductive pads 102 may be grouped by function. For example, those conductive pads 102 having similar or identical functions may be grouped together. Meanwhile, it is not necessary to divide all the conductive pads 102 having the similar or identical function into only one group, but they may be divided into plural groups, for example, those conductive pads 102 having the similar or identical function that are relatively adjacent in arrangement position may be divided into one group, and others conductive pads 102 having the similar or identical function that are relatively adjacent in arrangement position may be divided into another group. By adopting the technical scheme of the embodiment of the disclosure, the position arrangement of the plurality of conductive pads 102 in the semiconductor package structure 100 can be more flexible, and the communication resistance of the conductive path formed from the conductive pads 102 to the conductive bumps is lower, so that the current processing capability is improved.

The top of the semiconductor substrate 101 is covered with a passivation layer 103 for insulation protection. The passivation layer 103 covers the entire semiconductor substrate 101 and the conductive pad 102 on the upper surface thereof. A plurality of vias 104 may be made in the passivation layer. The plurality of vias corresponds to each conductive pad 102 such that the conductive pad is at least partially exposed so that the conductive pad 102 may be connected out in a later process step. In one embodiment, the via 104 may be fabricated by forming a patterned opening through a laser grooving process.

A UBM layer 105 is fabricated over the corresponding portions of passivation layer 103 for each set of conductive pads 102 and over the sidewalls and bottom of each via 104. UBM layer 105 is a metallization transition layer between conductive pad 102 and a conductive bump, and mainly functions as adhesion and diffusion barrier, and is typically composed of multiple metal films such as an adhesion layer, a diffusion barrier layer, and a wetting layer. The UBM layer 105 may be formed by sputtering, evaporation, electroless plating, electroplating a conductive material, and the like. UBM layer 105 needs to have a sufficiently good adhesion to conductive pad 102 and passivation layer 103 for protecting conductive pad 102 during subsequent processing steps and maintaining a low contact resistance between conductive pad 102 and conductive bump 113, while acting as an effective diffusion barrier between conductive pad 102 and conductive bump 113, and also as a seed layer for solder bump or metal bump deposition for providing a conductive path for subsequent fabrication of RDL layer 106.

Over UBM layer 105 is RDL layer 106.RDL layer 106 fills vias 104 on conductive pads 102 and covers UBM layer 105 over conductive pads 102. In one embodiment, RDL layer 106 may comprise copper (Cu) and have a thickness. The thickness can be selected according to practical application requirements. RDL layer 106 is used to change the original contact locations (conductive pads 102) of the chip through a wafer level metal routing process, enabling the chip to be adapted for different package styles.

On top of RDL layer 106 is a solder layer 112. In one embodiment, the weld layer 112 includes other suitable metals such as nickel (Ni). In one embodiment, the thickness of the solder layer 112 is 1 micrometer (μm) to 3 μm.

In a semiconductor device, as the spacing between different RDL layers 106 continues to decrease, electrical shorts are likely to result between adjacent RDL layers 106 corresponding to different sets of conductive pads 102. Thus, to further ensure device reliability and long life requirements, in embodiments of the present disclosure, a corrosion barrier layer 107 will be formed on top and sides of the solder layer 112, sides of the RDL layer 106, and portions of the passivation layer 103 adjacent to the sides root of the RDL layer 106. The etch stop layer 107 completely encapsulates the top and side surfaces of the solder layer 112 and the side surfaces of the RDL layer 106 and extends outwardly from the side root of the RDL layer 106 to cover a portion of the top surface of the adjacent passivation layer 103 such that the etch stop layer 107 and the RDL layer 106 form a dense contact. The width of the etch stop layer 107 extending outwardly from the lateral root of RDL layer 106 at the top surface of passivation layer 103 is illustrated as a first width d1. In one embodiment, the first width d1 may be selected to be a suitable width based on the process steps and process level sufficient to form a dense contact between the etch stop layer 107 and the RDL layer 106. Dense contact means that no gaps at all exist between the etch stop layer 107 and the RDL layer 106. Because the corrosion barrier layer 107 extends from the root of the side surface of the RDL layer 106 to a part of the passivation layer 103, the RDL layer 106 cannot diffuse out through any gaps to form whiskers even at the root of the side surface, thereby avoiding the corroded channel of the RDL layer 106, meeting the requirements of high reliability and long service life, and especially realizing zero risk of devices in a high-humidity environment.

In one embodiment, a corrosion barrier layer 107 may be formed by sputtering an inert metal on the top and side surfaces of the solder layer 112, the side surfaces of the RDL layer 106, and portions of the passivation layer 103 adjacent the root of the side surfaces of the RDL layer 106 to form a dense protection for the RDL layer 106. The etch stop layer 107 is formed by a sputtering process without additional process equipment, and only by conventional sputtering steps in semiconductor fabrication processes, without special process control and risk. In addition, the thickness of the corrosion barrier layer 107 is easy to control by adopting a sputtering process, and a thinner corrosion barrier layer 107 can be formed, so that the influence on the size and the spacing of the RDL layer 106 is very small, and the process consistency is good and the yield is high. For example, in one embodiment, the thickness of the corrosion barrier layer 107 is 0.1 μm to 0.5 μm. In other processes, such as chemical plating, the thickness uniformity of the plated layer of the positive wafer is generally more than 1-2 μm.

In one embodiment, the corrosion barrier layer 107 may be made of an electrochemical corrosion resistant metal, such as titanium (Ti), chromium (Cr), nickel (Ni), or gold (Au).

After the formation of the etch stop layer 107, the conductive bump 113 may be formed directly on the etch stop layer 107. In one embodiment, the conductive bumps 113 comprise solder balls, which may be formed directly on the etch stop layer 107 using a wire bonding process. One of ordinary skill in the art will appreciate that the wire bonding process is to burn one end of a wire used to connect the chip and the leadframe into a ball shape. In the embodiment disclosed herein, the ball shape formed by firing one end of the metal wire is a solder ball, and may be directly soldered on the corrosion barrier layer 107.

The solder balls are coupled to the set of conductive pads 102 through the etch stop layer 107, the solder layer 112, the RDL layer 106, and the vias 104. The conductive pads 102 on the semiconductor substrate 101 are coupled to corresponding contact areas or pins on the package lead frame, package base or circuit motherboard, respectively, by solder balls, so that the semiconductor substrate 101 will be mounted or bonded to the package lead frame, package base or circuit motherboard, etc. by a wire-bonding packaging process. In one embodiment, the corrosion barrier layer 107 may also serve as a solder bond layer during solder ball soldering, eliminating the outermost metal layer required for surface layer processing in the case of conventional RDL layers 106 used in a wire bonding process. In other words, the etch stop layer 107 replaces the outermost metal layer required for the surfacing process in the case of conventional RDL layers 106 for the wire bonding process.

In one embodiment, the semiconductor package structure 100 further includes an insulating layer 108 formed on the passivation layer 103. The insulating layer 108 separates the corresponding etch stop layer 107 under each conductive bump 113 from the etch stop layer 107 under other adjacent conductive bumps 113. Meanwhile, in order to further enhance the reliability of the semiconductor package structure 100, a gap is left between the insulating layer 108 and the corrosion barrier layer 107, so that the corresponding corrosion barrier layer 107 under each conductive bump 113 is better separated from the corrosion barrier layer 107 under other adjacent conductive bumps 113. In the embodiment shown in fig. 1, the void width, which is the linear distance of the side of the etch stop layer 107 from the adjacent insulating layer 108, is illustrated as a second width d2. In the embodiment shown in fig. 1, the second width d2 is greater than the first width d1. In one embodiment, the insulating layer 108 comprises spin-on glass (SOG), a flowable oxide, an organic material, or other suitable material having a low dopant diffusivity. In the embodiment disclosed in the present application, since the top surface of the corrosion barrier layer 107 is not coated with an insulating layer, the area for manufacturing solder balls on the corrosion barrier layer 107 is very large, and a wire with a thicker wire diameter of the bonding wire can be selected in practical application to meet the requirement of high current, while for the same wire diameter of the bonding wire, the embodiment disclosed in the present application can be designed to have a smaller size to meet the requirement.

Next, a packaging method for fabricating a semiconductor device (e.g., the semiconductor package structure 100 mentioned in the above embodiments) will be described according to one embodiment of the present disclosure. Fig. 2A to 2O show a schematic flow diagram of the middle stage of the encapsulation method. It should be understood by those skilled in the art that the cross-sectional views of fig. 2A through 2O illustrate only a partial flow of the semiconductor package 100.

Referring to the illustration of fig. 2A, a via 104 is fabricated in a passivation layer 103 in a prepared semiconductor substrate 101. The vias 104 extend longitudinally from the upper surface of the passivation layer 103 to the conductive pads 102, each via 104 passing through an underlying portion of the passivation layer 103 until at least a portion of the underlying conductive pad 102 is exposed. The plurality of vias 104 may expose portions of the conductive pad 102.

Referring next to fig. 2B, an insulating layer 108 is coated on the plurality of via holes 104 and the passivation layer 103. The insulating layer 108 fills each of the vias 104 up to a certain thickness on the passivation layer 103. The insulating layer 108 is typically Polyimide (PI) or poly-p-Phenylene Benzobisoxazole (PBO).

Referring then to fig. 2C, the insulating layer 108 is exposed and developed. The insulating layer 108 over the conductive pad 102 is removed.

Referring next to fig. 2D, UBM layer 105 is fabricated on the upper surface of passivation layer 103, the upper surface and sides of insulating layer 108, and the sidewalls and bottom of each via 104. UBM layer 105 is typically copper, titanium, or a copper-titanium alloy, such as titanium Tungsten (TiW), titanium copper (TiCu), nickel titanium (TiNi), or the like, having a thickness of 0.3 micrometers (μm) to 0.5 μm.

With continued reference to fig. 2E, a first photoresist layer PR1 is coated on the upper surface of the prepared UBM layer 105.

With continued reference to fig. 2F, the first photoresist layer PR1 is exposed and development patterned to expose the UBM layer 105 under the conductive bump 113. Note that the first photoresist layer PR1 remaining after exposing and developing the patterning will cover the UBM layer 105 on the side of the insulating layer 108 and a portion of the UBM layer 105 on the passivation layer 103 adjacent to the root of the side of the insulating layer 108, in addition to the UBM layer 105 surrounding the top of the insulating layer 108.

With continued reference to fig. 2G, an RDL layer 106 is fabricated on the exposed UBM metal layer 105, the RDL layer 106 filling each via 104 and up to a certain thickness on the UBM layer 105. In one embodiment, the thickness may be 1 μm to 20 μm. For example, in one embodiment, the thickness of RDL layer 106 may be 5 μm to 20 μm. In another embodiment, the thickness may be 1 μm to 30 μm.

With continued reference to fig. 2H, a solder layer 112 is fabricated on top of RDL layer 106.

With continued reference to fig. 2I, the first photoresist layer PR1 is stripped and exposes UBM layer 105 on the top and side surfaces of insulating layer 108 and UBM layer 105 on the top surface of passivation layer 103.

With continued reference to fig. 2J, UBM layer 105 is etched away, exposing insulating layer 108 and a portion of passivation layer 103.

Referring next to fig. 2K, an etch stop layer 107 is formed on the semiconductor structure prepared in fig. 2J, wherein the etch stop layer 107 completely covers the top surface of the entire semiconductor structure, i.e.: completely encapsulating the top and side surfaces of the solder layer 112, the side surfaces of the RDL layer 106, and the surface of the passivation layer 103. In this step, the etch stop layer 107 may be formed using a sputtering process. In this step, the corrosion barrier layer 107 is made of a material resistant to electrochemical corrosion, such as titanium (Ti), chromium (Cr), nickel (Ni), or gold (Au). In one embodiment, the thickness of the corrosion barrier layer 107 is 0.1 μm to 0.5 μm, for example 0.4 μm.

Referring to fig. 2L, a second photoresist layer PR2 is then coated on the upper surface of the semiconductor device formed in fig. 2K.

Subsequently referring to fig. 2M, the second photoresist layer PR2 is exposed and development patterned such that the etch stop layer 107 on the top surface of the insulating layer 108 and a portion of the etch stop layer 107 on the top surface of the passivation layer 103 are exposed.

With continued reference to fig. 2N, the exposed etch stop layer 107 is etched away.

Referring then to fig. 2O, the second photoresist layer PR2 is stripped off, exposing the etch stop layer 107. After the etch stop layer 107 is formed, a wire bonding process may be directly used to form solder balls on top of the etch stop layer 107.

The present disclosure provides semiconductor devices including conductive bumps formed on a rewiring layer and related methods of fabricating semiconductor devices, although some embodiments of the invention are described in detail, it should be understood that these embodiments are for illustration only and are not intended to limit the scope of the invention. Other possible alternative embodiments will be apparent to those of ordinary skill in the art from reading this disclosure.

Claims

1. A semiconductor package structure, the package structure comprising:

a semiconductor substrate including at least one conductive pad formed thereon;

a passivation layer covering the semiconductor substrate;

a plurality of vias, each via passing through the passivation layer until a portion of the conductive pad is exposed;

a conductive rewiring layer filling the plurality of through holes and covering a portion of the passivation layer;

a soldering layer formed on the top surface of the conductive rewiring layer; and

and the corrosion barrier layer completely covers the top surface and the side surface of the welding layer and the side surface of the conductive rewiring layer, and extends outwards from the root part of the side surface of the conductive rewiring layer to cover the top surface of part of the passivation layer, wherein the outwards extending width of the corrosion barrier layer on the top surface of the passivation layer is a first width.

2. The package structure of claim 1, further comprising at least one conductive bump formed on a top surface of the corrosion barrier layer.

3. The package structure of claim 2, wherein the package structure further comprises:

and the insulating layer is formed on the top surface of the passivation layer and is used for separating the corresponding corrosion barrier layer under each conductive bump from the corrosion barrier layers under other adjacent conductive bumps.

4. The package of claim 3, wherein the corrosion barrier layer on the side of the conductive rewiring layer has a void with an adjacent insulating layer, the void having a second width, wherein the second width is greater than the first width.

5. The package structure of claim 2, wherein the conductive bumps comprise solder balls.

6. The package structure of claim 1, wherein the corrosion barrier layer has a thickness of 0.1 microns to 0.5 microns.

7. The package structure of claim 1, wherein the solder layer comprises nickel.

8. The package structure of claim 1, wherein the package structure further comprises:

and the under bump metal layer is covered on the passivation layer right below the conductive rewiring layer and the side walls and the bottoms of the through holes.

9. A method of fabricating a semiconductor device, the method comprising:

manufacturing a passivation layer on a semiconductor substrate;

manufacturing a plurality of through holes in the passivation layer;

forming a conductive rewiring layer filling the plurality of through holes and covering a portion of the passivation layer;

manufacturing a welding layer on the top surface of the conductive rewiring layer; and

and forming an etch stop layer on the top and side surfaces of the solder layer, the side surface of the conductive rewiring layer, and the top surface of the passivation layer adjacent to the side root of the conductive rewiring layer, wherein the etch stop layer has a first width extending outwardly from the side root of the conductive rewiring layer on the top surface of the passivation layer.

10. The method of manufacturing of claim 9, wherein the method of manufacturing further comprises:

and forming a conductive bump on a top surface of the corrosion barrier layer, wherein the conductive bump comprises a solder ball coupled to at least one conductive pad in the semiconductor substrate through the plurality of vias.

11. The method of manufacturing of claim 10, further comprising:

and forming an insulating layer on the top surface of the passivation layer, wherein the insulating layer is used for separating the corrosion barrier layer on the side surface of the conductive rewiring layer from an adjacent insulating layer by a second width, and the second width is larger than the first width.

12. The method of manufacturing of claim 10, wherein forming a corrosion barrier layer on the top and side surfaces of the solder layer, the side surface of the conductive rewiring layer, and the top surface of the passivation layer adjacent the root of the side surface of the conductive rewiring layer comprises:

forming a corrosion barrier layer on the top and side surfaces of the insulating layer, the top and side surfaces of the passivation layer, the top and side surfaces of the solder layer, and the side surface of the conductive rewiring layer; and

etching away the corrosion barrier layer on the top surface and the side surface of the insulating layer and the top surface of the passivation layer adjacent to the root of the side surface of the insulating layer.