CN116414682A - Program testing method and device, electronic equipment and storage medium - Google Patents
Program testing method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The program testing method, device, electronic equipment and storage medium provided by the application are applied to the technical field of computers, and the method comprises the following steps: when a test program is run on a tested device provided with a processor, a terminal monitors device information of the tested device under the condition that the execution state of the tested device is not changed through a target register corresponding to a debugging interface of the processor; the terminal writes an execution instruction carrying an exception handling address in a debugging interface of the processor so that the processor executes the execution instruction; when the abnormal processing address exists in the equipment information, acquiring process information from a debugging interface of the processor so that the processor operates normally; and carrying out test analysis on the equipment information and the process information. The method and the device reduce the time of the processor in an abnormal state in the testing process of the program as much as possible, thereby reducing the influence on the normal operation of the processor.
Description
Technical Field
The application belongs to the technical field of computers, and particularly relates to a program testing method, a program testing device, electronic equipment and a storage medium.
Background
In general, software needs to be debugged and performance optimized in a software development stage, or when an operating system is abnormal, information such as registers, processes and the like needs to be analyzed. However, when software is debugged, especially for release version software, the software does not have integrated debugging functions, and the debugging is very difficult. Some debug interfaces may be included in the processor for enabling debugging of the processor, common debug interfaces such as JTAG (Joint Test Action Group ) debug interfaces and EJTAG (Enhanced Joint Test Action Group ) debug interfaces.
In the prior art, during the process of debugging a processor, different debugging methods are determined according to different protocols followed by a debugging interface. For some debug interfaces, there is a state where when the processor enters a debug mode (i.e. a state in which the processor is debugged), the processor core will cease to operate until the debug mode is over, and the processor core will return to a normal operating state. The debugging method by using the EJTAG interface is that the processor is controlled to enter an EJTAG abnormal state by repeatedly accessing three registers, namely ADDRESS register, DATA register and CONTROL register, corresponding to the EJTAG interface in the processor, then equipment information when the processor enters the abnormal state is acquired in the EJTAG dmseg (fault register), and after the equipment information acquisition is completed, the processor is controlled to exit the EJTAG abnormal state and return to a position before the EJTAG abnormal state to continue the normal operation flow.
However, in the existing debugging mode, the process of reading the equipment information from the EJTAG dmseg can enable the processor to be in an EJTAG abnormal state for a long time, so that indexes such as a central processing unit TIMER (CPU TIMER) of the processor deviate from actual conditions, and deviation exists between obtained test data and data when the program runs truly, and accuracy of program analysis is affected.
Disclosure of Invention
In view of this, the embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for testing a program, which are used to solve the problem that in the prior art, in the process of reading device information from dmseg space, a processor is in an EJTAG abnormal state for a long time, so that indexes such as a CPU TIMER of the processor deviate from actual conditions, resulting in deviation between obtained test data and data when the program runs actually, thereby affecting accuracy of program analysis.
A first aspect of the present application provides a method for testing a program, the method comprising:
when a test program is run on a tested device provided with a processor, a terminal monitors device information of the tested device under the condition that the execution state of the tested device is not changed through a target register corresponding to a debugging interface of the processor;
the terminal writes an execution instruction carrying an exception handling address in a debugging interface of the processor so that the processor executes the execution instruction;
when the abnormal processing address exists in the equipment information, acquiring process information from a debugging interface of the processor so that the processor operates normally;
and carrying out test analysis on the equipment information and the process information.
Optionally, the target register includes: the PC sampling register, the terminal monitors the device information of the tested device under the condition of not changing the execution state of the tested device through a target register corresponding to a debugging interface of the processor, and the PC sampling register comprises:
and the terminal monitors the equipment information of the tested equipment under the condition of not changing the execution state of the tested equipment through a PC sampling register corresponding to the debugging interface of the processor.
Optionally, the performing test analysis on the device information and the process information includes:
dividing the process information into target process information corresponding to each process;
and acquiring a process function corresponding to the target process information meeting the test requirement, and taking the acquired process function as an analysis result.
Optionally, the dividing the process information into target process information corresponding to each process includes:
and under the condition that the test program adopts a memory management unit to switch the process, dividing the process information according to the breakpoint in the equipment information to obtain target process information corresponding to each process, wherein the execution code of the breakpoint is preset in a process switching function of the program.
Optionally, the dividing the process information into target process information corresponding to each process includes:
and under the condition that the test program does not adopt a memory management unit to switch the process, analyzing the process number in the equipment information to divide the process information so as to obtain target process information corresponding to each process.
Optionally, when the debug interface support window is configured to memory, the execution instructions are configured to map the exception handling address window to a memory address location.
Optionally, when the debug interface does not support window configuration to memory, the execution instructions are configured to instruct the processor to jump to memory access the exception handling address.
According to a second aspect of the present application, there is provided a testing device for a program, the device comprising:
the monitoring module is configured to enable a terminal to monitor equipment information of the tested equipment under the condition that the execution state of the tested equipment is not changed through a target register corresponding to a debugging interface of a processor when a test program is run on the tested equipment provided with the processor;
the writing module is configured to enable the terminal to write an execution instruction carrying an exception handling address in a debugging interface of the processor so that the processor executes the execution instruction;
the acquisition module is configured to acquire process information from a debugging interface of the processor when the presence of the exception handling address in the equipment information is detected, so that the processor operates normally;
and the analysis module is configured to perform test analysis on the equipment information and the process information.
According to a third aspect of the present application, there is provided an electronic device comprising a processor, a memory, and a program or instruction stored on the memory and executable on the processor, the program or instruction when executed by the processor implementing the method for testing the program according to the first aspect.
According to a fourth aspect of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of testing the program according to the first aspect described above.
Aiming at the prior art, the application has the following advantages:
the utility model provides a test method, a device, electronic equipment and a storage medium of program, this scheme is in the in-process of processor operation program, through the target register that the debugging interface of processor corresponds under the circumstances that does not interrupt the normal operating condition of processor, and thereby confirm that the processor gets into abnormal state and obtain process information from the debugging interface when monitoring to the equipment information contains unusual access address, make the equipment under test normal operating, and supply the equipment information and the process information that obtain to test analysis use, reduce the time that the processor is in abnormal state in the test process of program as far as, thereby alleviateed the influence to the normal operating of processor.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a hardware debug connection provided in an embodiment of the present application;
FIG. 2 is a standard state machine transition diagram for JTAG provided by embodiments of the present application;
FIG. 3 is a flow chart of steps of a testing method of a program according to an embodiment of the present application;
FIG. 4 is a flow chart of steps of a testing method of another program according to an embodiment of the present application;
fig. 5 is a block diagram of a testing device for a program according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
FIG. 1 is a schematic diagram of a hardware debug connection, where terminals are connected to a processor being debugged through an emulator. The program codes are compiled at the terminal, and the compiled generated codes are downloaded into the memory of the processor through the simulator.
As shown in fig. 1, the aforementioned terminal may be a Debug host, which is connected to a test access port channel (TAP access, test Access Port access) through an Ethernet (Ethernet) and/or RS-232 (asynchronous transfer standard interface) or the like, and in a specific implementation, the test access port channel may be an EJTAG emulator for EJTAG probing (EJTAG probe) and connected to a System Prototype (System Prototype) through a JTAG test access port type interface (JTAG TAP interface), wherein in the System Prototype, other System logic (Other System Logic) is connected to a System On Chip (SOC, system On Chip), an application specific integrated circuit (ASIC, application Specific Integrated Circuit) and/or a special standard product (ASSP, application Specific Standard Parts) through a JTAG scan chain (JTAG scan chain); the system on chip, the application specific integrated circuit or the special standard product is a system on chip, an application specific integrated circuit and/or a special standard product respectively comprising a central processing unit (such as a CPU with EJTAG) with a debugging interface.
To illustrate the debugging process of the processor, consider EJTAG boundary testing as an example, and the debugging implementation details of the processor are described herein.
The EJTAG standard is based on the JTAG standard, and three registers, namely an ADDRESS (ADDRESS), a DATA (DATA) and a CONTROL (CONTROL), are added to CONTROL and record the state of the processor. FIG. 2 is a diagram of a standard state machine transition of JTAG, in which TAP access plays an important role, and control of TAP access is accomplished by a TAP controller; the TAP controller mainly comprises four logic signals, namely a TCK signal (clock signal), a TMS signal (transition signal of a state machine), a TDI signal and a TDO signal (input and output signals), wherein the three logic signals of the TMS signal, the TDI signal and the TDO signal need to be kept synchronous with the TCK signal, namely, each bit of data is driven to be input from TDI according to the beat of the TCK signal, and each bit of data is driven to be output from TDO; each TAP controller accesses two types of registers, IR (instruction register) and DR (data register), respectively, the Data Register (DR) is used for monitoring and controlling the input and output of the processor, and the Instruction Register (IR) is used for realizing control of the data register, for example, a data register determined according to instructions in the instruction register is included between a TDI signal pin and a TDO signal pin.
In fig. 2, 16 synchronization state transition mechanisms of the TAP controller are shown, each of which is described below. In the following, the low level is represented by 0, and the high level is represented by 1. Firstly, after the system is powered on, the TAP controller enters a Test-Logic-Reset state (Test Logic Reset state); then, the TAP controller takes the test logic reset state as a starting point, and jumps to a corresponding intermediate state according to the fact that the TMS signal is in a high level/low level (shown by an arrow mark in FIG. 2 in detail) when the TCK signal rises; in each intermediate state, the TAP controller jumps to the next state until reaching the end state, according to the TMS signal being at high/low level at the rising edge of the TCK signal. Among them, the intermediate states and end states that the TAP controller can jump include Run-Test/Idle, select-DR-Scan, capture-DR, shift-DR, exit-DR, pause-data register, exit2-DR, update-DR, select-IR-Scan, capture-register, shift-instruction register, exit-IR, update-IR, and Pause-IR.
In this embodiment, the processor configures the control register, the address register and the data register for the debug interface locally, and the terminal can directly access the three registers through the debug interface. Wherein, the first appointed position in the control register contains whether the processor has an access request to send to the fault register of the debugging interface; the second designated bit in the control register contains whether the access request sent by the processor is a read request or a write request; the third designated bit in the control register contains the read-write width of the access request; the first, second and third pointing positions are preset according to actual conditions. Illustratively, PRACC (bit 18) of the control register is the first designated bit, PRnW (bit 19) of the control register is the second designated bit, and Psz bits of the control register is the third designated bit. The data register is used for storing data/instructions; the address register is used to store the address of an access instruction (read instruction/write instruction).
Fig. 3 is a flowchart of steps of a testing method of a program, where the method is applied to a process of testing (or called debugging) a processor, the processor includes a debug interface, and a target register configured for the debug interface is included in the processor, and includes:
In the embodiment of the application, the target register refers to a register that reads device information in the process of running a test program by the processor before the processor enters an abnormal state, that is, the target register stores the device information of the tested device; the read process of the target register does not interrupt the normal operation of the test program. The device information refers to information in a PC register of the tested device, and the PC register is used for storing an instruction address required to be executed by the tested device. Optionally, the test program is a preset program for performing various function tests on the processor; in particular, the test program may be a program executed by the processor at high frequency.
Compared with the prior art that the processor is in a debugging abnormal (such as EJTAG abnormal) state and then accesses the fault state register to read the equipment information, the processor can continue to normally operate after exiting the debugging abnormal state, so that the processor is in the abnormal state for a long time; according to the method and the device for processing the equipment information, before the processor enters the debugging abnormal state, the control target register continuously reads the equipment information, so that the reading efficiency of the equipment information can be effectively improved, the time that the processor is in the debugging abnormal state is shortened, and the influence on normal operation of the processor is reduced as much as possible.
In the embodiment of the application, the exception handling address is an address which is accessed by the processor when entering a debug exception and is mapped to a debug interface. When the test program runs, the terminal can trigger the debugging exception through the debugging interface, or the processor encounters a breakpoint instruction to enter the debugging exception when executing. The processor may access the address mapped to the debug interface when executing the debug exception, requesting to read instructions or store data from the exception handling address that needs to be accessed. At this time, the simulator provides the execution instruction or data corresponding to the exception handling address to the debug interface, so that the processor obtains the device information and the process information of the processor entering the exception state according to the execution instruction, and the device information and the process information are used together for debugging analysis of the processor.
Optionally, the processor generating the debug exception scenario includes: the processor executes the test program to meet the preset breakpoint; or setting the break bit in the control register corresponding to the debug interface as an abnormal value, wherein the abnormal value is a value which enters a debug abnormal state when the processor executes to a specified position of the test program.
Specifically, when the processor is abnormal in debugging, the processor is provided with two abnormal vector entry addresses, the abnormal vector entry addresses are determined by abnormal bits of a control register corresponding to the debugging interface, and the abnormal bits are preset positions used for representing abnormal conditions according to actual conditions; when the exception bit is 1, the exception vector entry address is indicated as a first address; when the exception bit is 0, it indicates that the exception vector entry address is the second address. Illustratively, the exception bit may be ProbeTrap (bit 14 in the control register), which when ProbeTrap is 1, indicates that the first address is 0xff200200,0xff200200 is in the fault register; when ProbeTrap is 0, it indicates that the second address is 0xbfc00000.
Further, probetrap= 1, the processor obtains the execution instruction from 0xff200200, at this time, the terminal writes the execution instruction into the data register corresponding to the debug interface, clears the first designated bit in the control register, and the processor removes the execution instruction. Probetrap= =0, the processor gets the execution instruction from 0xbfc 00000; when the second method is adopted, the 0xbfc00000 can acquire the execution instruction through the window mapping to the memory, the execution instruction can be acquired from the local place, and the processor and the terminal do not need to interact through the debugging interface, so that the speed of acquiring the execution instruction is higher.
Optionally, when the processor accesses the abnormal address range determined by the first address, the processor is realized through the debugging interface; specifically, the processor accesses the abnormal address range through a data register and/or a control register corresponding to the debug interface. Illustratively, the exception address range is 0xff200000-0xff300000.
When the abnormal vector entry is the second address, the processor can write the process information generated by the running of the test program to the starting address (such as 0xff 200000) of the fault register, and then read the process information from the starting address and write the process information into the data register, so that the terminal can acquire the process information from the debugging interface as returned test data, namely when the terminal reads the control register and finds that the abnormal bit is 1, the process information is read from the data register, and the first designated bit is set to 0 and then written into the control register; the debug mode returns from the second address, exits the exception, and the instruction that returned to the pre-exception continues execution.
By adopting the technical scheme, when the processor acquires the execution instruction from the 0xff200200, the processor needs to interact with the terminal through the debugging interface, so that the speed of acquiring the execution instruction is slower, and the program operation is discontinuous due to the too slow instruction acquisition speed, so that the operation condition of the test program is inconsistent with the actual operation condition, and the test result is inaccurate. Based on the above, when the processor adopts the instruction obtained from 0xbfc00000, the window mapping function is combined to map 0xbfc00000 to the memory address, so that the time interval between different instructions of the test program operation is reduced, the test program operation condition is consistent with the actual operation condition, and the test program is kept to continuously operate.
In the embodiment of the application, in the process of running the test program, the processor continuously reads the equipment information from the target register and detects whether an exception handling address exists in the equipment information, and the data register corresponding to the debugging interface can acquire the information read by the target register in real time; based on the method, the terminal can timely monitor that the corresponding abnormal access address exists in the process information acquired by the data register corresponding to the debugging interface, so that whether the processor enters an abnormal state or not can be timely determined. When the terminal detects that the device information has an abnormal processing address carried by an execution instruction written in the debugging interface, determining that the processor enters an abnormal state, at the moment, the terminal can acquire the process information of the processor from a data register in the debugging interface and transfer the process information and the read device information to the simulator, so that the abnormal state can be maintained on the simulator for subsequent analysis; and when the process information of the tested equipment does not have the exception handling address any more, the tested equipment can continue to execute the instruction before the execution instruction carrying the exception handling address so as to continue normal operation. Specifically, the exception handling address may be preset in the device information of the tested device by the tester according to the test requirement.
And 104, performing test analysis on the equipment information and the process information.
In the embodiment of the application, the terminal performs test analysis on the equipment information and the process information when the processor on the equipment to be tested enters the abnormal state, so as to debug the running performance of the test program on the processor.
According to the program testing method, the device information is monitored through the target register corresponding to the debugging interface of the processor under the condition that the normal operation of the processor is not interrupted, and when the monitored device information contains the abnormal access address, the processor is determined to enter the abnormal state so as to acquire the process information from the debugging interface, so that the tested device operates normally, the acquired device information and the process information are used for testing and analyzing, the time that the processor is in the abnormal state in the testing process of the program is reduced as much as possible, and therefore the influence on the normal operation of the processor is reduced.
Based on the above embodiments, fig. 4 is a flowchart illustrating steps of a testing method of another program according to an embodiment of the present application, where in the flowchart shown in fig. 4, the target register bit may be a PC SAMPLE register (PC SAMPLE register), and the method includes:
In the embodiment of the application, the PC sampling register is a register for periodically reading the equipment information of the tested equipment, which corresponds to the debugging interface; the terminal reads the PC SAMPLE register and the address register which are the same, and the execution of the test program is not interrupted.
This step may be described in detail with reference to step 102, and will not be described here again.
This step is described in detail with reference to step 103, and will not be described here.
And 204, dividing the process information into target process information corresponding to each process.
In the embodiment of the application, the process information read by the terminal may be various processes generated during the running of various different programs, such as a starting process, an updating process, a window opening process, and the like of the program; therefore, if the processes to which the process information belongs are not distinguished, the process with the problem cannot be found accurately, that is, for a certain process, in the abnormal operation process state, it is determined which part of the program in the test program is in operation, and the abnormal operation condition is caused by the corresponding process function error. The target process information is the process information corresponding to the process with the problem.
In this embodiment of the present application, the test requirement may be a determination condition obtained by defining, according to an actual debug requirement, process information of a required analysis result by setting an index condition.
Optionally, a function with a plurality of sampling times in the same process is determined as a hot spot function, and the hot spot function is used as an analysis result.
Optionally, the step 204 may include: and under the condition that the test program adopts a memory management unit to switch the process, dividing the process information according to the set breakpoint in the equipment information to obtain target process information corresponding to each process, wherein the execution code of the breakpoint is preset in a process switching function of the program.
In the embodiment of the present application, the memory management unit (MMU, memory Management Unit) is a control device for managing virtual memory and physical memory, and is also responsible for mapping virtual addresses to physical addresses, and providing a memory access authorization, multi-tasking and multi-process operating system for hardware mechanisms. Because the test program adopts the memory management unit to call the process switching function when the process is switched, the breakpoint can be set in the process switching function of the test program, and the execution code of the breakpoint can be executed in the execution process of the process switching function to read the process information; the specific location of the breakpoint setting may be a program code location indicated by an address in an identifier register (e.g., mtc entryhi register) of a process switch function (e.g., schedule function) that stores a virtual page number of an entered key and a currently active address space identifier.
Optionally, the step 204 may include: and under the condition that the test program does not adopt a memory management unit to switch the process, analyzing the process number in the equipment information to divide the process information so as to obtain target process information corresponding to each process.
In the embodiment of the application, if the test program does not adopt the memory management unit to switch the process, the terminal can obtain the process number of each process information by analyzing the process number in the processor core, so as to divide the process information. Specifically, when the process is switched, the operating system of the processor will increment the value in the count register, that is, the initial value in the count register is prid, and prid+1 is generated once for each process, so that the process number when the value in the count register changes can be used as the process number corresponding to the generated process information.
Optionally, when the debug interface support window is configured to memory, the execution instructions are configured to map the exception handling address window to a memory address location.
In the embodiment of the present application, in order to implement fast processing of a breakpoint when a process is switched, if a debug interface support window is configured to a memory, an exception vector entry address corresponding to an exception handling address in a program may be set to a fixed storage address (e.g. 0xbfc 00480), so that the exception handling address is mapped from the fixed storage address to a corresponding position in the memory through a processor window, where the processor window refers to an extended window used by a processor to perform data calculation.
Optionally, when the debug interface does not support window configuration to memory, the execution instructions are configured to instruct the processor to jump to memory access the exception handling address.
In this embodiment of the present application, if the debug interface does not support configuration of the window to the memory, the address routing window may be used to route the exception handling address to the memory, and the processor may be controlled to enter an exception state by jumping to the memory through a jump instruction, where the address routing window is an extended function window that may route the address to the memory.
According to the test method of the program, equipment information is monitored through the target register corresponding to the debugging interface of the processor under the condition that normal operation of the processor is not interrupted, and when the monitored equipment information contains an abnormal access address, the processor is determined to enter an abnormal state so as to read out the process information from the debugging interface, so that the tested equipment operates normally, the obtained equipment information and the process information are used for test analysis, the time that the processor is in the abnormal state in the test process of the program is reduced as much as possible, and therefore the influence on normal operation of the processor is reduced.
Fig. 5 is a block diagram of a test apparatus 30 according to an embodiment of the present application, the apparatus including:
the monitoring module 301 is configured to enable a terminal to monitor device information of a tested device through a target register corresponding to a debugging interface of a processor under the condition that the execution state of the tested device is not changed when a test program is run on the tested device provided with the processor;
a writing module 302 configured to cause the terminal to write an execution instruction carrying an exception handling address at a debug interface of the processor, so that the processor executes the execution instruction;
an obtaining module 303, configured to obtain process information from a debug interface of the processor when the presence of the exception handling address in the device information is detected, so that the processor operates normally;
an analysis module 304 configured to perform a test analysis on the device information and the process information.
Optionally, the target register includes: the monitoring module 301 is further configured to enable the terminal to monitor the device information of the device under test through the PC sampling register corresponding to the debug interface of the processor without changing the execution state of the device under test.
Optionally, the analysis module 304 includes:
the process information dividing unit is configured to divide the process information into target process information corresponding to each process;
the process function acquisition unit is configured to acquire a process function corresponding to the target process information meeting the test requirement, and takes the acquired process function as an analysis result.
Optionally, the process information dividing unit is further configured to:
and under the condition that the test program adopts a memory management unit to switch the process, dividing the process information according to the set breakpoint in the equipment information to obtain target process information corresponding to each process, wherein the execution code of the breakpoint is preset in a process switching function of the program.
Optionally, the process information dividing unit is further configured to:
and under the condition that the test program does not adopt a memory management unit to switch the process, analyzing the process number in the equipment information to divide the process information, and obtaining the target process information corresponding to each process.
Optionally, when the debug interface support window is configured to memory, the execution instructions are configured to map the exception handling address window to a memory address location.
Optionally, when the debug interface does not support window configuration to memory, the execution instructions are configured to instruct the processor to jump to memory access the exception handling address.
According to the program testing device, the device information is monitored through the target register corresponding to the debugging interface of the processor under the condition that the normal operation of the processor is not interrupted, and when the monitored device information contains the abnormal access address, the processor is determined to enter the abnormal state so as to acquire the process information from the debugging interface, so that the tested device operates normally, the acquired device information and the process information are used for testing and analyzing, the time that the processor is in the abnormal state in the testing process of the program is reduced as much as possible, and therefore the influence on the normal operation of the processor is reduced.
The embodiment of the application provides an electronic device, which comprises a processor, a memory and a program or an instruction stored on the memory and capable of running on the processor, wherein the program or the instruction realizes the testing method of the program in any embodiment when being executed by the processor.
According to the electronic device provided by the embodiment of the application, the device information is acquired before the processor enters the abnormal state through the target register corresponding to the debugging interface of the processor in the process of running the program of the processor, and the processor is determined to enter the abnormal state when the acquired device information contains the abnormal access address, so that the acquired device information and the acquired process information are transferred to the simulator for test analysis, the time that the processor is in the abnormal state in the test process of the program is reduced as much as possible, and the influence on the normal running of the processor is reduced.
The present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, enables the test method of the program of any of the above embodiments.
The embodiment of the application provides a computer storage medium, in the process of running a program by a processor, equipment information is acquired before the processor enters an abnormal state through a target register corresponding to a debugging interface of the processor, and the processor is determined to enter the abnormal state when the acquired equipment information contains an abnormal access address, so that the read equipment information and process information are transferred to the equipment for test analysis, the time that the processor is in the abnormal state in the test process of the program is reduced as much as possible, and the influence on the normal running of the processor is reduced.
Those skilled in the art will appreciate that the present application includes reference to apparatus for performing one or more of the operations described herein. These devices may be specially designed and constructed for the required purposes, or may comprise known devices in general purpose computers. These devices have computer programs stored therein that are selectively activated or reconfigured. Such a computer program may be stored in a storage medium of a device (e.g., a computer) or in any type of medium suitable for storing electronic instructions and coupled to a bus, respectively, including, but not limited to, any type of disk (including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks), ROMs (Read-Only memories), RAMs (Random Access Memory, random access memories), EPROMs (Erasable Programmable Read-Only memories), EEPROMs (Electrically Erasable Programmable Read-Only memories), flash memories, magnetic cards, or optical cards. That is, a storage medium includes any medium that stores or transmits information in a form readable by a device (e.g., a computer).
It will be understood by those within the art that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by computer program instructions. Those skilled in the art will appreciate that the computer program instructions can be implemented in a processor of a test method for a general purpose computer, special purpose computer, or other programmable program to perform the functions specified in the block diagrams and/or flowchart block or blocks of the disclosed subject matter.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of testing a program, the method comprising:
when a test program is run on a tested device provided with a processor, a terminal monitors device information of the tested device under the condition that the execution state of the tested device is not changed through a target register corresponding to a debugging interface of the processor;
the terminal writes an execution instruction carrying an exception handling address in a debugging interface of the processor so that the processor executes the execution instruction;
when the abnormal processing address exists in the equipment information, acquiring process information from a debugging interface of the processor so that the processor operates normally;
and carrying out test analysis on the equipment information and the process information.
2. The method of claim 1, wherein the destination register comprises: the PC sampling register, the terminal monitors the device information of the tested device under the condition of not changing the execution state of the tested device through a target register corresponding to a debugging interface of the processor, and the PC sampling register comprises:
and the terminal monitors the equipment information of the tested equipment under the condition of not changing the execution state of the tested equipment through a PC sampling register corresponding to the debugging interface of the processor.
3. The method of claim 1, wherein said performing a test analysis on said device information and said process information comprises:
dividing the process information into target process information corresponding to each process;
and acquiring a process function corresponding to the target process information meeting the test requirement, and taking the acquired process function as an analysis result.
4. The method of claim 3, wherein the dividing the process information into the target process information corresponding to each process comprises:
and under the condition that the test program adopts a memory management unit to switch the process, dividing the process information according to the set breakpoint in the equipment information to obtain target process information corresponding to each process, wherein the execution code of the breakpoint is preset in a process switching function of the program.
5. The method of claim 3, wherein the dividing the process information into the target process information corresponding to each process comprises:
and under the condition that the test program does not adopt a memory management unit to switch the process, analyzing the process number in the equipment information to divide the process information so as to obtain target process information corresponding to each process.
6. The method of any of claims 1-5, wherein, when the debug interface support window is configured to memory, the execution instructions are configured to map the exception handling address window to a memory address location.
7. The method of any of claims 1-5, wherein, when the debug interface does not support window configuration to memory, the execution instructions are configured to instruct the processor to jump to memory to access the exception handling address.
8. A test device for a program, the device comprising:
the monitoring module is configured to enable a terminal to monitor equipment information of the tested equipment under the condition that the execution state of the tested equipment is not changed through a target register corresponding to a debugging interface of a processor when a test program is run on the tested equipment provided with the processor;
the writing module is configured to enable the terminal to write an execution instruction carrying an exception handling address in a debugging interface of the processor so that the processor executes the execution instruction;
the acquisition module is configured to acquire process information from a debugging interface of the processor when the presence of the exception handling address in the equipment information is detected, so that the processor operates normally;
and the analysis module is configured to perform test analysis on the equipment information and the process information.
9. An electronic device comprising a processor, a memory and a program or instruction stored on the memory and executable on the processor, which when executed by the processor implements a method of testing a program as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the method of testing a program according to any one of claims 1 to 7.
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