CN116405360A - High data rate carrier index differential chaos keying modulation and demodulation method and system based on scrambling matrix - Google Patents

Abstract

Compared with the prior art, the method and the system for modulating and demodulating the high-data-rate carrier index differential chaos keying based on the scrambling matrix can increase the data transmission rate, the energy efficiency and the confidentiality of the system. In addition, the invention adopts a repeating circuit at the transmitting end, and the receiving end adopts average processing, so that the noise component in the decision variable can be greatly reduced, thereby improving the bit error code performance of the system. Meanwhile, the method adopted by the invention can avoid using delay units in the receiving end and the transmitting end, further reduce noise components in the decision variables of the receiving end, improve the bit error performance of the system and further obtain lower bit error rate.

Description

High Data Rate Carrier Indexed Differential Chaos Keying Modulation and Demodulation Based on Scrambling Matrix law and system

technical field

The invention relates to the technical field of communication signal processing, in particular to a high data rate carrier index differential chaotic keying modulation and demodulation method and system based on a scrambling matrix.

Background technique

Chaotic digital modulation technology can not only retain the characteristics of low intercept probability and reduce multipath effect of traditional spread spectrum communication system, but also show unique advantages in many other aspects, such as reducing the hardware cost of the system and improving communication security , which is suitable for effectively distinguishing different users in a multi-user environment, and can improve the performance of spread spectrum communication systems.

Because there is no reliable and effective method to achieve chaos synchronization at the receiving end, most of the existing chaotic digital modulation and demodulation methods are based on the transmission reference method, that is, both the carrier signal and the information-carrying signal are sent to the receiving end. Among them, the differential chaos shift keying (Differential Chaos Shift Keying, DCSK) modulation and demodulation method does not need to complete channel estimation, and can obtain better bit error performance. In many practical applications (ie: including wireless personal area network, wireless sensor network, etc.) have shown strong competitiveness. However, in order to ensure the orthogonality between the reference signal and the information signal, DCSK transmits the two signals in different time periods, so both the transmitting end and the receiving end must use a delay unit. In ultra-wideband transmission, it is almost impossible to integrate an analog delay unit using existing technology, and a delay unit implemented in a digital mode will consume huge power.

In response to the above problems, the Multi-Carrier Differential ChaosShift Keying (MC-DCSK) modulation and demodulation method uses multiple subcarriers to transmit reference signals and multiple information signals at the same time, and distinguishes them through different subcarriers. Reference signal and various information signals. Among all the subcarriers, only one subcarrier is assigned to the reference signal, and all the remaining subcarriers are assigned to the information signal, and each information signal occupies one subcarrier. Although MC-DCSK eliminates the delay unit in the transceiver equipment, the bit error rate of MC-DCSK is still high, and the bit error performance and security are not ideal.

Contents of the invention

One of the purposes of the present invention is to provide a high data rate carrier index differential chaotic keying system based on a scrambling matrix to solve the problem of low data rate, unsatisfactory security, low energy efficiency and bit errors in existing modulation and demodulation methods. The problem of high code rate.

In order to achieve the above object, the present invention adopts the following technical solutions: a high data rate carrier index differential chaotic keying modulation and demodulation method based on scrambling matrix, in general, at the sending end:

First convert the information to be transmitted into N groups of parallel information through serial parallel conversion, and divide each group of information into P index bits and 1 modulation bit;

Use the chaotic generator to generate a chaotic reference signal and repeat it multiple times, multiply the repeated chaotic reference signal with the carrier to generate a Hadamard matrix, and select each row as a Walsh code;

The index bits are selected by the index mapper to select one of the 2 ^P carriers for information bit transmission, the modulation bits are converted into modulation symbols by the polarity converter, and then differential chaotic keying modulation is performed with the former, and the differential chaotic keying The modulated signal is multiplied by the Walsh code and then added to the repeated chaotic reference signal, and finally scrambled by the scrambler to obtain the sending signal of the sending end and send it to the channel;

On the receiving end:

The received signal is first processed by a descrambler, and then multi-carrier demodulated to restore the reference signal and N information signals respectively;

Obtain the segmentally averaged reference signal sequence, perform matrix multiplication with N information signal sequences, and then use the energy comparator to demodulate the index bits, restore the modulated bits through threshold judgment, and finally output the original signal through parallel-to-serial conversion. information.

Specifically, at the sending end, signal modulation includes the following steps:

1) Perform serial-to-parallel conversion on the input information signal, and divide it into N groups of information, each group of information includes two parts: P-bit index bit and 1-bit modulation bit;

2) Pass N sets of index bits through the index mapper, and select a carrier from 2 ^P carriers for transmission;

3) Use the chaotic generator to generate a Logistic chaotic reference signal with a length of θ, and repeat it R times;

4) After converting N groups of modulation bits into modulation symbols through a polarity converter, multiply by the result of step 2), and then multiply by the repeated chaotic signal;

5) Multiply the repeated chaotic signal with the carrier;

6) Generate a Hadamard matrix, from which each row is selected as a Walsh code;

7) Multiply the result of step 4 by the Walsh code, and then add it to the chaotic reference signal of step 3;

8) Scramble the result of step 7 through the scrambler to obtain the sending signal of the sending end.

Wherein, at the receiving end, signal demodulation includes the following steps:

9) Process the received signal through the descrambler;

10) Multiply the signal obtained in step 9 with 2 ^P synchronized carriers to obtain the product signal;

11) Matching filtering is performed on the signals obtained in step 10 respectively, and time-domain sampling is performed on the filtered 2 ^P channel product signals;

12) Multiply the information signals obtained in step 11 with their corresponding Walsh sequences, and then average the results;

13) Segmentally average the reference signal obtained in step 11;

14) Correlate the averaged reference signal sequence obtained in step 13 with the N information signal sequences obtained in step 12 to obtain N correlation values;

15) Pass the N correlation values obtained in step 14 through N energy comparators respectively to obtain the element with the largest absolute value, thereby demodulating the index bits;

16) Pass the N correlation values obtained in step 14 through N energy comparators respectively, and then pass threshold judgment to restore the modulation bits;

17) Combine the index bits obtained in step 15 and the modulated bits obtained in step 16, and then perform parallel-to-serial conversion to recover the original information signal.

On the other hand, the present invention also relates to a high data rate carrier index differential chaotic keying system based on a scrambling matrix, which includes a transmitting end and a receiving end, and the transmitting end and the receiving end use the method described above to process the signal Modem.

To be precise, the transmitting end modulates the input information signal according to the method of step 1 to step 8 above.

Wherein, the receiving end demodulates the received signal according to the method of step 9 to step 17 above.

In an embodiment of the present invention, the sending end includes:

Chaotic signal generator, pulse shaping filter, serial-to-parallel conversion circuit, repetition circuit, polarity converter, N index mappers, N*2 ^P carrier multipliers, N carrier adders, N modulation multipliers and N Walsh sequence multipliers;

The chaotic signal generator is used to generate a discrete chaotic reference signal sequence; the pulse shaping filter is used to perform pulse shaping and filtering on the chaotic reference signal to obtain a reference signal in the current symbol period; the serial-to-parallel conversion circuit is used to convert the current symbol time The serial data bits to be transmitted are converted into parallel data bits; the repetition circuit is used to repeat the chaotic signal to reduce noise interference; the polarity converter is used to convert the input modulation bits into modulation symbols; the N index mappers are used to select a carrier according to the index bit to transmit the signal; the N*2 ^P carrier multipliers are used to multiply the carrier modulation coefficient with the carrier to realize carrier index modulation; the N carrier adders are used for The signals multiplied by the carrier are added; the N modulation multipliers are used to multiply the carrier index modulation signal and the modulation bit; the N Walsh sequence multipliers are used to multiply the information signal and N Walsh codes .

In an embodiment of the present invention, the receiving end includes:

2 ^P carrier multipliers, 2 ^P matched filters, 2 ^P sampling switches, N correlators, N energy comparators, N threshold decision devices and parallel-to-serial conversion circuits;

The 2 ^P carrier multipliers are used to multiply the 2 ^P synchronous subcarriers with the received signals to obtain 2 ^P product signals; the 2 ^P matched filters are used to match the 2 ^P product signals respectively Filtering; the 2 ^P sampling switches are used to perform time-domain sampling on the 2 ^P product signals after matched filtering, and recover 1 discrete reference signal sequence and 2 ^P discrete information signal sequence; the N correlators use Correlating the recovered reference signal with the information signal; the N energy comparators are used to compare the energy of the N signals respectively, so as to demodulate the index bit; the output of the N threshold decision devices has the maximum absolute value elements; the parallel-to-serial conversion circuit is used to combine the obtained N paths of index bits and modulated bits respectively and then combine them into 1 path of serial demodulated data bits and output it.

Compared with the existing differential chaotic shift keying (DCSK) modulation and demodulation method, the high data rate carrier index differential chaotic keying modulation and demodulation method based on the scrambling matrix provided by the present invention can transmit the Signals and information signals increase the data transfer rate, energy efficiency, and security of the system. In addition, the present invention adopts repetitive circuits at the sending end and average processing at the receiving end, which can greatly reduce the noise component in the decision variable, thereby improving the bit error performance of the system. At the same time, because the method adopted in the present invention can avoid using delay units in the receiving end and the transmitting end, further reduces the noise component in the decision variable of the receiving end, improves the bit error performance of the system, and thus can obtain a higher MC - Lower bit error rate of DCSK modulation and demodulation method.

Description of drawings

Fig. 1 is a schematic flowchart of the modulation and demodulation method involved in the embodiment.

Fig. 2 is a schematic structural diagram of the transmitting end (modulator) in the embodiment.

Fig. 3 is a schematic structural diagram of the receiving end (demodulator) in the embodiment.

Fig. 4 is a comparison chart of bit error performance between the modulation and demodulation method involved in the embodiment and the existing MCS-MDCSK method in an additive white Gaussian noise channel.

Detailed ways

In order to facilitate the understanding of those skilled in the art, the present invention will be further described below in conjunction with the embodiments and accompanying drawings.

In general, the present invention converts the information to be transmitted into N groups of parallel information through serial parallel conversion, and divides each group of information into P index bits and 1 modulation bit; uses a chaos generator to generate a chaos reference signal and repeats Multiple times, the repeated chaotic reference signal is multiplied by the carrier to generate a Hadamard matrix, and each row is selected as a Walsh code; the index bit is selected by the index mapper to select one of the 2 ^P carriers for information bit transmission, and the Modulation bits are converted into modulation symbols by a polarity converter, and then differential chaotic keying modulation is performed with the former. The signal modulated by differential chaotic keying is multiplied by Walsh code and then added to the repeated chaotic reference signal. The scrambler performs scrambling, obtains the sending signal from the sending end, and sends it to the channel; after that, the received signal is first processed by the descrambler, and then multi-carrier demodulation is performed to restore the reference signal and N-channel Information signal: By obtaining the reference signal sequence after segment average, matrix multiplication is performed on it and N-way information signal sequence, and then the index bit is demodulated by the energy comparator, and the modulated bit is recovered by the threshold judgment, and finally through the combination The string conversion outputs the original information.

Figure 1 shows the process of the high data rate carrier index differential chaotic keying modulation and demodulation method based on scrambling matrix, which mainly includes the following steps:

On the sender side:

Step 1: carry out serial-to-parallel conversion to the input information signal, be divided into N groups of information, each group of information includes two parts of P index bit and 1 modulation bit;

Step 2: select a carrier from 2 ^P carriers for transmission by passing N groups of index bits through the index mapper;

Step 3: Utilize chaos generator to generate the Logistic chaos reference signal that length is θ, and repeat R times;

Step 4: multiply N groups of modulation bits with the result of step 2 after being converted into modulation symbols through a polarity converter, and then multiply with the chaotic signal after repetition;

Step 5: multiply the chaotic signal x after repetition with the carrier f ₀ ;

Step 6: select each row as the Walsh code from the Hadamard matrix produced;

Step 7: the result of step 4 is multiplied with the Walsh code, and then added with the chaotic reference signal of step 3;

Step 8: Scrambling the result of step 7 through a scrambler to obtain a sending signal from the sending end.

On the receiving end:

Step 9: process the received signal through the descrambler;

Step 10: multiply step 9 gained signal and 2 ^P synchronous carriers respectively, obtain product signal;

Step 11: carry out matched filtering to step 10 gained signal respectively, carry out time-domain sampling to the ^2P road product signal after filtering;

Step 12: the information signal that step 11 is obtained is multiplied with respectively corresponding Walsh sequence, the result that obtains averages again;

Step 13: the reference signal obtained in step 11 is averaged in sections;

Step 14: correlating the averaged reference signal sequence obtained in step 13 with the N path information signal sequence obtained in step 12, respectively, to obtain N correlation values;

Step 15: N correlation values obtained in step 14 are passed through N energy comparators respectively to obtain the element with the maximum absolute value, thereby demodulating the index bit;

Step 16: N correlation values of step 14 gained are passed through N energy comparators respectively, and then through threshold value judgment, recover modulation bit;

Step 17: Combining the index bits obtained in step 15 and the modulated bits obtained in step 16 and then performing parallel-to-serial conversion to restore the original information signal.

Based on the same technical idea as the above modulation and demodulation method, the present invention also proposes a high data rate carrier index differential chaotic keying system based on scrambling matrix, which can use the above method to modulate and demodulate signals.

Figure 2 shows the specific structure of the transmitting end (modulator) in the system. Generally speaking, it mainly includes: chaotic signal generator, pulse shaping filter, serial-to-parallel conversion circuit, repeating circuit, polarity converter, N Index mappers, N*2 ^P carrier multipliers, N carrier adders, N modulation multipliers, and N Walsh sequence multipliers; among them, the chaotic signal generator is used to generate discrete chaotic reference signal sequences, pulse shaping filter The device is used to shape and filter the chaotic reference signal pulse to obtain the reference signal in the current symbol period. The serial-parallel conversion circuit is used to convert the serial data bits to be transmitted in the current symbol time into parallel data bits. The repetition circuit is used for the chaotic signal. Repeat to reduce noise interference, the polarity converter is used to convert the input modulation bit into a modulation symbol, N index mappers are used to select a carrier to transmit the signal according to the index bit, and N*2 ^P carrier multipliers are used. The carrier modulation coefficient is multiplied by the carrier to realize the carrier index modulation. N carrier adders are used to add the signal multiplied by the carrier. N modulation multipliers are used to multiply the carrier index modulation signal and the modulation bit. N A Walsh sequence multiplier is used to multiply the information signal with N Walsh codes.

Figure 3 shows the specific structure of the receiving end (demodulator) in the system. Generally speaking, it mainly includes: 2 ^P carrier multipliers, 2 ^P matched filters, 2 ^P sampling switches, N correlation devices, N energy comparators, N threshold decision devices and parallel-to-serial conversion circuits. Among them, 2 ^P carrier multipliers are used to multiply 2 ^P synchronous sub-carriers with received signals respectively to obtain 2 ^P product signals, and 2 ^P matched filters are used to perform matched filtering on 2 ^P product signals respectively, 2 ^P sampling switches are used to perform time-domain sampling on the 2 ^P product signals after matched filtering to recover 1 discrete reference signal sequence and 2 ^P discrete information signal sequences, and N correlators are used to convert the recovered reference signal sequence The signal and the information signal are respectively correlated, and N energy comparators are used to compare the energy of the N signals, thereby demodulating the index bits, N threshold decision devices output the element with the largest absolute value, and the parallel-to-serial conversion circuit is used for The obtained N paths of index bits and modulated bits are respectively combined and then combined into one path of serial demodulated data bits and output.

In the high data rate carrier index differential chaotic keying modulation and demodulation method based on scrambling matrix, the data transmission rate, energy efficiency and confidentiality of the system can be increased because the test signal and information signal can be transmitted in the same period. In addition, because the system uses repetitive circuits at the sending end and averaging processing at the receiving end, the noise components in the decision variables can be greatly reduced, thereby improving the bit error performance of the system. At the same time, since the system does not need to use a delay unit in the receiving end and the transmitting end, theoretically, the noise component in the decision variable at the receiving end can be further reduced, the bit error performance of the system can be improved, and a lower bit error rate can be obtained.

In order to verify whether the high data rate carrier index differential chaotic keying modulation and demodulation method based on scrambling matrix can substantially reduce the bit error rate, the verification test is carried out through the following test cases. The verification test process is designed as follows:

At the sending end, the signal is modulated by high data rate carrier index differential chaotic keying based on scrambling matrix:

时，采用一个符号时间内离散混沌信号序列长度θ为10，可供使用的载波数目2^P=8，N=800, P=3的条件。Step 1: Select the bit SNR in the channel

When , the discrete chaotic signal sequence length θ is 10 in one symbol time, and the number of available carriers is 2 ^P =8, N=800, P=3 conditions.

，并重复5次。Step 2: Within a symbol period [0, Tb], the chaotic signal generator outputs a discrete chaotic signal sequence with a length of 10

, and repeat 5 times.

Step 3: Pass the discrete chaotic signal sequence generated in step 2 through a square raised cosine roll-off filter whose time domain impulse response is h(t), complete the pulse shaping filter, and obtain the reference signal in the current symbol period:

；

;

Among them, t represents time; T _c represents chip time.

Step 4: Use a serial-to-parallel conversion circuit to convert one channel of serial data bits with a length of 3200 to be transmitted in the current symbol period into 800 channels of parallel low-speed data bits. Each group of information includes two parts: 3 index bits and 1 modulation bit;

Step 5: Pass 800 sets of index bits through the mapping selector at the same time, and select a carrier from 8 carriers for transmission;

Step 6: Multiply the 800 groups of modulation bits with the result of step 5, and then multiply with the repeated chaotic signal;

Step 7: Generate a 512*512 Hadamard matrix, from which each row is selected as a Walsh code;

Step 8: After the chaotic signal x is repeated, it is multiplied by the carrier f ₀ to obtain the reference signal;

Step 9: The result of step 6 is passed through the scrambling matrix to obtain the sending signal of the sending end;

Step 10: Receive the signal sent in step 9, multiply it with 8 synchronous carriers respectively after descrambling the matrix, and obtain the product signal;

Step 11: Perform matching filtering on the 8-way product signals obtained in step 10, and perform time-domain sampling on the filtered 8-way product signals, and each sampled signal passes through matrix B and matrix A respectively to obtain 1 reference signal and 800-way information signal;

Step 12: Multiply the 800+1 signals obtained in step 11 with their corresponding Walsh sequences, and then average the results;

Step 13: correlating the averaged reference signal sequence obtained in step 12 with the 800 information signal sequences obtained in step 12 to obtain 800 correlation values;

Step 14: Pass the 800 correlation values obtained in step 13 through 800 energy comparators respectively to obtain the element with the largest absolute value, so that the index bits can be demodulated;

Step 15: Pass the 800 correlation values obtained in step 14 through 800 energy comparators respectively, and then pass through the threshold decision device respectively to recover the modulation bits;

Step 16: Combine the index bits obtained in step 14 and the modulation bits obtained in step 15, and then perform parallel-to-serial conversion to recover the original information signal.

产生，混沌信号采样频率为1MHz，符号持续时间T=16us，每个符号时间内等效的信号采样点数为16，平方升余弦滚降滤波器滚降系数α=0.25，所有子载波的中心频率间隔满足/>

。The high data rate carrier index differential chaotic keying modulation and demodulation method based on the scrambling matrix designed in the test case is tested by computer simulation. In the experiment, the number of transmitted data bits is 3200, and the discrete chaotic signal sequence is mapped by Logistic

Generation, chaotic signal sampling frequency is 1MHz, symbol duration T=16us , the equivalent number of signal sampling points in each symbol time is 16, the square raised cosine roll-off filter roll-off coefficient α=0.25 , the center frequency of all subcarriers Interval meets />

.

Fig. 4 shows the bit error rate of the test cases simulated in the additive Gaussian white noise channel. As a comparison, the bit error rate of the existing MCS-MDCSK method obtained by simulation under the same conditions is also shown in the figure. It can be seen from the figure that compared with the existing MCS-MDCSK method, the above-mentioned high data rate carrier index differential chaotic keying modulation and demodulation method based on scrambling matrix significantly reduces the bit error rate and shows better performance. bit error performance.

The above-mentioned embodiments are preferred implementation solutions of the present invention. In addition, the present invention can also be realized in other ways, and any obvious replacements are within the scope of protection of the present invention without departing from the concept of the technical solution.

In order to make it easier for those skilled in the art to understand the improvement of the present invention compared to the prior art, some drawings and descriptions of the present invention have been simplified, and for the sake of clarity, some other elements have been omitted in this application document, Those of ordinary skill in the art should realize that these omitted elements may also constitute the content of the present invention.

Claims (8)

1. The high data rate carrier index differential chaos keying modulation and demodulation method based on the scrambling matrix is characterized by comprising the following steps of:

at the transmitting end:

converting information to be transmitted into N groups of parallel information through serial-parallel conversion, and dividing each group of information into P index bits and 1 modulation bit;

generating a chaotic reference signal by using a chaotic generator and repeating for a plurality of times, multiplying the repeated chaotic reference signal by a carrier wave to generate a Hadamard matrix, and selecting each row from the Hadamard matrix as a Walsh code;

selecting index bits by index mapper 2 ^p 1 carrier wave in the carrier waves carries out information bit transmission, modulation bits are converted into modulation symbols through a polarity converter, then differential chaos keying modulation is carried out on the modulation symbols, signals subjected to differential chaos keying modulation are multiplied by Walsh codes and then added with repeated chaos reference signals, finally scrambling is carried out through a scrambling device, and a sending signal of a sending end is obtained and sent to a channel;

at the receiving end:

processing the received signal by a descrambler, and then demodulating by multiple carriers to recover a reference signal and N paths of information signals respectively;

and obtaining a reference signal sequence after segmentation average, respectively multiplying the reference signal sequence with the N paths of information signal sequences by a matrix, demodulating index bits by using an energy comparator, recovering modulation bits by threshold judgment, and finally outputting original information by parallel-serial conversion.

2. The scrambling matrix-based high data rate carrier index differential chaos keying modulation and demodulation method of claim 1, wherein at a transmitting end, signal modulation comprises the steps of:

1) Serial-parallel conversion is carried out on an input information signal, and the input information signal is divided into N groups of information, wherein each group of information comprises two parts, namely a P-bit index bit and a 1-bit modulation bit;

2) Passing N groups of index bits through an index mapper from 2 ^p Selecting one carrier from the carriers for transmission;

3) Generating a Logistic chaotic reference signal with the length theta by using a chaotic generator, and repeating R times;

4) Converting N groups of modulation bits into modulation symbols through a polarity converter, multiplying the modulation symbols with the result of the step 2, and multiplying the modulation symbols with the repeated chaotic signal;

5) Multiplying the repeated chaotic signal by a carrier wave;

6) Generating a Hadamard matrix from which each row is selected as a Walsh code;

7) Multiplying the result of the step 4 by a Walsh code, and adding the result with the chaotic reference signal of the step 3;

8) And (3) scrambling the result in the step (7) through a scrambler to obtain a transmitting signal of the transmitting end.

3. The scrambling matrix-based high data rate carrier index differential chaos keying modulation and demodulation method of claim 1 or 2, wherein at a receiving end, signal demodulation comprises the steps of:

9) Processing the received signal by a descrambler;

10 (ii) combining the signal obtained in step 9 with 2 ^p Multiplying the synchronous carriers respectively to obtain a product signal;

11 Respectively carrying out matched filtering on the signals obtained in the step 10, and carrying out 2 after filtering ^p Carrying out time domain sampling on the path product signal;

12 Multiplying the information signals obtained in the step 11 with the corresponding Walsh sequences respectively, and averaging the obtained results;

13 Step 11), segment average is carried out on the reference signals obtained in the step;

14 Respectively correlating the averaged reference signal sequence obtained in the step 13 with the N paths of information signal sequences obtained in the step 12 to obtain N correlation values;

15 Respectively passing the N correlation values obtained in the step 14 through N energy comparators to obtain an element with the maximum absolute value, thereby demodulating index bits;

16 The N correlation values obtained in the step 14 are respectively passed through N energy comparators, and then are subjected to threshold judgment to recover modulation bits;

17 And (3) combining the index bit obtained in the step (15) with the modulation bit obtained in the step (16), and then carrying out parallel-to-serial conversion to recover the original information signal.

4. The high data rate carrier index differential chaos keying system based on the scrambling matrix comprises a transmitting end and a receiving end, and is characterized in that: the transmitting end and the receiving end modulate and demodulate signals by adopting the method of claim 1.

5. The scrambling matrix based high data rate carrier index differential chaos keying system of claim 4, wherein: the transmitting end modulates the input information signal according to the method of steps 1 to 8 in claim 2.

6. The scrambling matrix based high data rate carrier index differential chaos keying system of claim 4 or 5, wherein: the receiving end demodulates the received signal according to the method of steps 9 to 17 in claim 3.

7. The scrambling matrix based high data rate carrier index differential chaos keying system of claim 6, wherein the transmitting end comprises:

chaotic signal generator, pulse shaping filter, serial-parallel conversion circuit, repeating circuit, polarity converter, N index mappers, N x 2 ^p The carrier wave multipliers, N carrier wave adders, N modulation multipliers and N Walsh sequence multipliers;

the chaotic signal generator is used for generating a discrete chaotic reference signal sequence; the pulse shaping filter is used for pulse shaping and filtering the chaotic reference signal to obtain a reference signal in the current symbol period; the serial-parallel conversion circuit is used for converting serial data bits to be transmitted in the current symbol time into parallel data bits; the repeating circuit is used for repeating the chaotic signal so as to reduce noise interference; the polarity converter is used for converting the input modulation bits into modulation symbols; the N index mappers are used for selecting one carrier to transmit signals according to index bits; the N is 2 ^P The carrier multipliers are used for multiplying the carrier modulation coefficients with carriers to realize carrier index modulation; the N carrier wave adders are used for adding signals multiplied by carriers; the N modulation multipliers are used for multiplying the carrier index modulation signals with modulation bits; the N Walsh sequence multipliers are used to multiply the information signal with N Walsh codes.

8. The scrambling matrix based high data rate carrier index differential chaos keying system of claim 7, wherein the receiving end comprises:

2 ^p multiple carrier multiplier, 2 ^p Matched filters, 2 ^p The device comprises a sampling switch, N correlators, N energy comparators, N threshold value decision devices and a parallel-serial conversion circuit;

said 2 ^p The carrier multipliers are used for multiplying 2 ^p The synchronous sub-carriers are multiplied by the received signals respectively to obtain 2 ^p A product signal; said 2 ^p A matched filter for pair 2 ^p The product signals are respectively matched and filtered; said 2 ^p The sampling switches are used for matchingPost-filter 2 ^p The product signals are respectively sampled in the time domain to recover 1 path of discrete reference signal sequence and 2 paths of discrete reference signal sequence ^p A sequence of discrete information signals; the N correlators are used for respectively correlating the recovered reference signals with the information signals; the N energy comparators are used for comparing the energy of the N paths of signals respectively so as to demodulate index bits; the N threshold decision devices output the element with the largest absolute value; the parallel-serial conversion circuit is used for combining the obtained N paths of index bits and modulation bits respectively, then merging the N paths of index bits and modulation bits into 1 path of serial demodulation data bits and outputting the 1 path of serial demodulation data bits.

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