CN116405031A - Analog-to-digital converters and chips - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, and discloses an analog-to-digital converter and a chip. The analog-to-digital converter includes: first and second passive switched capacitor integrators; two capacitive analog-to-digital conversion arrays; and a control logic circuit , used to close the first and second switch groups in the first passive switched capacitor integrator to output the first residual voltage when the capacitor in the array is reset, and close the second passive switched capacitor integrator The third and fourth switch groups are used to output the second residual voltage; and the double differential input comparator is used to receive the sum of the first residual voltage and the input voltage of the current preset period as the first differential input signal, and receive The second residual voltage is used as the second differential input signal, and the comparison result is output, and the control logic circuit is also used to output a plurality of switch control signals to the capacitive analog-to-digital conversion array according to the comparison result, so as to output the current preset cycle digital data, thereby effectively suppressing quantization noise within the signal band.

Description

Analog-to-digital converters and chips

technical field

The invention relates to the technical field of integrated circuits, in particular to an analog-to-digital converter and a chip.

Background technique

Successive approximation analog-to-digital converters are widely used in many scenarios due to their low power consumption and high energy efficiency. However, various internal non-ideal factors and various noises limit the signal-to-noise ratio it can achieve. Noise is the most prominent. Oversampling and noise shaping techniques can shape quantization noise and comparator noise by constructing corresponding high-pass or band-pass noise transfer functions, thereby effectively improving the in-band signal-to-noise ratio of the analog-to-digital converter. However, in order to achieve a good suppression of the noise in the signal band, it is often necessary to use active circuit modules with high power consumption in the noise shaping loop to build the circuit, which is not conducive to the realization of a low-power system.

Contents of the invention

The purpose of the present invention is to provide an analog-to-digital converter and chip, which adopts the second-order passive hybrid noise shaping technology to respectively sample and integrate the residual voltage of the previous preset period through two sets of passive switched capacitor integrators , and the output of the two integrators is fed into the input sampling signal of the current cycle in the way of error feedback and forward addition, respectively, and converted together, so as to modulate the in-band quantization noise and comparator noise of the analog-to-digital converter to the high frequency band , to achieve the second-order high-pass noise shaping effect and suppress the correlated noise in the signal band.

In order to achieve the above object, the first aspect of the present invention provides an analog-to-digital converter, the analog-to-digital converter includes: a first passive switched capacitor integrator, which includes: 2Q first capacitors and the 2Q capacitors connected in series The first switch group of Q capacitors in the first capacitor and the second switch group of other Q capacitors in the 2Q first capacitors connected in series; the second passive switched capacitor integrator, which includes: 2Q The second capacitor and the third switch group connected in series to the Q capacitors in the 2Q second capacitors and the fourth switch group connected in series to the other Q capacitors in the 2Q second capacitors; two capacitive An analog-to-digital conversion array; a control logic circuit, configured to close the first switch group and the second switch group when the capacitors in the two capacitive analog-to-digital conversion arrays are reset to an initial state, so that The first passive switched capacitor integrator outputs a first residual voltage, and closes the third switch group and the fourth switch group, so that the second passive switched capacitor integrator outputs a second residual voltage voltage, wherein the first residual voltage is the sum of the first sub-residual voltages of the 2Q first capacitors in the last preset period, and the second residual voltage is the sum of the 2Q second sub-residual voltages The sum of the second sub-residual voltages of the capacitor in the last preset period; and a dual differential input comparator, configured to receive the sum of the first residual voltage and the input voltage of the current preset period as a first difference input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result, and the control logic circuit is further configured to output a plurality of switch control signals to the two capacitors according to the comparison result The analog-to-digital conversion array is used to output the digital data of the current preset period corresponding to the input voltage of the current preset period.

Preferably, the first passive switched capacitor integrator further includes: a fifth switch group connected in parallel to the 2Q first capacitors, correspondingly, the output voltage corresponding to the input voltage of the last preset period After the digital data of the last preset period, the control logic circuit is also used to divide the residual voltage of the upper plates of the two capacitive analog-to-digital conversion arrays by closing the fifth switch group to the 2Q first capacitors, so that the voltage of the first capacitors is the first sub-residual voltage.

Preferably, the second passive switched capacitor integrator further includes: a sixth switch group connected in parallel to the 2Q second capacitors, correspondingly, when performing the step of closing the fifth switch group to convert the After the step of distributing the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitors, the control logic circuit is also used to disconnect the fifth switch group, and by closing the The sixth switch group is used to distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitors, so that the voltage of the second capacitors is equal to the first Secondary residual voltage.

Preferably, the digital data is N-bit data, and the analog-to-digital converter further includes: a sampling switch circuit, before the capacitance in the two capacitive analog-to-digital conversion arrays is reset to an initial state, the control logic The circuit is further configured to perform the following operation: according to the predicted value of the current preset period, connect the lower plates of the highest capacitors on the positive side and the negative side of the two capacitive analog-to-digital conversion arrays to different Reference voltage; turn on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital conversion array; and disconnect the sampling switch circuit, and switch the capacitive analog to digital Each capacitor in the conversion array is reset to an initial state, so as to feed in the pre-offset compensation amount corresponding to the reference voltage and the lower N−1 bits of the N-bit data output in the last preset period.

Preferably, after performing the step of outputting the digital data of the current preset period corresponding to the input voltage of the current preset period, the control logic circuit is further configured to perform the following operation: the current preset subtracting the lower N-1 bit data of the N-bit data output in the previous preset cycle from the N-bit data output periodically to obtain an N-bit difference; and subtracting the N-bit difference from the preset offsetting a value corresponding to the compensation amount, so as to output the compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.

Preferably, the control logic circuit is further configured to add the compensated N-bit data of the current preset period to the lower N-1 bit data of the N-bit data output in the current preset period, so as to Get the predicted value for the next preset period.

Preferably, the control logic circuit is used to connect the lower plates of the highest capacitors on the positive side and the negative side of the two capacitive analog-to-digital conversion arrays to different reference voltages, including: When the predicted value of the cycle is set to 1, connect the lower plate of the highest capacitor on the positive side and the negative side of the capacitive analog-to-digital conversion array located at the input positive terminal to the positive reference voltage, and connect the lower plate located at the input negative The lower plates of the highest bit capacitors on the positive side and the negative side of the capacitive analog-to-digital conversion array at the terminal are connected to a negative reference voltage; or in the case of a predicted value of 0 for the current preset period, will be located The positive side of the capacitive analog-to-digital conversion array at the input positive terminal and the lower plate of the highest capacitor on the negative side are connected to a negative reference voltage, and the positive side of the capacitive analog-to-digital conversion array at the input negative terminal is connected Connect the lower plate of the highest capacitor on the negative side to the positive reference voltage.

Preferably, the control logic circuit is used to reset each capacitor in the capacitive analog-to-digital conversion array to an initial state comprising: connecting the lower plate of the positive side capacitor in the capacitive analog-to-digital conversion array to a positive reference voltage, and ground the lower plate of the capacitor on the negative side of the capacitive analog-to-digital conversion array.

Preferably, the first passive switched capacitor integrator includes 4 first capacitors; and the second passive switched capacitor integrator includes 4 second capacitors, wherein the first capacitor and the second The capacitance of the capacitor is equal to 1/2 times the total capacitance of the capacitive analog-to-digital conversion array.

Through the above technical solution, the present invention creatively closes the first switch group and the second switch group through the control logic circuit when the capacitors in the two capacitive analog-to-digital conversion arrays are reset to the initial state, making the first passive switched capacitor integrator output a first residual voltage, and closing the third switch group and the fourth switch group through a control logic circuit, so that the second passive switched capacitor integrator output the second residual voltage; the sum of the first residual voltage and the input voltage of the current preset period is received as the first differential input signal through a dual differential input comparator, and the second residual voltage is received as the second Differential input signals, and output comparison results; then output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison results through the control logic circuit, so as to output the current preset cycle The digital data of the current preset cycle corresponding to the input voltage. Therefore, the present invention adopts the second-order passive hybrid noise shaping technology to sample and integrate the residual voltage of the previous preset period through two sets of passive switched capacitor integrators, and respectively use error feedback and forward addition In this way, the output of the two integrators is fed into the input sampling signal of the current period and converted together, thereby modulating the in-band quantization noise and comparator noise of the analog-to-digital converter to the high frequency band, realizing the second-order high-pass noise shaping effect and suppressing the signal In-band correlated noise.

The second aspect of the present invention provides a chip, the chip includes the analog-to-digital converter

For the specific details and benefits of the chip provided by the embodiment of the present invention, please refer to the above-mentioned description of the analog-to-digital converter, which will not be repeated here.

Other features and advantages of the present invention will be described in detail in the detailed description that follows.

Description of drawings

The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used together with the following specific embodiments to explain the embodiments of the present invention, but do not constitute limitations to the embodiments of the present invention. In the attached picture:

FIG. 1 is a structural diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present invention;

Fig. 2 is a structural diagram of a first passive switched capacitor integrator provided by an embodiment of the present invention;

Fig. 3 is a structural diagram of a second passive switched capacitor integrator provided by an embodiment of the present invention;

Fig. 4 is two configuration diagrams at different times of the first passive switched capacitor integrator and the second passive switched capacitor integrator provided by an embodiment of the present invention;

FIG. 5 is a working sequence diagram of the successive approximation analog-to-digital converter provided by an embodiment of the present invention; and

FIG. 6 is a flow chart of the working mechanism of the analog-to-digital converter provided by an embodiment of the present invention.

Detailed ways

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

Fig. 1 is a structural diagram of an analog-to-digital converter provided by an embodiment of the present invention, and the analog-to-digital converter may include: a first passive switched capacitor integrator 10; a second passive switched capacitor integrator 20; two A capacitive analog-to-digital conversion array (ie CDAC) 30 ; a control logic circuit 40 and a dual differential input comparator 50 , as shown in FIG. 1 .

Wherein, the first passive switched capacitor integrator 10 may include: 2Q first capacitors and a first switch group connecting Q capacitors in the 2Q first capacitors in series and connecting the 2Q first capacitors in series A second switch group for the other Q capacitors among the capacitors.

Wherein, Q is a positive integer. For example, the first passive switched capacitor integrator may include four first capacitors (ie, C _A1 -C _A4 ); a first switch group S _A9 , S _A10 ; and a second switch group S _A11 , S _A12 , as shown in picture 2. Wherein, the capacitance of the first capacitor (for example, 1/2C _DAC ) is equal to 1/2 times the total capacitance of the capacitive analog-to-digital conversion array 30 (for example, C _DAC ).

Wherein, the second passive switched capacitor integrator 20 may include: 2Q second capacitors and a third switch group connected in series with Q capacitors in the 2Q second capacitors and connected in series with the 2Q second capacitors The fourth switch group of the other Q capacitors among the capacitors.

For example, the second passive switched capacitor integrator may include four second capacitors (ie, C _B1 -C _B4 ); a third switch group S _B9 , S _B10 ; and a fourth switch group S _B11 , S _B12 , As shown in Figure 3. Wherein, the capacitance of the second capacitor (for example, 1/2C _DAC ) is equal to 1/2 times the total capacitance of the capacitive analog-to-digital conversion array 30 (for example, C _DAC ).

Wherein, the control logic circuit 40 is used to close the first switch group and the second switch group when the capacitance in the capacitive analog-to-digital conversion array 30 is reset to an initial state, so that the The first passive switched capacitor integrator outputs a first residual voltage, and the third switch group and the fourth switch group are closed, so that the second passive switched capacitor integrator outputs a second residual voltage.

Specifically, the first residual voltage is the sum of the first sub-residual voltages of the 2Q first capacitors in the last preset period, and the second residual voltage is the sum of the first sub-residual voltages of the 2Q second capacitors The sum of the second sub-residual voltages in the last preset period.

For example, after the start signal (ΦRST signal) returns to high (that is, the capacitance in the capacitive analog-to-digital conversion array 30 is reset to the initial state) and the conversion control signal (ΦCNV signal) is pulled high (as shown in FIG. 5 ) , the first switch group and the second switch group (that is, switches S _A9 -S _A12 ) in the passive switched capacitor integrator 10 are connected with the third switch group and the fourth switch group switches in the passive switched capacitor integrator 20 ( That is, the switches S _B9 -S _B12 ) are closed. At this time, the configurations of the passive switched capacitor integrator 10 and the passive switched capacitor integrator 20 are shown on the right side of FIG. 4 . After the sub-residual voltage V _EF of the last preset period passively integrated in the passive switched capacitor integrator 10 is passively multiplied by 2 times (that is, the first residual voltage is 2V _EF ), it is connected in series with the input voltage , and added to the first differential input terminal of the dual differential input comparator 50; at the same time, the sub-residual voltage V _CIFF of the last preset period through the passive integration in the passive switched capacitor integrator 20 is passively doubled After multiplication (that is, the second residual voltage is 2V _CIFF ), it is applied to the second differential input terminal, as shown in FIG. 1 .

Wherein, the dual differential input comparator 50 is configured to receive the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, and receive the second residual voltage as a second differential input signal, and output the comparison result.

For example, the amplification factor of the first differential input terminal of the dual differential input comparator is 1; and the amplification factor of the second differential input terminal of the dual differential input comparator is 5.

Specifically, when the signal ΦCNV is high, when the comparator control signal ΦCLKC is high, the double differential input comparator 50 uses the sum of the 2V _EF output by the passive switched capacitor integrator 10 and the input voltage as the first Differential input signal; Simultaneously, the 2V _CIFF that the passive switched capacitor integrator 10 outputs is used as the second differential input signal, then, according to the signal output corresponding comparison result of above-mentioned expression: when two positive differential terminals of the comparator receive the signal When the sum is greater than the sum of the signals received by the two negative differential terminals of the comparator, the comparison result is positive, otherwise it is negative.

In the case where the dual differential input comparator outputs a comparison result, the control logic circuit 40 is further configured to output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison result, so as to outputting digital data of the current preset period corresponding to the input voltage of the current preset period.

Specifically, the control logic circuit 40 can switch the capacitors on the corresponding bits in the two capacitive analog-to-digital conversion arrays 30 according to the comparison result output by the dual differential input comparator 50 according to the switching scheme of splitting the switched capacitor array. switch.

For example, when the comparison result is positive, the comparison (conversion) result of the kth bit is 1, and the corresponding switch is controlled by the successive approximation control circuit 41 in the control logic circuit 40 so that the capacitive analog-to-digital conversion array 30 located at the input positive terminal The lower plate of the P-side capacitor corresponding to the kth bit is changed from the positive reference voltage V _REFP to the negative reference voltage V _REFN , so that the voltage value on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 at the input positive terminal V _DACP is reduced by (1/4) ^k (V _REFP -V _REFN ); and the lower pole of the N-side capacitor in the capacitive analog-to-digital conversion array 30 at the input negative terminal is controlled by the successive approximation control circuit 41 to The plate is changed from the negative reference voltage V _REFN to the positive reference voltage V _REFP , so that the voltage value V _DACN on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 input to the negative terminal increases by (1/4) ^k (V _REFP -V _REFN ). Conversely, when the comparison result was negative, the comparison (conversion) result of the k bit was 0, and the lower plate of the N-side capacitor corresponding to the k bit in the capacitive analog-to-digital conversion array 30 at the input positive end was referenced by the negative The voltage V _REFN is reconnected to the positive reference voltage V _REFP , so that the voltage value V _DACP on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 input to the positive terminal increases by (1/4) ^k (V _REFP −V _REFN ), and the lower plate of the P-side capacitor in the capacitive analog-to-digital conversion array 30 at the input negative terminal is changed from the positive reference voltage V _REFP to the negative reference voltage V _REFN , so that the capacitive analog-to-digital conversion array 30 at the input negative terminal The voltage value V _DACN on the upper plate of the capacitor in is reduced by (1/4) ^k (V _REFP -V _REFN ) to achieve a binary successive approximation where the common-mode level remains constant.

The entire successive approximation process is shown in the following formula, where N is the number of bits/bits of the analog-to-digital converter, D _k represents the conversion result of the k-th bit, V _IP and V _IN represent the capacitive capacitor sampled to the positive input terminal in the sampling stage, respectively. The voltage value of the analog-to-digital conversion array (that is, CDAC) 30 and the voltage value of the capacitive analog-to-digital conversion array 30 located at the input negative terminal, V _REFP and V _REFN represent positive reference voltage/level and negative reference voltage/level respectively, V _DACP and V _DACN respectively represent the voltage value of the capacitive analog-to-digital conversion array (namely CDAC) 30 located at the input positive terminal and the voltage value of the capacitive analog-to-digital conversion array 30 located at the input negative terminal:

When comparing to the last bit, if the comparison result is positive, then the lower plate of the positive pole (P) side capacitance of the lowest position in the capacitive analog-to-digital conversion array (i.e. CDAC) 30 at the input positive end is referenced by the positive The voltage is reconnected to a negative reference voltage to generate a correct residual voltage (V _RES ) on the upper plate of the capacitor of the differential capacitive analog-to-digital conversion array (ie CDAC) 30 to complete the successive approximation conversion; otherwise, the The lower plate of the lowest positive (P) side capacitor of the capacitive analog-to-digital conversion array (namely CDAC) 30 located at the input negative terminal is changed from a positive reference voltage to a negative reference voltage, and the successive approximation conversion is completed.

The first sub-residual voltage of the first capacitor in the last preset period and the second sub-residual voltage of the second capacitor in the last preset period in the above embodiment are respectively introduced below.

The first passive switched capacitor integrator 10 may further include: a fifth switch group connected in parallel to the 2Q first capacitors, correspondingly, outputting all voltages corresponding to the input voltage of the last preset period After the digital data of the previous preset period, the control logic circuit is also used to distribute the residual voltage of the upper plates of the two capacitive analog-to-digital conversion arrays to The 2Q first capacitors, so that the voltage of the first capacitors is the first sub-residual voltage.

For example, the first passive switched capacitor integrator 10 may further include: a fifth switch group (for example, switches S _A1 -S _A8 shown in FIG. 2 ) connected in parallel to four first capacitors.

The second passive switched capacitor integrator 20 may also include: a sixth switch group connected in parallel to the 2Q second capacitors, correspondingly, when performing the step of closing the fifth switch group to connect the two After the step of distributing the residual voltage of the upper plates of capacitive analog-to-digital conversion arrays to the 2Q first capacitors, the control logic circuit is also used to disconnect the fifth switch group, and by closing the The sixth switch group is used to distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitors, so that the voltage of the second capacitors is the second Sub residual voltage.

For example, the second passive switched capacitor integrator 20 may further include: a sixth switch group (for example, switches S _B1 -S _B8 shown in FIG. 2 ) connected in parallel to four second capacitors.

Specifically, after the corresponding digital data is converted in the last preset period, in the analog domain, the control logic circuit 40 controls the signal ΦEF to pull high to turn on the fifth switch group ( That is, switches S _A1 -S _A8 , the configuration of the passive switched capacitor integrator 10 at this time is shown in the left side of Fig. The residual voltage on the board is sampled to the integrating capacitors C _A1 -C _A4 through charge redistribution among the capacitors in a differential manner to realize first-order passive integration. This process satisfies the following formula, where V _EF is the first sub-residual voltage of the first capacitor in the last preset period:

After ΦEF returns to low (turn off the switches S _A1 -S _A8 ), the control logic circuit 40 controls the signal ΦCIFF to pull high to turn on the sixth switch group in the passive switched capacitor integrator 20 (that is, the switches S _B1 -S _B8 , at this moment, the configuration of the passive switched capacitor integrator 20 is as shown in the left side of Fig. 4) and the updated residual voltage (ie The residual voltage of the capacitive analog-to-digital conversion array 30 after being sampled by the passive switched capacitor integrator 10 is equal to the voltage V _EF on each of the capacitors C _A1 -C _A4 ) is sampled in a differential manner by charge redistribution to Integrating capacitors C _B1 -C _B4 realize second-order passive integration. This process satisfies the following formula, where V _CIFF is the second sub-residual voltage of the second capacitor in the last preset period:

The sum of the 2V _EF output by the passive switched capacitor integrator 10 and the input voltage is used as the first differential input signal of the double differential input comparator 50; meanwhile, the 2V _CIFF output by the passive switched capacitor integrator 10 is used as the second The differential input signal, therefore, the successive approximation control circuit 41 outputs the signal represented by the following formula (the system signal transfer function of the discrete domain):

D _OUT (z)＝V _INPUT (z)+4V _EF (z)+5×4V _CIFF (z)＝V _INPUT (z)+(1-0.8z ^-1 ) ² Q(z),

Wherein, z is a variable in the discrete domain, and the additional gain of 5 times corresponding to V _CIFF is realized by the corresponding multiple of the size of the transistor at the second differential input end of the comparator and the size of the transistor at the first differential input end.

The above second-order passive hybrid noise shaping technology samples and integrates the converted residual voltage through two sets of passive switched capacitor integrators, and then feeds the output of the two integrators to the The input sampling signal of the next cycle is converted together, so that the in-band quantization noise and comparator noise of the analog-to-digital converter are modulated to the high frequency band, and the second-order high-pass noise shaping effect is realized. This scheme can more effectively reduce quantization noise and comparator noise within the signal bandwidth, and can further improve the in-band signal-to-noise ratio of the analog-to-digital converter while maintaining a smaller chip area.

For the capacitive analog-to-digital conversion array (ie CDAC) 30, it includes: N pairs of capacitors and corresponding N pairs of switches. Wherein, each pair of capacitances corresponds to one data bit, specifically, the N pairs of capacitances include a pair of highest-level capacitances (including the highest-level capacitance on the positive side and the highest-level capacitance on the negative side) and N-1 pairs of other low-level capacitances ( Including N-2 middle low capacitors on the positive side, N-2 middle low capacitors on the negative side, and 1 lowest capacitor and 1 supplementary capacitor on the positive side), which in turn correspond to the highest data and low N- 1 bit of data.

Although oversampling and noise shaping techniques can effectively improve the in-band signal-to-noise ratio of the ADC, they cannot reduce the impact of the harmonic distortion introduced by the capacitor array mismatch on the ADC, and the latter often affects high-resolution analog converters. The signal-to-noise ratio of the digital converter has a greater impact.

In view of the above technical problems, in this embodiment, the input signal pre-skew technology based on prediction is aimed at the mechanism of feeding the low-bit conversion result of the previous preset cycle into the current conversion for the error feedback mismatch error shaping, using oversampling According to the characteristics of the conversion result of the previous preset cycle, the range of the "voltage value to be converted" after the low-order result is fed into the next cycle is predicted; Offset, so that the voltage to be converted does not exceed the full swing of the input signal range, ensuring that the dynamic range of the input is not affected. It should be noted that since this scheme uses a two-point prediction technique, it can effectively avoid introducing new harmonics.

In an embodiment, the digital data may be N-bit data, and the analog-to-digital converter may further include: a sampling switch circuit 60 , as shown in FIG. 1 .

Before the capacitances in the two capacitive analog-to-digital conversion arrays are reset to the initial state, the control logic circuit 40 is further configured to perform the following operations: according to the predicted value of the current preset period, the two The lower plates of the highest capacitors on the positive side and the negative side of the capacitive analog-to-digital conversion array are connected to different reference voltages; the sampling switch circuit is turned on to sample the input voltage of the current preset period to the the capacitive analog-to-digital conversion array; and disconnect the sampling switch circuit, and reset each capacitor in the capacitive analog-to-digital conversion array to an initial state, so as to feed in a pre-offset compensation corresponding to the reference voltage amount and the lower N-1 bit data in the N-bit data output in the last preset period.

Wherein, the control logic circuit 40 is used to connect the lower plates of the highest capacitors on the positive side and the negative side of the two capacitive analog-to-digital conversion arrays to different reference voltages may include: When the predicted value of the preset period is 1, connect the lower plate of the highest capacitor on the positive side and the negative side of the capacitive analog-to-digital conversion array located at the input positive terminal to the positive reference voltage, and connect the lower plate located at the input The lower plates of the highest capacitors on the positive and negative sides of the capacitive analog-to-digital conversion array at the negative end are connected to a negative reference voltage; The lower plate of the highest capacitor on the positive side and the negative side of the capacitive analog-to-digital conversion array located at the input positive terminal is connected to a negative reference voltage, and the positive terminal of the capacitive analog-to-digital conversion array located at the input negative terminal The bottom plate of the highest capacitor on the negative side and the negative side is connected to the positive reference voltage.

Wherein, the control logic circuit 40 is used to reset each capacitor in the capacitive analog-to-digital conversion array to the initial state may include: connecting the lower plate of the capacitor on the positive side in the capacitive analog-to-digital conversion array to to a positive reference voltage, and ground the lower plate of the capacitor on the negative side of the capacitive analog-to-digital conversion array.

Specifically, after obtaining the predicted value of the current preset period, control the lower plates of the highest capacitors of the two capacitive analog-to-digital conversion arrays 30 to be connected to the positive reference voltage according to the corresponding predicted results (predicted result is positive) or negative reference voltage (result is negative) input pre-offset to prepare for input pre-offset: when the result is positive, the lower plate of the highest capacitor on the positive (P) side is connected to Positive reference voltage, the lower plate of the highest capacitor on the negative (N) side is connected to the negative reference voltage; and when the predicted result is negative, vice versa.

At the beginning of a preset cycle, the control logic circuit 40 pulls the sampling control signal ΦCLKS high and maintains it for 4 clock cycles to turn on the sampling switch, so that the input signal can be differentially sampled to the capacitive modulus at the positive and negative ends. On the conversion array 30; the switches connected to the lower plates of the remaining low-level capacitors maintain the connection of the previous preset cycle unchanged, and the low-order conversion results of the last preset cycle are kept on the corresponding bits to realize (low-level capacitor phase higher than the highest bit capacitance) mismatch error shaping.

After the control signal ΦCLKS becomes low (that is, the sampling switch circuit 60 is disconnected), after a short delay, the start signal ΦRST is pulled low for one clock cycle to reset all the capacitors in the capacitive analog-to-digital conversion array 30 to Initial state: Connect the lower plates of all capacitors on the P side to the positive reference voltage, and connect the lower plates of all capacitors on the N side to ground. When reset, the feed-in of the low-bit conversion result of the previous preset cycle required for mismatch error shaping and the input pre-offset compensation required to eliminate the influence of mismatch error shaping ±1/2(V _REFP -V _REFN ) (in the case that the prediction value about the current preset period is 1, connect the lower plate of the highest capacitor on the positive side and the negative side of the capacitive analog-to-digital conversion array located at the input positive terminal to the positive The reference voltage, and the lower plate of the highest capacitor on the positive side and the negative side of the capacitive analog-to-digital conversion array at the input negative terminal are connected to the negative reference voltage, in this case, the amount of compensation introduced by the reset phase is Negative value, that is, -1/2(V _REFP -V _REFN ); otherwise, the compensation amount introduced in the reset phase is a positive value, that is, +1/2(V _REFP -V _REFN )) introduces two operations. The pre-offset operation can offset the input signal overload caused by feeding in the previous low-bit conversion result, so that the signal to be converted after feeding in is still within the normal input range of the analog-to-digital converter, thereby avoiding the error caused by mismatch error shaping. The resulting loss of input dynamic range. Since this scheme only needs to add an array adder, no additional dynamic element matching circuit is required, and the influence of the original mismatch error shaping scheme on the input dynamic range is eliminated, the implementation is simple and has good robustness.

Since the low N-1 bit data DAC _LSB (n-1) and the pre-offset compensation amount DAC _PRE (n) output in the previous preset period are introduced before conversion (that is, on the analog domain), as shown in Figure 6, Therefore, corresponding corrections can be made for the converted N-bit data of the current preset period.

After performing the step of outputting the digital data of the current preset period corresponding to the input voltage of the current preset period, the control logic circuit 40 is further configured to perform the following operation: output the current preset period The N-bit data minus the lower N-1 bit data in the N-bit data output in the previous preset cycle to obtain the N-bit difference; and subtracting the N-bit difference from the pre-offset A value corresponding to the compensation amount, so as to output the compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.

Specifically, since the low-bit signal of the previous preset period is added to the input signal in the analog domain, after the conversion is completed, in the digital domain, the 10-bit data D<1:10> (current The sum of the lower 9-bit data D _LSB (n) of the preset cycle n and the highest bit data D _MSB (n) of the current preset cycle n) enters the subtracter, and subtracts the value stored in the corresponding register with D<1:10> The lower 9-bit conversion result (that is, D _LSB (n-1)) of the last preset cycle n-1 of , as shown in Figure 6, so as to construct a corresponding The high-pass shaping transfer function (1-z ^-1 ) of (1-z -1 ) implements first-order high-pass mismatch error shaping.

The reason is as follows: Due to the mismatch of the actual low-side capacitance compared to the highest-side capacitance, the low-side conversion result of the mode converter (DAC) will carry a corresponding mismatch error E(n) (where DAC _LSB (n) represents the value left in CDAC The low-order conversion result on the lower plate of the corresponding capacitor, D _LSB (n) represents the result of the lower 9 bits in the output digital code except for the highest bit),

DAC _LSB (n)=D _LSB (n)+E(n);

The Mismatch Shaping (MES) technology relies on returning the lower bits of the conversion result of the previous cycle carrying the mismatch error E(n) to the current cycle, and constructing a high-pass shaping function for E(n). In the analog domain, it is only necessary to keep the low-order (LSB) result of the last conversion on the corresponding lower plate of the capacitor during the sampling period, and then reset the input signal and the DAC _LSB (n) after the sampling is completed. add up:

V _INPUT (n)+DAC _LSB (n-1)-DAC _MSB (n)-DAC _LSB (n)＝0;

Since the low-bit signal of the previous cycle is added to the input signal in the analog domain, after the conversion is completed, in the digital domain, the 10-bit output D<1:10> of the analog-to-digital converter enters the subtractor, and subtracts the corresponding The lower 9-bit conversion result of the previous cycle stored in the register is used to subtract the fed-in low-bit result of the previous cycle, and construct a corresponding high-pass shaping transfer function for the mismatch E(n) between the low-bit capacitance and the highest bit (1-z ^-1 ), implementing first-order high-pass mismatch error shaping:

D _OUT (n)=D _MSB (n)+D _LSB (n)−D _LSB (n−1).

Substituting the first two formulas above into the third formula, we can get

D _OUT (n)=V _INPUT (n)+E(n-1)-E(n),

That is:

D _OUT (z)=V _INPUT (z)+(1-z ^-1 )E(z),

It is equivalent to performing first-order high-pass shaping on the mismatch error carried in the output result.

Then, the above-mentioned subtraction result is sent to the adder-subtractor to subtract the value corresponding to the pre-offset compensation amount (that is, D _PRE (n) shown in FIG. 6 ), and the output result is used as the current preset Set the output digital quantity S<1:10> after period compensation. Specifically, according to the predicted value about the current preset period, in the case that the predicted value about the current preset period is 1, the compensation amount introduced in the reset phase is a negative value (that is, -1/2(V _REFP -V _REFN )), then add 1/2(V _REFP -V _REFN ) to the result of the above subtraction; on the contrary, when the predicted value of the preset period is 0, the compensation amount introduced in the reset phase is If it is a positive value (ie, +1/2(V _REFP −V _REFN )), then subtract 1/2(V _REFP −V _REFN ) from the result of the above subtraction.

After acquiring the compensated N-bit data of the current preset period, the control logic circuit 40 is further configured to combine the compensated N-bit data of the current preset period with the N-bit output of the current preset period The lower N-1 bits of the data are added together to obtain a predicted value for the next preset period.

Specifically, the output processing and prediction circuit 42 in the control logic circuit 40 combines the compensated N-bit data S<1:10> of the current preset period with the N-bit data output in the current preset period The lower N-1 bits of data D _LSB (n) are added together to obtain a predicted value for the next preset period.

According to whether the predicted value of the next preset period is positive or negative, the output processing and prediction circuit 42 further sets the corresponding control bit to 0 (the predicted value is positive) or 1 (the predicted value is negative), and then When the last clock rising edge of the current preset cycle and the ΦSET signal is high, the value of the control bit is sent to the control switch of the highest capacitor, and the input based on the input signal range prediction is realized by changing the lower plate of the highest capacitor. Signal pre-skew.

Since the analog-to-digital conversion process needs to use the corresponding result of the previous preset cycle, the corresponding preset cycle is defined in the above-mentioned embodiments, but it should be noted that each of the analog-to-digital conversion processes in the above-mentioned embodiments The steps are not limited to the corresponding preset period (eg, the current preset period), which can be similarly applied to each preset period (eg, the previous preset period or the next preset period).

The analog-to-digital conversion process in the current preset period is described below, which mainly includes the following steps S1-S8.

S1: On the rising edge of the last clock in the last preset cycle, the ΦSET signal is high, and according to the corresponding prediction result of the previous preset cycle to the current preset cycle, the positive side and the The lower plate of the highest capacitor on the negative side is connected to the positive reference voltage (the prediction result is positive) or the negative reference voltage (the result is negative) to prepare for the input pre-offset.

S2: When the current preset cycle starts, the sampling control signal ΦCLKS is pulled high and kept for 4 clock cycles to turn on the sampling switch, thereby differentially sampling the input signal to two capacitive analog-to-digital conversion arrays 30; The switch connected to the lower plate maintains the connection of the previous preset cycle unchanged, so as to keep the low-level conversion result of the previous preset cycle at the corresponding bit, so as to realize the mismatch (low-level capacitance compared with the highest-level capacitance) Error shaping.

S3: After the control signal ΦCLKS goes low, after a short delay, the start signal ΦRST is pulled low for one clock cycle, and all the capacitors in the two capacitive analog-to-digital conversion arrays 30 are reset to the initial state.

S4: After the ΦRST signal returns to high, the ΦCNV signal is pulled high to close the switches S _A9 -S _A12 in the passive switched capacitor integrator 10 and the switches S _B9 -S _B12 in the passive switched capacitor integrator 20, and no The sub-residual voltage V _EF of the previous preset period passively integrated in the source switched capacitor integrator 10 is passively multiplied by 2 times (that is, the first residual voltage is 2V _EF ) and connected in series with the input voltage, and Added to the first differential input terminal of the double differential input comparator 50; meanwhile, after the sub-residual voltage V _CIFF of the last preset period of the passive integration in the passive switched capacitor integrator 20 is passively multiplied by 2 times (ie, the second residual voltage is 2V _CIFF ) applied to the second differential input terminal.

S5: When the control signal ΦCNV is high, when the comparator control signal ΦCLKC is high, the double differential input comparator 50 uses the sum of the 2V _EF output by the passive switched capacitor integrator 10 and the input voltage as the first differential input signal; at the same time, the 2V _CIFF output by the passive switched capacitor integrator 10 is used as the second differential input signal, and the comparison result is output. According to the output of the comparator, the capacitors on the corresponding bits in the two capacitive analog-to-digital conversion arrays 30 are switched according to the switching scheme of splitting the switched capacitor arrays.

S6: After the conversion is completed, in the analog domain, the control signal ΦEF is pulled high to turn on the switches S _A1 -S _A8 in the passive switched capacitor integrator 10, and convert the residual on the upper plate of the capacitive analog-to-digital conversion array 30 The difference voltage is sampled to the integration capacitors C _A1 -C _A4 through the charge redistribution among the capacitors in a differential manner, so as to realize the first-order passive integration. After ΦEF returns to low, the control signal ΦCIFF is pulled high to turn on the switches S _B1 -S _B8 in the passive switched capacitor integrator 20, and convert the residual voltage on the upper plate of the capacitive analog-to-digital conversion array 30 in a differential manner The charge redistribution is used to sample to the integration capacitors C _B1 -C _B4 to realize the second-order passive integration.

S7: Since the low-bit signal of the previous preset period is added to the input signal in the analog domain, after the conversion is completed, in the digital domain, the 10-bit data D<1:10> output by the analog-to-digital converter enters the subtractor , subtract D _LSB (n-1) stored in the corresponding register from D<1:10>, as shown in Figure 6, to implement first-order high-pass mismatch error shaping. Then, the above-mentioned subtraction result is sent to the adder and subtractor, and the numerical value D _PRE (n) corresponding to the pre-offset compensation amount is subtracted from the predicted value of the current preset period, and the output result is used as the current preset period. Set the output digital quantity S<1:10> after period compensation.

S8: The output processing and prediction circuit 42 combines the compensated N-bit data S<1:10> of the current preset period with the lower N-1 bit data D _LSB of the N-bit data output in the current preset period (n) adding to obtain the predicted value for the next preset period. According to whether the predicted value of the next preset period is positive or negative, the output processing and prediction circuit 42 further sets the corresponding control bit to 0 (the predicted value is positive) or 1 (the predicted value is negative), and then When the last clock rising edge of the current preset cycle and the ΦSET signal is high, the value of the control bit is sent to the control switch of the highest capacitor, and the input based on the input signal range prediction is realized by changing the lower plate of the highest capacitor. Signal pre-skew.

The above-mentioned embodiment mainly adopts passive hybrid noise shaping technology and prediction-based input signal pre-skew technology to further improve the signal-to-noise ratio of the analog-to-digital converter. Higher signal-to-noise ratio and spurious-free dynamic range (SFDR) are achieved with a smaller chip area and lower power consumption. The above scheme can be applied to low-power sensor systems, which can effectively reduce the quantization noise within the signal bandwidth, improve the in-band signal-to-noise ratio of the analog-to-digital converter, and can be used in an environment with good mismatch error shaping (elimination) effect At the same time, the influence of the mismatch error shaping technology on the input dynamic range of the analog-to-digital converter is eliminated, and the resolution and linearity of the analog-to-digital converter in the system are effectively improved.

In summary, the present invention creatively closes the first switch group and the second switch group by controlling the logic circuit when the capacitors in the two capacitive analog-to-digital conversion arrays are reset to the initial state, making the first passive switched capacitor integrator output a first residual voltage, and closing the third switch group and the fourth switch group through a control logic circuit, so that the second passive switched capacitor integrator output the second residual voltage; the sum of the first residual voltage and the input voltage of the current preset period is received as the first differential input signal through a dual differential input comparator, and the second residual voltage is received as the second Differential input signals, and output comparison results; then output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison results through the control logic circuit, so as to output the current preset cycle The digital data of the current preset cycle corresponding to the input voltage. Therefore, the present invention adopts the second-order passive hybrid noise shaping technology to sample and integrate the residual voltage of the previous preset period through two sets of passive switched capacitor integrators, and respectively use error feedback and forward addition In this way, the output of the two integrators is fed into the input sampling signal of the current period and converted together, thereby modulating the in-band quantization noise and comparator noise of the analog-to-digital converter to the high frequency band, realizing the second-order high-pass noise shaping effect and suppressing the signal In-band correlated noise.

An embodiment of the present invention also provides a chip, which includes the analog-to-digital converter.

For the specific details and benefits of the chip provided by the embodiment of the present invention, please refer to the above-mentioned description of the analog-to-digital converter, which will not be repeated here.

The preferred embodiment of the present invention has been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the specific details of the above embodiment, within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, These simple modifications all belong to the protection scope of the present invention.

In addition, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable way if there is no contradiction. The combination method will not be described separately.

Those skilled in the art can understand that all or part of the steps in the method of the above-mentioned embodiments can be completed by instructing the relevant hardware through a program. (processor) executes all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

In addition, various combinations of different embodiments of the present invention can also be combined arbitrarily, as long as they do not violate the idea of the present invention, they should also be regarded as the disclosed content of the present invention.

Claims (10)

1. An analog-to-digital converter, the analog-to-digital converter comprising:

a first passive switched capacitor integrator, comprising: 2Q first capacitances and a first switch group connecting Q capacitances of the 2Q first capacitances in series and a second switch group connecting another Q capacitances of the 2Q first capacitances in series;

a second passive switched capacitor integrator comprising: 2Q second capacitances and a third switch group connecting Q of the 2Q second capacitances in series and a fourth switch group connecting another Q of the 2Q second capacitances in series;

two capacitive analog-to-digital conversion arrays;

the control logic circuit is used for closing the first switch group and the second switch group under the condition that the capacitors in the two capacitive analog-to-digital conversion arrays are reset to an initial state, so that the first passive switched capacitor integrator outputs a first residual voltage, and closing the third switch group and the fourth switch group, so that the second passive switched capacitor integrator outputs a second residual voltage, wherein the first residual voltage is the sum of first sub residual voltages of the 2Q first capacitors in a last preset period, and the second residual voltage is the sum of second sub residual voltages of the 2Q second capacitors in the last preset period; and

A dual differential input comparator for receiving a sum of the first residual voltage and an input voltage of a current preset period as a first differential input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result,

the control logic circuit is further configured to output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison result, so as to output digital data of a current preset period corresponding to the input voltage of the current preset period.

2. The analog-to-digital converter of claim 1, wherein the first passive switched-capacitor integrator further comprises: a fifth switch group connecting the 2Q first capacitors in parallel,

correspondingly, after outputting the digital data of the previous preset period corresponding to the input voltage of the previous preset period, the control logic circuit is further configured to distribute the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltages of the first capacitors are the first sub residual voltages.

3. The analog-to-digital converter of claim 2, wherein the second passive switched-capacitor integrator further comprises: a sixth switch group connecting the 2Q second capacitors in parallel,

Accordingly, after performing the step of distributing the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitances by closing the fifth switch group, the control logic is further configured to open the fifth switch group and distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitances by closing the sixth switch group such that the voltages of the second capacitances are the second sub-residual voltages.

4. The analog-to-digital converter of claim 1, wherein the digital data is N-bit data, and the analog-to-digital converter further comprises: the sampling switch circuit is used for sampling the data,

the control logic is further configured to, prior to resetting the capacitances in the two capacitive analog-to-digital conversion arrays to an initial state, perform the following operations:

according to the predicted value of the current preset period, connecting lower polar plates of the highest capacitors on the positive electrode side and the negative electrode side in the two capacitive analog-to-digital conversion arrays to different reference voltages;

switching on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital conversion array; and

And switching off the sampling switch circuit, and resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state so as to feed in a pre-offset compensation amount corresponding to the reference voltage and low-N-1 bit data in the N-bit data output in the last preset period.

5. The analog-to-digital converter of claim 4, wherein after performing the step of outputting digital data of a current preset period corresponding to the input voltage of the current preset period, the control logic circuit is further configured to:

subtracting low-N-1 bit data in the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference value; and

subtracting a value corresponding to the pre-offset compensation amount from the N-bit difference value to output compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.

6. The analog-to-digital converter of claim 5, wherein said control logic is further configured to add the compensated N-bit data of the current preset period to the low N-1 bit data of the N-bit data output from the current preset period to obtain a predicted value for the next preset period.

7. The analog-to-digital converter of claim 4, wherein the control logic circuit for connecting the bottom plates of the highest bit capacitances of the positive and negative sides of the two capacitive analog-to-digital conversion arrays to different reference voltages comprises:

connecting the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end to a positive reference voltage and the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end to a negative reference voltage, with a predicted value of 1 for the current preset period; or alternatively

In case that the predicted value for the current preset period is 0, the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end are connected to a negative reference voltage, and the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end are connected to a positive reference voltage.

8. The analog-to-digital converter of claim 4, wherein the control logic circuit for resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state comprises:

The lower plate of the capacitor on the positive side in the capacitive analog-to-digital conversion array is connected to a positive reference voltage, and the lower plate of the capacitor on the negative side in the capacitive analog-to-digital conversion array is grounded.

9. The analog-to-digital converter of claim 1, wherein said first passive switched capacitor integrator comprises 4 first capacitors; and the second passive switched capacitor integrator comprises 4 second capacitors,

wherein the capacitance value of the first capacitor and the second capacitor is equal to 1/2 times of the total capacitance value of the capacitive analog-to-digital conversion array.

10. Chip, characterized in that it comprises an analog-to-digital converter according to any of claims 1-9.

Images