CN116405016A

CN116405016A - Low-voltage PMOS switch circuit, system, control method and control device

Info

Publication number: CN116405016A
Application number: CN202310683546.0A
Authority: CN
Inventors: 刘涛; 张世东
Original assignee: Chengdu Bor Microcrystalline Technology Co ltd; Xtx Technology Inc
Current assignee: Chengdu Bor Microcrystalline Technology Co ltd; Xtx Technology Inc
Priority date: 2023-06-09
Filing date: 2023-06-09
Publication date: 2023-07-07

Abstract

The invention relates to the technical field of switching circuits, and particularly discloses a low-voltage PMOS switching circuit, a system, a control method and a control device, wherein the low-voltage PMOS switching circuit comprises a power input end, a PMOS switching tube, a power voltage detector, a logic controller, a first switch, a second switch and a negative-voltage charge pump; the low-voltage PMOS switching circuit detects the voltage of the power input end in real time based on the power voltage detector and generates a detection signal used for judging whether the voltage of the power input end can drive the PMOS switching tube to be conducted or not, namely, the detection signal characterizes whether the voltage of the power input end meets the condition of driving the PMOS switching tube to be conducted or not, so that the logic controller can control the grid electrode of the PMOS switching tube to be grounded through a second switch or connected into a negative-pressure charge pump according to the detection signal, and the PMOS switching tube can generate grid source voltage with a large absolute value enough to be conducted through the negative-pressure charge pump under the low-voltage state.

Description

Low-voltage PMOS switch circuit, system, control method and control device

Technical Field

The application relates to the technical field of switching circuits, in particular to a low-voltage PMOS switching circuit, a system, a control method and a control device.

Background

MOS transistor drive circuits are common circuits in analog circuit design, widely distributed in various products: such as DCDC converters, LDO circuits, motor driver drivers, etc.

The PMOS switch circuit is conducted by grounding the gate voltage of the PMOS switch tube to a low level so that a large enough starting voltage (voltage difference) exists between the source electrode and the gate electrode of the PMOS switch tube; however, in some cases, there is a problem that the PMOS switching tube is not turned on or is in the subthreshold region due to insufficient turn-on voltage, which results in failure of conduction of the PMOS switching tube and affects key indexes such as product performance and conduction resistance, that is, the existing PMOS switching circuit has a problem that it cannot be turned on under the condition of low operating voltage.

In view of the above problems, no effective technical solution is currently available.

Disclosure of Invention

The invention aims to provide a low-voltage PMOS switching circuit, a system, a control method and a control device, so that the PMOS switching circuit can smoothly conduct a PMOS switching tube when working voltage is in a low-voltage state.

In a first aspect, the present application provides a low-voltage PMOS switch circuit for controlling circuit on-off, the low-voltage PMOS switch circuit includes:

the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a logic controller, a first switch, a second switch and a negative voltage charge pump;

the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch;

one end of the power supply voltage detector is connected with the power supply input end, and the other end of the power supply voltage detector is connected with the logic controller and is used for outputting a detection signal to the logic controller according to the voltage of the power supply input end;

the logic controller is connected with the negative-pressure charge pump, the first switch and the second switch, and is used for controlling the on-off of the first switch, controlling the running state of the negative-pressure charge pump according to the detection signal and controlling the on-off of the second switch.

The low-voltage PMOS switch circuit detects the voltage of the power input end in real time based on the power voltage detector, and generates the detection signal used for judging whether the voltage of the power input end can drive the PMOS switch tube to conduct, namely, whether the voltage of the power input end meets the condition of driving the PMOS switch tube to conduct is characterized by the detection signal, so that the logic controller can control the grid electrode of the PMOS switch tube to be grounded through the second switch or connected into the negative-pressure charge pump according to the detection signal, and the PMOS switch tube can generate grid source voltage with an absolute value large enough to conduct through the negative-pressure charge pump under the low-voltage state.

The logic controller is connected with the negative-pressure charge pump through a clock component, and the clock component is used for generating two complementary clock signals to control the negative-pressure charge pump to operate.

In this example, the negative charge pump is a charge pump circuit that outputs a negative voltage based on the alternate input of two complementary clock signals, and therefore, the logic controller controls the operation of the negative charge pump by controlling the input state of the clock component to the negative charge pump to operate the negative charge pump when the input voltage is in a low-voltage state to increase the absolute value of the gate-source voltage of the PMOS switching transistor, and to stop the operation of the negative charge pump when the input voltage is in a non-low-voltage state to ground the PMOS switching transistor through the second switch to control the conduction.

The low-voltage PMOS switch circuit further comprises a third switch, the second end of the negative-pressure charge pump is grounded through the third switch, and the third switch is connected with the logic controller and is controlled to be on-off by the logic controller.

The low-voltage PMOS switch circuit further comprises a pull-down resistor, and the grid electrode of the PMOS switch is connected with the first end of the negative-pressure charge pump and one end of the second switch through the pull-down resistor.

The low-voltage PMOS switch circuit is characterized in that the first switch and the second switch are MOS transistors, and the grid electrodes of the first switch and the second switch are connected with the logic controller.

The low-voltage PMOS switch circuit is characterized in that the first switch is a PMOS tube, and the second switch is an NMOS tube.

In a second aspect, the present application further provides a low-voltage PMOS switching system for controlling on-off of a circuit, the system including a low-voltage PMOS switching circuit, the low-voltage PMOS switching circuit including: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a logic controller, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end, and the other end of the power supply voltage detector is connected with the logic controller and is used for outputting a detection signal to the logic controller according to the voltage of the power supply input end; the logic controller is connected with the negative-pressure charge pump, the first switch and the second switch;

the logic controller is used for controlling the first switch to be turned off when the PMOS switching tube needs to be turned on;

the logic controller is further configured to control the second switch to be turned off and control the negative-pressure charge pump to operate when the detection signal indicates that the input voltage is smaller than a preset voltage, so that the gate voltage of the PMOS switching tube drops to a negative voltage;

and the logic controller is also used for controlling the second switch to be conducted and controlling the negative-pressure charge pump to stop running when the detection signal indicates that the input voltage is greater than or equal to the preset voltage, so that the grid voltage of the PMOS switch tube is zero.

The low-voltage PMOS switch system detects the voltage of the power input end in real time based on the power voltage detector, and generates the detection signal used for judging whether the voltage of the power input end can drive the PMOS switch tube to conduct, namely, whether the voltage of the power input end meets the condition of driving the PMOS switch tube to conduct is characterized by the detection signal, so that the logic controller can control the grid electrode of the PMOS switch tube to be grounded through the second switch or connected into the negative-pressure charge pump according to the detection signal, and the PMOS switch tube can generate grid source voltage with an absolute value large enough to conduct through the negative-pressure charge pump under the low-voltage state.

The low-voltage PMOS switch system comprises a logic controller, wherein the logic controller is connected with a negative-voltage charge pump, and the low-voltage PMOS switch system comprises a low-voltage PMOS switch circuit, wherein the low-voltage PMOS switch circuit further comprises a third switch, the second end of the negative-voltage charge pump is grounded through the third switch, and the third switch is connected with the logic controller;

the logic controller is further configured to control the third switch to be turned on when the detection signal indicates that the input voltage is less than a preset voltage, and control the third switch to be turned off when the detection signal indicates that the input voltage is greater than or equal to the preset voltage.

In a third aspect, the present application further provides a low-voltage PMOS switch control method, configured to control on-off of a circuit, where the control method is applied to a low-voltage PMOS switch circuit, and the low-voltage PMOS switch circuit includes: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end and is used for outputting a detection signal according to the voltage of the power supply input end;

the method comprises the following steps:

acquiring a switch enabling signal;

when a switch enabling signal is turned on, the first switch is controlled to be turned off, and the detection signal is obtained;

when the detection signal indicates that the input voltage is smaller than a preset voltage, the second switch is controlled to be turned off, and the negative-pressure charge pump is controlled to operate, so that the grid voltage of the PMOS switching tube is reduced to be negative pressure;

when the detection signal indicates that the input voltage is greater than or equal to a preset voltage, the second switch is controlled to be turned on, and the negative-pressure charge pump is controlled to stop running, so that the grid voltage of the PMOS switching tube is zero.

According to the low-voltage PMOS switch control method, the voltage of the power input end is detected in real time based on the power voltage detector, and a detection signal used for judging whether the voltage of the power input end can drive the PMOS switch tube to conduct is generated, namely whether the voltage of the power input end meets the condition of driving the PMOS switch tube to conduct is represented by the detection signal, so that the grid electrode of the PMOS switch tube is controlled to be grounded through the second switch or connected into the negative-pressure charge pump according to the detection signal, and the PMOS switch tube can generate grid source voltage with a large absolute value enough to conduct through the negative-pressure charge pump in a low-voltage state.

In a fourth aspect, the present application further provides a low-voltage PMOS switch control device, configured to control on-off of a circuit, where the control device is applied to a low-voltage PMOS switch circuit, and the low-voltage PMOS switch circuit includes: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end and is used for outputting a detection signal according to the voltage of the power supply input end;

the device comprises:

the first acquisition module is used for acquiring a switch enabling signal;

the second acquisition module is used for controlling the first switch to be turned off and acquiring the detection signal when the switch enabling signal is turned on;

the first control module is used for controlling the second switch to be turned off and controlling the negative-pressure charge pump to operate when the detection signal indicates that the input voltage is smaller than the preset voltage, so that the grid voltage of the PMOS switching tube is reduced to be negative pressure;

and the second control module is used for controlling the second switch to be conducted and controlling the negative-pressure charge pump to stop running when the detection signal indicates that the input voltage is greater than or equal to the preset voltage, so that the grid voltage of the PMOS switching tube is zero.

The low-voltage PMOS switch control device detects the voltage of the power input end in real time based on the power voltage detector, and generates a detection signal used for judging whether the voltage of the power input end can drive the PMOS switch tube to be conducted or not, so that the grid electrode of the PMOS switch tube is controlled to be grounded through the second switch or connected into the negative-pressure charge pump according to the detection signal, and the PMOS switch tube can generate grid source voltage with an absolute value large enough to be conducted through the negative-pressure charge pump under the low-voltage state.

As can be seen from the above, the present application provides a low-voltage PMOS switch circuit, a system, a control method and a control device, where the low-voltage PMOS switch circuit detects the voltage of the power input end in real time based on a power voltage detector, and generates a detection signal for determining whether the voltage of the power input end can drive the PMOS switch tube to be turned on, that is, the detection signal characterizes whether the voltage of the power input end meets the condition of driving the PMOS switch tube to be turned on, so that the logic controller can control the gate of the PMOS switch tube to be grounded through the second switch or connected to the negative-pressure charge pump according to the detection signal, so that the PMOS switch tube can generate a gate-source voltage with a sufficiently large absolute value through the negative-pressure charge pump to be turned on in a low-voltage state.

Drawings

Fig. 1 is a schematic structural diagram of a low-voltage PMOS switch circuit according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a low-voltage PMOS switching system according to an embodiment of the present application.

Fig. 3 is a flowchart of a low-voltage PMOS switch control method according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a low-voltage PMOS switch control device according to an embodiment of the present application.

Reference numerals: vin, power supply input; l1, a power supply voltage detector; CTRL, logic controller; s1, a first switch; s2, a second switch; s3, a third switch; CP, negative pressure charge pump; PC, PMOS switching tube; CLK, clock component; r, pull-down resistor; p1, a first PMOS tube; p2, a second PMOS tube; p3, a third PMOS tube; p4, a fourth PMOS tube; n1, a first NMOS tube; n2, a second NMOS tube; 401. a first acquisition module; 402. a second acquisition module; 4031. a first control module; 4032. and a second control module.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

The PMOS switch circuit is conducted by grounding the gate voltage of the PMOS switch tube to a low level so that a large enough starting voltage (voltage difference) exists between the source electrode and the gate electrode of the PMOS switch tube; however, in some cases, there is a problem that the PMOS switching tube is not turned on or is in the subthreshold region due to insufficient turn-on voltage, which results in failure of the PMOS switching tube to turn on, thereby affecting key indexes such as product performance and on-resistance.

Under the condition of lower working voltage, the existing PMOS switching circuit has the problem of non-conduction, for example: the threshold voltage vth=1.2v of the PMOS switching tube of the 5V LDMOS of the SMIC18 process at-40 ℃ _ss; the threshold voltage vth=1.8v of the PMOS switching tube in the 5V LDMOS in the GFC18 process at-40 ℃ _ss, if the product definition input voltage is 1V to 5.5V, if the working voltage is 1-1.2V, the PMOS switching tube cannot be normally turned on by the 5V LDMOS in the smic18 process, and if the working voltage is 1-1.8V, the PMOS switching tube cannot be normally turned on by the 5V LDMOS in the GFC18 process.

In a first aspect, referring to fig. 1, some embodiments of the present application provide a low-voltage PMOS switch circuit for controlling on-off of a circuit, the low-voltage PMOS switch circuit includes:

the power supply input end Vin, the PMOS switch tube PC, the power supply voltage detector L1, the logic controller CTRL, the first switch S1, the second switch S2 and the negative-pressure charge pump CP;

the power input end Vin is connected with the source electrode of the PMOS switch tube PC, the power input end Vin is also connected with the grid electrode of the PMOS switch tube PC through the first switch S1, the grid electrode of the PMOS switch tube PC is also connected with the first end of the negative pressure charge pump CP, the second end of the negative pressure charge pump CP is grounded, and the first end of the negative pressure charge pump CP is also grounded through the second switch S2;

one end of the power supply voltage detector L1 is connected with the power supply input end Vin, and the other end of the power supply voltage detector L is connected with the logic controller CTRL and is used for outputting a detection signal to the logic controller CTRL according to the voltage of the power supply input end Vin;

the logic controller CTRL is connected to the negative-pressure charge pump CP, the first switch S1, and the second switch S2, and is configured to control on-off of the first switch S1, and is configured to control an operation state of the negative-pressure charge pump CP according to a detection signal, and control on-off of the second switch S2.

Specifically, the PMOS switching transistor PC has a conduction condition in which the gate-source voltage is negative and the absolute value is greater than the threshold voltage.

More specifically, the embodiment of the present application aims to provide a control circuit capable of driving a PMOS switch tube PC to normally switch even in a low-voltage environment, where the first switch S1 is a current switch of the PMOS switch tube PC and is controlled by a logic controller CTRL, when the first switch S1 is turned on, a power input terminal Vin is connected to a gate and a source of the PMOS switch tube at the same time, so that a gate-source voltage of the PMOS switch tube PC is zero, and it is ensured that the PMOS switch tube PC is not turned on, that is, when the PMOS switch tube PC needs to be turned off, the logic controller CTRL can ensure that the PMOS switch tube PC is always turned off by controlling the first switch S1 to be turned off, and when the PMOS switch tube PC needs to be turned on, the logic controller CTRL can disconnect a gate of the PMOS switch tube PC from the power input terminal Vin, so that a gate voltage of the PMOS switch tube PC is discharged to zero or is pulled down to be negative based on a negative voltage, so that the gate-source voltage of the PMOS switch tube PC is negative and absolute value is greater than a threshold voltage of the PMOS switch tube PC, and the PMOS switch tube PC is turned on.

More specifically, the power voltage detector L1 is configured to detect the voltage of the power input terminal Vin and generate a corresponding detection signal to the logic controller CTRL, where the detection signal may be a data signal including the voltage, or may be a determination signal reflecting whether the voltage reaches a desired level, in this embodiment, it is preferable that the power voltage detector L1 is configured to compare the voltage of the power input terminal Vin with a preset voltage, that is, the power voltage detector L1 is configured to compare the voltage of the power input terminal Vin with the preset voltage to generate a detection signal representing a high level or a low level to the logic controller CTRL so as to reflect whether the voltage of the power input terminal Vin reaches above the preset voltage, and therefore, in this embodiment, the power voltage detector L1 is preferably a comparator circuit.

More specifically, when the first switch S1 is turned off, the PMOS switching transistor PC only has a source connected to the voltage of the power input terminal Vin (hereinafter referred to as the input voltage), so that the gate-source voltage of the PMOS switching transistor PC can be ensured to be negative, and the low-voltage PMOS switching circuit of the embodiment of the present application sets the power voltage detector to determine whether the input voltage is large enough to generate a gate-source voltage of the PMOS switching transistor PC small enough to drive the PMOS switching transistor PC to be turned on; when the input voltage is too small, the logic controller CTRL can control the second switch S2 to be turned off, and the negative-pressure charge pump CP to operate to generate negative pressure and apply the negative pressure to the gate of the PMOS switching tube PC, so that the PMOS switching tube PC has a sufficiently small gate-source voltage (the absolute value is greater than the threshold voltage) to drive the PMOS switching tube PC to be turned on; when the input voltage is large enough, the logic controller CTRL can control the second switch S2 to be turned on and the negative-pressure charge pump CP to stop running, so that the gate of the PMOS switch tube PC is grounded to zero, and the absolute value of the gate-source voltage of the PMOS switch tube PC is equal to the input voltage, so as to drive the PMOS switch tube PC to be turned on, and avoid the negative-pressure charge pump CP from adding additional power consumption and avoid the PMOS switch tube PC from being damaged due to the excessively large absolute value of the gate-source voltage.

More specifically, the logic controller may be a semi-custom circuit, or may be a digital circuit constructed based on logic gates, and is configured to trigger and control the operation state of the negative-pressure charge pump CP, the on-off of the first switch S1, and the on-off of the second switch S2 according to the on-off state required by the PMOS switch PC and the detection signal, for example, the on-off state of the first switch S1 may be changed by generating a corresponding high-level signal or a corresponding low-level signal through an in-phase buffer or an inverter according to the enable signal representing the on-off state required by the PMOS switch PC, and the on-off state of the negative-pressure charge pump CP may be changed by generating a corresponding high-level signal or a corresponding low-level signal through a dual-input and gate according to the enable signal representing the on-off state required by the PMOS switch PC and the detection signal.

More specifically, the negative-pressure charge pump CP may use an existing one-stage or multi-stage negative-pressure charge pump to generate a voltage drop to the gate of the PMOS switching transistor PC to form a negative pressure; in the embodiment of the present application, the negative voltage charge pump CP is preferably a primary negative voltage charge pump, and generates a negative voltage based on an input voltage, so that the PMOS switching tube PC can generate a gate-source voltage with an absolute value twice the input voltage, so as to ensure that the PMOS switching tube PC can still be turned on in a low voltage state.

More specifically, the drain of the PMOS switching transistor PC is the voltage output terminal Vout.

According to the low-voltage PMOS switch circuit, the voltage of the power input end Vin is detected in real time based on the power voltage detector L1, and a detection signal used for judging whether the voltage of the power input end Vin can drive the PMOS switch tube PC to be conducted is generated, namely whether the voltage of the power input end meets the condition of driving the PMOS switch tube PC to be conducted is represented by the detection signal, so that the logic controller CTRL can control the grid electrode of the PMOS switch tube PC to be grounded through the second switch S2 or connected into the negative-pressure charge pump CP according to the detection signal, and the PMOS switch tube PC can generate a grid source voltage with a sufficient absolute value to be conducted through the negative-pressure charge pump CP in a low-voltage state.

In some preferred embodiments, the logic controller CTRL is connected to the negative charge pump CP via a clock component CLK, which is used to generate two complementary clock signals to control the operation of the negative charge pump CP.

Specifically, the negative charge pump CP is a charge pump circuit that outputs a negative voltage based on the alternate input of two complementary clock signals, and thus, in the embodiment of the present application, the logic controller CTRL controls the operation of the negative charge pump CP by controlling the input state of the clock component CLK to the negative charge pump CP to operate the negative charge pump CP when the input voltage is in the low-voltage state to increase the absolute value of the gate-source voltage of the PMOS switching transistor PC, and stops the operation of the negative charge pump CP when the input voltage is in the non-low-voltage state to ground the PMOS switching transistor PC through the second switch S2 to control the conduction.

In some preferred embodiments, as shown in fig. 2, the negative pressure charge pump CP is a primary negative pressure charge pump, comprising: the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1 and the second NMOS tube N2; the source, the drain and the substrate of the first PMOS transistor P1 are all connected to the first clock signal CLKA, the source, the drain and the substrate of the second PMOS transistor P2 are all connected to the second clock signal CLKB, the gate of the first PMOS transistor P1 is connected to the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1, the gate of the second PMOS transistor P2 is connected to the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the gate of the PMOS switch PC, the source of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4 and is connected to the drain of the fourth PMOS transistor P4, and the gate of the second NMOS transistor N2 is connected to the gate of the third PMOS transistor P3 and the drain of the fourth PMOS transistor P3, the third PMOS transistor P3, the first NMOS transistor N1 and the second NMOS transistor N2 are all drain-source-drain connections.

Specifically, the first PMOS transistor P1 and the second PMOS transistor P2 in the primary negative-pressure charge pump serve as capacitors.

In some preferred embodiments, the negative-pressure charge pump CP further includes a third switch S3, where the second end of the negative-pressure charge pump CP is grounded through the third switch S3, and the third switch S3 is connected to the logic controller CTRL and is controlled to be turned on or off by the logic controller CTRL.

Specifically, in this embodiment, when the negative-pressure charge pump CP is running, the logic controller CTRL controls the third switch S3 to be turned on, so that the sources of the third PMOS transistor P3 and the fourth PMOS transistor of the negative-pressure charge pump CP are grounded, and further, the sources of the first NMOS transistor N1 and the second NMOS transistor N2 can alternately generate negative pressure to supply to the gate of the PMOS switch PC; when the negative-pressure charge pump CP stops operating, the logic controller CTRL controls the third switch S3 to be turned off and the second switch S2 to be turned on, so that the gate of the PMOS switching transistor PC is grounded.

In some preferred embodiments, the PMOS switch further includes a pull-down resistor R, and the gate of the PMOS switch is connected to the first terminal of the negative voltage charge pump CP and one terminal of the second switch S2 through the pull-down resistor R.

Specifically, the pull-down resistor R can perform a current limiting function, and smoothly clamp the gate voltage of the PMOS switching transistor PC to zero or a negative voltage value generated by the negative voltage charge pump CP.

In some preferred embodiments, the first switch S1 and the second switch S2 are both MOS transistors, and the gates of both are connected to the logic controller CTRL.

Specifically, in this embodiment, the logic controller CTRL can directly generate a high level or low level signal to be applied to the gate of the corresponding MOS transistor to control on/off of the switch, which has the characteristics of small volume, simple response logic and fast response speed.

In some preferred embodiments, the first switch S1 is a PMOS transistor and the second switch S2 is an NMOS transistor.

In some preferred embodiments, the third switch S3 is an NMOS transistor.

In a second aspect, referring to fig. 2, some embodiments of the present application further provide a low-voltage PMOS switching system, configured to control on/off of a circuit, where the system includes a low-voltage PMOS switching circuit, and the low-voltage PMOS switching circuit includes: the power supply input end Vin, the PMOS switch tube PC, the power supply voltage detector L1, the logic controller CTRL, the first switch S1, the second switch S2 and the negative-pressure charge pump CP; the power input end Vin is connected with the source electrode of the PMOS switch tube PC, the power input end Vin is also connected with the grid electrode of the PMOS switch tube PC through the first switch S1, the grid electrode of the PMOS switch tube PC is also connected with the first end of the negative pressure charge pump CP, the second end of the negative pressure charge pump CP is grounded, and the first end of the negative pressure charge pump CP is also grounded through the second switch S2; one end of the power supply voltage detector L1 is connected with the power supply input end Vin, and the other end of the power supply voltage detector L is connected with the logic controller CTRL and is used for outputting a detection signal to the logic controller CTRL according to the voltage of the power supply input end Vin; the logic controller CTRL is connected with the negative-pressure charge pump CP, the first switch S1 and the second switch S2;

the logic controller CTRL is configured to control the first switch S1 to be turned off when the PMOS switching transistor PC needs to be turned on;

the logic controller CTRL is further configured to control the second switch S2 to be turned off and control the negative-pressure charge pump CP to operate when the detection signal indicates that the input voltage is less than the preset voltage, so that the gate voltage of the PMOS switching tube PC drops to a negative voltage;

the logic controller CTRL is further configured to control the second switch S2 to be turned on and control the negative-pressure charge pump CP to stop operating when the detection signal indicates that the input voltage is greater than or equal to the preset voltage, so that the gate voltage of the PMOS switching tube PC is zero.

Specifically, the preset voltage is a preset voltage value for judging whether the input voltage has enough conduction driving capability to drive the PMOS switching transistor PC; it should be noted that the preset voltage is set according to the size specification and the usage scenario of the PMOS switching transistor PC, and in this embodiment of the present application, the preset voltage is preferably 1.5-2.5V, which is suitable for controlling the PMOS switch in the driving circuit on the market.

More specifically, in this embodiment, when the PMOS switching transistor PC needs to be turned off, the logic controller CTRL controls the first switch S1 to be turned on, so that the gate-source voltage of the PMOS switching transistor PC is zero, thereby keeping the PMOS switching transistor PC in a high-resistance state all the time and making the drain thereof not perform voltage output.

According to the low-voltage PMOS switching system, the voltage of the power input end Vin is detected in real time based on the power voltage detector L1, and a detection signal used for judging whether the voltage of the power input end Vin can drive the PMOS switching tube PC to be conducted is generated, namely whether the voltage of the power input end meets the condition of driving the PMOS switching tube to be conducted is represented by the detection signal, so that the logic controller CTRL can control the grid electrode of the PMOS switching tube PC to be grounded through the second switch S2 or connected into the negative-pressure charge pump CP according to the detection signal, and the PMOS switching tube PC can generate a grid source voltage with a sufficient absolute value to be conducted through the negative-pressure charge pump CP in a low-voltage state.

In some preferred embodiments, the low-voltage PMOS switching circuit further includes a third switch S3, the second end of the negative-voltage charge pump CP is grounded through the third switch S3, and the third switch S3 is connected to the logic controller CTRL;

the logic controller CTRL is further configured to control the third switch S3 to be turned on when the detection signal indicates that the input voltage is less than the preset voltage, and control the third switch S3 to be turned off when the detection signal indicates that the input voltage is greater than or equal to the preset voltage.

In a third aspect, referring to fig. 3, some embodiments of the present application further provide a low-voltage PMOS switch control method, configured to control on-off of a circuit, where the control method is applied to a low-voltage PMOS switch circuit, and the low-voltage PMOS switch circuit includes: the power supply input end Vin, the PMOS switch tube PC, the power supply voltage detector L1, the first switch S1, the second switch S2 and the negative-pressure charge pump CP; the power input end Vin is connected with the source electrode of the PMOS switch tube PC, the power input end Vin is also connected with the grid electrode of the PMOS switch tube PC through the first switch S1, the grid electrode of the PMOS switch tube PC is also connected with the first end of the negative pressure charge pump CP, the second end of the negative pressure charge pump CP is grounded, and the first end of the negative pressure charge pump CP is also grounded through the second switch S2; one end of the power supply voltage detector L1 is connected with the power supply input end Vin and is used for outputting a detection signal according to the voltage of the power supply input end Vin;

the method comprises the following steps:

s1, acquiring a switch enabling signal;

s2, when the switch enabling signal is turned on, the first switch S1 is controlled to be turned off, and a detection signal is obtained;

s31, when the detection signal indicates that the input voltage is smaller than the preset voltage, the second switch S2 is controlled to be turned off, and the negative-pressure charge pump CP is controlled to operate, so that the grid voltage of the PMOS switching tube PC is reduced to negative pressure;

and S32, when the detection signal indicates that the input voltage is greater than or equal to a preset voltage, controlling the second switch S2 to be turned on, and controlling the negative-pressure charge pump CP to stop running so as to enable the grid voltage of the PMOS switch tube PC to be zero.

Specifically, the switch enabling signal represents the on-off state required by the PMOS switch tube PC, and is generated by the upper control end of the low-voltage PMOS switch circuit, which may be a control chip, a driving chip, etc. of the power supply.

More specifically, in the embodiment of the present application, the on (representing a high level) of the switch enable signal indicates that the PMOS switching transistor needs to be switched to the on state, and the off (representing a low level) of the switch enable signal indicates that the PMOS switching transistor needs to be switched to the off state.

According to the low-voltage PMOS switch control method, the voltage of the power input end Vin is detected in real time based on the power voltage detector L1, and a detection signal used for judging whether the voltage of the power input end Vin can drive the PMOS switch tube PC to be conducted is generated, namely whether the voltage of the power input end meets the condition of driving the PMOS switch tube PC to be conducted is represented by the detection signal, so that the grid electrode of the PMOS switch tube PC is controlled to be grounded through the second switch S2 or connected into the negative-pressure charge pump CP according to the detection signal, and the PMOS switch tube PC can generate grid source voltage with a large absolute value enough to be conducted through the negative-pressure charge pump CP in a low-voltage state.

In a fourth aspect, referring to fig. 4, some embodiments of the present application further provide a low-voltage PMOS switch control device, configured to control on-off of a circuit, where the control device is applied to a low-voltage PMOS switch circuit, and the low-voltage PMOS switch circuit includes: the power supply input end Vin, the PMOS switch tube PC, the power supply voltage detector L1, the first switch S1, the second switch S2 and the negative-pressure charge pump CP; the power input end Vin is connected with the source electrode of the PMOS switch tube PC, the power input end Vin is also connected with the grid electrode of the PMOS switch tube PC through the first switch S1, the grid electrode of the PMOS switch tube PC is also connected with the first end of the negative pressure charge pump CP, the second end of the negative pressure charge pump CP is grounded, and the first end of the negative pressure charge pump CP is also grounded through the second switch S2; one end of the power supply voltage detector L1 is connected with the power supply input end Vin and is used for outputting a detection signal according to the voltage of the power supply input end Vin;

the device comprises:

a first acquisition module 401, configured to acquire a switch enable signal;

a second obtaining module 402, configured to control the first switch S1 to be turned off and obtain a detection signal when the switch enable signal is turned on;

the first control module 4031 is configured to control the second switch S2 to be turned off and control the negative-pressure charge pump CP to operate when the detection signal indicates that the input voltage is less than the preset voltage, so that the gate voltage of the PMOS switch tube PC drops to a negative voltage;

the second control module 4032 is configured to control the first switch S1 to be turned off and the second switch S2 to be turned on, and control the negative-pressure charge pump CP to stop operating when the detection signal indicates that the input voltage is greater than or equal to the preset voltage, so that the gate voltage of the PMOS switch tube PC is zero.

According to the low-voltage PMOS switch control device, the voltage of the power input end Vin is detected in real time based on the power voltage detector L1, and a detection signal used for judging whether the voltage of the power input end Vin can drive the PMOS switch tube PC to be conducted is generated, namely whether the voltage of the power input end meets the condition of driving the PMOS switch tube PC to be conducted is represented by the detection signal, the grid electrode of the PMOS switch tube PC is controlled to be grounded through the second switch S2 or connected into the negative-pressure charge pump CP according to the detection signal, and the PMOS switch tube PC can generate grid source voltage with an absolute value large enough to be conducted through the negative-pressure charge pump CP in a low-voltage state.

In summary, the embodiment of the application provides a low-voltage PMOS switch circuit, a system, a control method and a control device, wherein the low-voltage PMOS switch circuit detects the voltage of a power input end Vin in real time based on a power voltage detector L1, and generates a detection signal for judging whether the voltage of the power input end Vin can drive a PMOS switch tube PC to be conducted, so that a logic controller CTRL can control a gate of the PMOS switch tube PC to be grounded through a second switch S2 or connected to a negative-pressure charge pump CP according to the detection signal, and the PMOS switch tube PC can generate a gate-source voltage with a sufficiently large absolute value through the negative-pressure charge pump CP to be conducted in a low-voltage state.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A low-voltage PMOS switch circuit for controlling the on-off of a circuit, the low-voltage PMOS switch circuit comprising:

2. The low voltage PMOS switching circuit of claim 1, wherein said logic controller is coupled to said negative voltage charge pump through a clock assembly, said clock assembly for generating two complementary clock signals to control operation of said negative voltage charge pump.

3. The low voltage PMOS switching circuit of claim 1, further comprising a third switch, said negative voltage charge pump second terminal being connected to ground through said third switch, said third switch being connected to and controlled by said logic controller.

4. The low voltage PMOS switch circuit of claim 1, further comprising a pull-down resistor, a gate of said PMOS switch being connected to a first terminal of said negative voltage charge pump and to a terminal of said second switch through said pull-down resistor.

5. The low voltage PMOS switch circuit of claim 1, wherein said first switch and said second switch are MOS transistors, and wherein both gates are connected to said logic controller.

6. The low voltage PMOS switching circuit of claim 5, wherein said first switch is a PMOS transistor and said second switch is an NMOS transistor.

7. A low voltage PMOS switching system for controlling the on-off of a circuit, said system comprising a low voltage PMOS switching circuit comprising: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a logic controller, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end, and the other end of the power supply voltage detector is connected with the logic controller and is used for outputting a detection signal to the logic controller according to the voltage of the power supply input end; the logic controller is connected with the negative-pressure charge pump, the first switch and the second switch;

and the logic controller is also used for controlling the second switch to be conducted and controlling the negative-pressure charge pump to stop running when the detection signal indicates that the input voltage is greater than or equal to a preset voltage, so that the grid voltage of the PMOS switching tube is zero.

8. The low voltage PMOS switching system of claim 7, further comprising a third switch, said negative voltage charge pump second terminal being coupled to ground through said third switch, said third switch being coupled to said logic controller;

9. The low-voltage PMOS switch control method is used for controlling the on-off of a circuit and is characterized by being applied to a low-voltage PMOS switch circuit, and the low-voltage PMOS switch circuit comprises: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end and is used for outputting a detection signal according to the voltage of the power supply input end;

the method comprises the following steps:

acquiring a switch enabling signal;

and when the detection signal indicates that the input voltage is greater than or equal to a preset voltage, controlling the second switch to be conducted, and controlling the negative-pressure charge pump to stop running so as to enable the grid voltage of the PMOS switching tube to be zero.

10. The utility model provides a low pressure PMOS switch controlling means for control circuit break-make, its characterized in that, controlling means is applied to low pressure PMOS switch circuit, low pressure PMOS switch circuit includes: the power supply comprises a power supply input end, a PMOS switching tube, a power supply voltage detector, a first switch, a second switch and a negative voltage charge pump; the power input end is connected with the source electrode of the PMOS switch tube, the power input end is also connected with the grid electrode of the PMOS switch tube through the first switch, the grid electrode of the PMOS switch tube is also connected with the first end of the negative pressure charge pump, the second end of the negative pressure charge pump is grounded, and the first end of the negative pressure charge pump is also grounded through the second switch; one end of the power supply voltage detector is connected with the power supply input end and is used for outputting a detection signal according to the voltage of the power supply input end;

the device comprises:

the first acquisition module is used for acquiring a switch enabling signal;