CN116387241A - Method for manufacturing semiconductor-on-insulator substrate and method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor-on-insulator substrate and a method for manufacturing a semiconductor device, which can improve the bubble ion implantation method in the intelligent stripping technology in the manufacturing stage of the semiconductor-on-insulator substrate, and form bubbles at different depths of the wafer. Bubble layer, so that semiconductor-on-insulator substrates with different top-layer semiconductor thicknesses can be directly obtained after wafer bonding, annealing and stripping, simplifying the manufacturing process, improving manufacturing efficiency, and saving costs.

Description

Method for manufacturing semiconductor-on-insulator substrate and method for manufacturing semiconductor device

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor-on-insulator substrate and a method for manufacturing a semiconductor device.

Background technique

Silicon-on-insulator (Silicon-On-Insulator, SOI) and other semiconductor-on-insulator technologies set a layer of embedded oxide layer between the top semiconductor and the substrate, which effectively reduces the parasitic capacitance between the top semiconductor and the substrate, and the SOI substrate is also It has the advantages of high integration density, small short channel effect, low substrate noise, high integration density, fast speed, and low power consumption, and is widely used in integrated circuits, optoelectronics, and micro-electro-mechanical systems (MEMS) sensors and other fields.

In existing chips formed based on semiconductor-on-insulator wafers, different components often have different thickness requirements for the top-layer semiconductor. The current method is to oxidize or etch the top-layer semiconductor of the semiconductor-on-insulator wafer to consume different thicknesses. The top-layer semiconductors are used to meet the manufacturing requirements of different components. This method has cumbersome steps and requires fine adjustment of the thermal oxidation or etching process recipe (recipe), which is low in efficiency and high in cost.

Contents of the invention

The purpose of the present invention is to provide a semiconductor-on-insulator substrate manufacturing method and a semiconductor device manufacturing method, which can form top-layer semiconductors with different thicknesses in the manufacturing stage of the semiconductor-on-insulator substrate and simplify the manufacturing process, improve manufacturing efficiency, and save energy. cost.

To achieve the above object, the present invention provides a method for manufacturing a semiconductor-on-insulator substrate, which includes:

forming a pre-oxidized layer on the surface of the second wafer;

performing bubbling ion implantation with different depths on different regions of the second wafer, so as to form bubbling layers with different depths in the second wafer;

bonding the side of the second wafer formed with the pre-oxidized layer to the first wafer;

annealing to make the bubble layer bubble, so that the corresponding part of the second wafer is peeled off at the bubble layer, thereby forming a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate having the first A wafer and the remainder of the second wafer bonded thereto.

Optionally, the pre-oxidized layer is formed on the surface of the second wafer by a thermal oxidation process or a deposition process.

Optionally, the pre-oxidized layer covers at least the front side of the second wafer, and bubble ion implantation is performed on the front side of the second wafer, and the A pre-oxidized layer is bonded to the first wafer.

Optionally, the step of performing bubble ion implantation at different depths on different regions of the second wafer includes:

Form a first mask layer on the pre-oxidation layer, and use the first mask layer as a mask to perform bubble ion implantation into the second wafer with the first implantation energy, so as to forming a bubble layer in the first depth of the second wafer;

removing the first mask layer, and forming a second mask layer on the pre-oxidation layer, the region defined by the second mask layer is different from the region defined by the first mask layer;

performing bubble ion implantation into the second wafer with a second implantation energy using the second mask layer as a mask, so as to form a bubble layer in a second depth of the second wafer, the The second depth is different from the first depth.

Optionally, the sidewall of at least one of the first mask layer and the second mask layer is an inclined sidewall, so that the bubble layer of the first depth and the bubble layer of the second depth Adjacent side walls meet.

Optionally, the first mask layer and the second mask layer are formed by exposing the positive photoresist and the negative photoresist respectively coated on the pre-oxidized layer successively through the same mask. mask layer.

Optionally, the step of performing bubble ion implantation at different depths on different regions of the second wafer includes:

forming a third mask layer on the pre-oxidation layer;

Bubble ion implantation is performed on the second wafer with the third mask layer as a mask, and the third mask layer provides different bubble ion implantation for different regions of the second wafer The selection ratio enables the formation of bubbling layers with different depths in different regions of the second wafer.

Optionally, the sidewalls of the third mask layer corresponding to the junctions of different regions are sloped sidewalls, so that adjacent sides of the bubble layers in adjacent regions meet or overlap.

Optionally, the bubbling ions implanted into the second wafer include hydrogen ions.

Optionally, both the first wafer and the second wafer for bubbling ion implantation are silicon wafers, and the semiconductor-on-insulator substrate is a silicon-on-insulator substrate.

Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which includes:

Using the method for manufacturing a semiconductor-on-insulator substrate according to the present invention, a semiconductor-on-insulator substrate is provided;

Different components and devices are fabricated based on top layer semiconductors of different thicknesses of the semiconductor-on-insulator substrate.

Compared with the prior art, the technical solution of the present invention can realize different top-layer semiconductor thicknesses in different regions during the manufacturing stage of the semiconductor-on-insulator substrate, thereby reducing subsequent process steps, saving time and reducing costs.

Description of drawings

Those of ordinary skill in the art will understand that the provided drawings are for better understanding of the present invention, but do not constitute any limitation to the scope of the present invention. in:

FIG. 1 is a schematic diagram of a cross-sectional structure of a device in a conventional manufacturing method of an SOI substrate.

FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor-on-insulator substrate according to the first embodiment of the present invention.

3 and 4 are schematic cross-sectional structures of two exemplary devices in the method for manufacturing a semiconductor-on-insulator substrate in this embodiment.

5 and 6 are schematic cross-sectional structures of two exemplary devices in the method for manufacturing a semiconductor-on-insulator substrate according to the second embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to determine the presence of certain features, steps, operations, elements and/or components, but does not exclude the presence or presence of one or more other features, steps, operations, elements, components and/or groups. Add to. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical solutions proposed by the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

Please refer to Fig. 1, a kind of manufacturing technology of SOI substrate is smart-cut technology (Smart-cut), and its main steps include: First, convert the surface of the second wafer (which can be a silicon wafer) W2 into Pre-oxidation layer OX, as shown in (A) among Fig. 1; Then form bubble layer in the second wafer W2 below pre-oxidation layer OX thickness by bubbling ion implantation process (implantation ion can comprise hydrogen ion etc.) H+, as shown in (B) in Fig. 1; Then the second wafer W2 with bubbling layer H+ and pre-oxidized layer OX is bonded with the first wafer (which can be a silicon wafer) W1, as shown in Fig. 1 Shown in (C) in; After annealing, the second wafer W2 will bubble at the bubble layer H+, and the back side W2' of the second wafer W2 will be peeled off from the bubble layer H+, thus obtaining SOI wafer, the remaining part of the second wafer W2 including the bubble layer H+ is the top layer silicon of the SOI wafer, the first wafer W1 is the base of the SOI wafer, the first wafer W1 and the remaining second wafer The pre-oxidized layer OX sandwiched between the circle W2 is the embedded oxide layer of the SOI wafer, as shown in (D) and (E) in Fig. 1; after that, the top layer silicon (such as The bubble layer (H+) is oxidized or etched with different thicknesses, so as to obtain SOI substrates with different thicknesses of top silicon, as shown in (F) in FIG. 1 .

In the above method, it is necessary to oxidize or etch the top layer silicon of different regions of the SOI wafer with different thicknesses to obtain top layer silicon with different thicknesses. The steps are cumbersome, and fine adjustment of the thermal oxidation or etching process formula (recipe), in order to control the thickness of the top silicon in different regions is different, the efficiency is low and the cost is high.

Based on this, the present invention provides a method for manufacturing a semiconductor-on-insulator substrate, which improves the bubble ion implantation method in the above-mentioned smart stripping technology to form bubble layers of different depths, so that after bonding, annealing and stripping Finally, semiconductor-on-insulator substrates with different top-layer semiconductor thicknesses can be directly obtained, which can simplify the manufacturing process, improve manufacturing efficiency, and save costs.

The method for manufacturing the semiconductor-on-insulator substrate of the present invention will be described in detail below in conjunction with corresponding specific embodiments.

first embodiment

Please refer to FIG. 2, the present embodiment provides a method for manufacturing a semiconductor-on-insulator substrate, which includes the following steps:

S1, forming a pre-oxidized layer on the surface of the second wafer;

S2, performing bubbling ion implantation with different depths on different regions of the second wafer, so as to form bubbling layers with different depths in the second wafer;

S3, bonding the side of the second wafer on which the pre-oxidized layer is formed to the first wafer;

S4, annealing to bubble the bubble layer, so that the corresponding part of the second wafer is peeled off at the bubble layer, thereby forming a semiconductor-on-insulator substrate, and the semiconductor-on-insulator substrate has the The remaining part of the first wafer and the second wafer bonded thereto.

It should be understood that the processes involved in each step in this embodiment can be completed by any suitable process in the art, and the selection of materials for each structure can be reasonably selected according to the requirements of the semiconductor-on-insulator substrate to be manufactured. This embodiment does not specifically limit it.

As an example, please refer to (A) in FIG. 3 , in step S1 of this embodiment, first, a second wafer W2 is provided, and the material of the second wafer is selected according to the semiconductor-on-insulator substrate to be manufactured. The top semiconductor material is selected, and the second wafer can be a bare wafer, or a wafer doped with any other suitable N-type impurities or P-type impurities. For example, the semiconductor-on-insulator substrate to be manufactured is a silicon-on-insulator substrate, and the second wafer is a bare silicon wafer. Then pre-oxidize the front, back and surrounding sidewall surfaces of the second wafer W2 through a thermal oxidation process to form a pre-oxidation layer OX surrounding the second wafer W2.

Please refer to (B) and (C) in FIG. 3 , in step S2 of this example, bubble layers are formed in different depths of the second wafer W2 through multiple bubble ion implantation processes.

Taking two bubble ion implantation procedures as an example, the specific process of step S2 in this example includes:

First, please refer to (B) in Fig. 3, coat a layer of photoresist (not shown, can be positive photoresist, also can be negative photoresist) on the pre-oxidized layer OX of the second wafer W2 front. resist), and photoresist the layer of photoresist through an ion implantation mask to form a patterned first mask layer Mask1, the first mask layer Mask1 covers a part of the pre-oxidized layer OX, and The corresponding ion implantation window is defined.

Then, please continue to refer to (B) in FIG. 3 , using the first mask layer Mask1 as a mask, the second wafer W2 in the ion implantation window defined by the first mask layer Mask1 is started by using the first implantation energy. Bubble ion implantation, to form a bubble layer H1 in the first depth of the second wafer W2 under the pre-oxidation layer OX, wherein the first implantation energy determines the implantation depth of the bubble ions, that is, determines the formed bubble layer The depth of the bottom of H1 (i.e. the first depth), and the depth of the bottom of the bubble layer H1 (i.e. the first depth) further determines the remaining semiconductor layer after peeling off at the subsequent bubble layer H1 (i.e. the semiconductor-on-insulator substrate to be manufactured The top semiconductor) thickness in this region. It should be understood that the bubbling ions implanted in this step follow a Gaussian distribution, which will be distributed concentratedly near the first depth, and have less thickness distribution on the surface layer of the second wafer W2 and below the first depth.

Next, please refer to (C) in FIG. 3 , remove the first mask layer Mask1, and coat another layer of photoresist on the pre-oxidized layer OX on the front side of the second wafer W2, and use the corresponding mask This other layer of photoresist is carried out photolithography on the plate, (form the patterned second mask layer Mask2, this second mask layer Mask2 covers the partial area of pre-oxidation layer OX, and defines the corresponding ion implantation window ( That is, the defined area). Preferably, the ion implantation window defined by the second mask layer Mask2 is aligned with or overlaps the sidewall of the ion implantation window defined by the first mask layer Mask1, so that the two types of subsequently formed The deep bubbling layers meet or overlap at adjacent sidewalls, which is beneficial to the subsequent smart peeling of corresponding parts on the second wafer.

Optionally, the exposure characteristics of the above-mentioned another layer of photoresist are opposite to those of the photoresist forming the first mask layer Mask1, and then the ion implantation mask used to form the first mask layer Mask1 can be used to control the exposure characteristics of the photoresist. Another layer of photoresist photolithography, that is, through the same mask plate, the positive photoresist and the negative photoresist respectively coated on the pre-oxidized layer are exposed successively to form the first mask layer Mask1 and the second mask layer Mask2, at this time, the regions defined by the first mask layer Mask1 and the second mask layer Mask2 (that is, the defined ion implantation window) are not only different but also complementary. Adjacent side walls of the bubble layer can be aligned and connected. On the other hand, compared with the prior art shown in FIG. Two regions with different bubbling ion depths can be obtained, which can reduce mask cost.

Afterwards, please continue to refer to (C) in FIG. 3 , using the second mask layer Mask2 as a mask, start the second wafer W2 in the ion implantation window defined by the second mask layer Mask2 through the second implantation energy. Bubble ion implantation, to form a bubble layer H2 in a second depth of the second wafer W2 below the pre-oxidation layer OX, wherein the second implantation energy determines the implantation depth of the bubble ions, that is, determines the formed bubble layer The depth of the bottom of H2 (i.e. the second depth), and the depth of the bottom of the bubble layer H2 (i.e. the second depth) further determines the remaining semiconductor layer (i.e. the semiconductor-on-insulator substrate to be manufactured) after the peeling occurs at the subsequent bubble layer H2. The top semiconductor) thickness in this region. After the bubble ion implantation is completed, the second mask layer Mask2 can be removed by any suitable process to prepare for subsequent wafer bonding. Wherein, when the second injection energy is less than the first injection energy, the second depth corresponding to the bottom of the bubble layer H2 is smaller than the first depth corresponding to the bottom of the bubble layer H1; when the second injection energy is greater than the first injection energy, the bubble The second depth corresponding to the bottom of layer H2 is greater than the first depth corresponding to the bottom of blistered layer H1.

In addition, the bubble ions implanted in each bubble ion implantation process can be any suitable ions, for example, the bubble ions include hydrogen ions and the like. The bubbling ions implanted in each bubbling ion implantation process may be the same or different. After the bubbling ions are implanted into the second wafer W2, a microcavity will be formed in the implanted part of the second wafer W2 (ie, the bubbling layers H1, H2). And foaming (or foaming).

It should be understood that the bubbling ions implanted in this step also follow a Gaussian distribution, which will be distributed concentratedly near the second depth, and have less thickness distribution on the surface layer of the second wafer W2 and below the second depth. Adjacent sidewalls of the foamed layer H2 of the second depth and the foamed layer H1 of the first depth are not only connected in the transverse direction, but also overlapped (or overlapped) in the vertical direction. Therefore, in the second depth After the deep bubble layer H2 is formed, the bubble layer H1 and the bubble layer H2 are connected, and different and continuous bubble layers with different depths are formed in different regions on the second wafer W2, and the continuous bubble layer connects the second wafer W2. Wafer W2 is divided into three layers from top to bottom: semiconductor layer W22 with negligible doping concentration of bubbling ions on the front side, bubbling layers H1 and H2 in the middle, and bubbling ion doping concentration on the back side. negligible semiconductor layer W21.

Please refer to (D) in FIG. 3 , in step S3 of this example, a first wafer W1 is first provided, and the selection of the first wafer W1 is selected according to the underlying semiconductor material of the semiconductor-on-insulator substrate to be manufactured, The first wafer W1 may be a bare wafer, or a wafer doped with any other suitable N-type impurities or P-type impurities. Then, the second wafer W2 is turned upside down, the back side is up, the front side is down, and the front side of the second wafer W2 (ie, the semiconductor layer W22 on the front side) faces the first wafer W1, and the second wafer W2 is placed on the front side. The pre-oxidized layer OX is bonded to the first wafer W1.

Please refer to (E) and (F) in FIG. 3 , in step S4 of this example, low-temperature annealing is performed on the first wafer W1 and the second wafer W2 bonded together, and the bubble layers H1 and H2 are due to Internal pressure is generated in the internal micro-cavity to cause foaming, and finally the semiconductor layer W21 on the back surface above the bubble layers H1 and H2 of the second wafer W2 is completely removed by intelligent peeling at the bubble layers H1 and H2. Then perform high-temperature annealing to increase the bonding strength between the semiconductor layer W22 on the front surface and the first wafer W1, and recover the damage caused by the bubble ion implantation in the remaining second wafer W2 (ie, the semiconductor layer W22 on the front surface), Then the desired semiconductor-on-insulator substrate is obtained. Wherein, the first wafer W1 is the bottom semiconductor layer of the semiconductor-on-insulator substrate, and the semiconductor layer W22 above the first wafer W1 (the remaining second wafer W2) is the top semiconductor layer of the semiconductor-on-insulator substrate, The pre-oxidation layer OX sandwiched between the first wafer W1 and the semiconductor layer W22 (the remaining second wafer W2 ) is a pre-buried oxide layer of the semiconductor-on-insulator substrate. Moreover, due to the different depths of the bubble layers H1 and H2, the remaining thicknesses of the semiconductor layer W22 (the remaining second wafer W2) in the bubble layer H1 region and the bubble layer H2 region are different, so the semiconductor-on-insulator substrate obtained The top semiconductor layer has different thicknesses in different regions.

It should be understood that, first, in step S3 of the above-mentioned example, the second wafer W2 is inverted and then bonded to the first wafer W1, and after performing smart stripping in step S4, the back surface of the second wafer W2 is peeled off. The semiconductor layer W21 with a corresponding thickness on the top of the semiconductor layer W21 on the front surface of the second wafer W2 is left as the top semiconductor layer of the semiconductor-on-insulator substrate. The thickness is small, for example, the maximum thickness of the top semiconductor layer can be within 10 μm. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, when the required maximum thickness of the top semiconductor layer is relatively large, please refer to FIG. 4, and the second After wafer W2 is thinned on the back side or front side, pre-oxidation treatment is performed on the surface to form a pre-oxidation layer OX. In step S3, the second wafer W2 is upright bonded to the first wafer W1 , after performing smart stripping in step S4, the semiconductor layer W22 of corresponding thickness on the front side of the second wafer W2 is stripped, leaving the semiconductor layer W21 on the back side of the second wafer W2 as the top semiconductor layer of the semiconductor-on-insulator substrate, Therefore, the top semiconductor layer of the formed semiconductor-on-insulator substrate can be relatively thick and the ion implantation damage in the top semiconductor layer can be reduced, thereby omitting the high-temperature annealing process after the smart stripping and reducing the cost.

Second, in the above example, the sidewalls of the first mask layer Mask1 and the second mask layer Mask2 are vertical sidewalls, and the sidewalls of the first bubble layer H2 and the second bubble layer H2 are aligned laterally but the technical solution of this embodiment is not limited thereto. In another example of this embodiment, please refer to (A) and (B) in FIG. 4 , the formation of the bubble layer H1 in step S1 and step S2 is the same as the example shown in FIG. 3 , and will not be repeated here. repeat. But please refer to (C) in FIG. 4 , the sidewall of the second mask layer Mask2 formed in step S2 facing the ion implantation window defined by it is an inclined sidewall, and the top of the inclined sidewall is in contact with the bubble layer H1 The sidewalls are aligned or located within the edge of the bubble layer H1, so that when the bubble layer H2 is formed by performing bubble ion implantation using the second mask layer Mask2 as a mask, the inclined sidewalls of the second mask layer Mask2 are used For the characteristics of the gradual change of the permeability of the bubbling ions, a transitional bubbling zone (unmarked) is formed on the side of the bubbling layer H2 adjacent to the bubbling layer H1, and the depth of the transitional bubbling zone is between the depth of the bubbling layer H1 and The depth range of the bubble layer H2 gradually changes. Please refer to (D) to (F) in FIG. 4 , after step S3 and step S4, the boundary region between two top semiconductor layers with different thicknesses of the formed semiconductor-on-insulator substrate can be made into a slope (not shown) mark), and since there are bubble layers in the region from bubble layer H1 to bubble layer H2, the smart peeling in step S4 is relatively easy and the effect is better, and the sidewall of the mask layer is used to create The scheme of forming a transitional bubble area between the bubble layers H1 and H2, compared with the mask layer scheme of the vertical side wall shown in FIG. Larger depth difference (for example, 1 μm ~ 5 μm). In addition, in other embodiments of the present invention, the corresponding sidewalls of one or both of the first mask layer mask1 and the second mask layer mask2 may be set as inclined sidewalls as required, so as to form the The desired transitional blistering zone.

Third, the limitations of the first mask layer Mask1 and the second mask layer Mask2 in the example shown in FIG. 3 and FIG. The technical solution of the present invention is not limited thereto. In other embodiments of the present invention, through the restriction of the first mask layer Mask1 and the second mask layer Mask2, the bubble layer H1 and the bubble layer H2 may not be in contact with each other in the horizontal direction, nor in the vertical direction. but the horizontal distance and the vertical distance between the two are relatively small, which does not affect the subsequent step S4 in which the part of the second wafer W2 located on the upper side of the bubble layer H1 and the bubble layer H2 and the part located on the bubble layer Integral Smart Peel between H1 and portions of the underside of the bubble layer H2.

To sum up, the manufacturing method of this embodiment, by improving the existing intelligent stripping technology, can manufacture semiconductor-on-insulator substrates with different thicknesses of top-layer semiconductors in the manufacturing stage of semiconductor-on-insulator substrates, and for two The manufacture of semiconductor-on-insulator substrates with different top semiconductor thicknesses, deeper bubble ion implantation means that the thickness of the top semiconductor layer in the semiconductor-on-insulator substrate is thicker, thereby realizing insulators with two different top semiconductor thicknesses The manufacture of the upper semiconductor substrate reduces process steps and saves production time and cost.

It should also be noted that in this embodiment, in step S2, the formation of bubble layers with two depths is only exemplified, which corresponds to the formation of a semiconductor-on-insulator substrate with a top semiconductor layer with two thicknesses, but this The technical solution of the invention is not limited thereto. In other embodiments of the present invention, in step S2, ion implantation windows located in more different regions on the front side of the second wafer can be respectively manufactured through multiple masks, thereby through the ion implantation windows in each ion implantation window The implantation energies of the bubbling ions are varied to create more bubbling layers with different depths, and ultimately to create S-on-insulator substrates with more top semiconductor layers with different thicknesses. In addition, the material of each mask layer formed in this process is not limited to photoresist, but can also be any other suitable material.

second embodiment

In the solutions of the above-mentioned embodiments, each manufacturing of a bubble layer of a depth requires a process of manufacturing a mask layer and bubble ion implantation, and the process is relatively complicated.

Therefore, this embodiment provides a method for manufacturing a semiconductor-on-insulator substrate, which also includes steps S1 to S4 as shown in FIG. Blistered layers of at least three different depths can be produced.

Specifically, referring to (A) in FIG. 5 , in step S1 of this embodiment, firstly, a second wafer W2 is provided, and the material of the second wafer is selected according to the top layer semiconductor of the semiconductor-on-insulator substrate to be manufactured. The second wafer can be a bare wafer, or a wafer doped with any other suitable N-type impurities or P-type impurities. For example, the semiconductor-on-insulator substrate to be manufactured is a silicon-on-insulator substrate, and the second wafer is a bare silicon wafer. Then pre-oxidize the front, back and surrounding sidewall surfaces of the second wafer W2 through a thermal oxidation process to form a pre-oxidation layer OX surrounding the second wafer W2.

Please refer to (B) in FIG. 5 , in step S2 of this embodiment, the masking effect of the same mask layer and its feature of providing different bubble ion implantation selectivity ratios in different regions of the second wafer W2 , so that bubble layers with different depths are formed in different regions of the second wafer W2.

Taking the formation of two types of bubbling layers with different depths in the second wafer W2 as an example, the specific process of step S2 in this embodiment includes:

First, please refer to (B) in FIG. 5 , by any suitable process such as coating or deposition, the third mask layer Mask3 is covered on the pre-oxidized layer OX on the front side of the second wafer W2, and the third mask layer is further The layer Mask3 is subjected to photolithography and etching to remove the third mask layer Mask3 in some areas. The material of the third mask layer Mask3 may be any suitable material, which is not specifically limited in the present invention.

Then, please continue referring to (B) in FIG. Without the blocking and energy loss of the third mask layer Mask3, it can be implanted into the deeper position of the second wafer W2, thus forming a deeper bubble layer H2, and the third mask layer Mask3 masks the bubbles in the region Ions can only be implanted into the shallower position of the second wafer W2 because of the barrier and energy loss of the third mask layer Mask3, thereby forming a shallower bubble layer H1. Wherein the permeability of the third mask layer Mask3 to the bubbling ions determines the bottom depth (i.e. the first depth) of the bubbling layer H1, and the energy of the bubbling ion implantation determines the bottom depth (i.e. the second depth) of the bubbling layer H2. depth), and the depth of the bottom of the bubble layer H1 and the bubble layer H2 (i.e. the first depth) further determines the remaining semiconductor layer after the peeling occurs at the subsequent bubble layer H1 (i.e. the top semiconductor layer of the semiconductor-on-insulator substrate to be manufactured ) in the thickness of these two regions.

It should be noted that the sidewalls of the third mask layer Mask3 may be vertical sidewalls or inclined sidewalls. Wherein, when the sidewall of the third mask layer Mask3 is an inclined sidewall, different thickness positions of the sidewall of the third mask layer Mask3 have different permeability to the bubbling ions. A transitional bubble region (unmarked) with gradual depth is formed between the bubble layers H2, which is beneficial to the smart peeling effect in the subsequent step S4, and is conducive to making the thickness difference between the top semiconductor layers of different thicknesses finally formed in adjacent regions. (ie the top step height difference) is greater.

In addition, after the bubble ion implantation in step S2 is completed, the third mask layer Mask3 is removed by any suitable process such as etching or chemical mechanical planarization (CMP) to prepare for subsequent wafer bonding.

In this embodiment, the bubbling ions implanted in the bubbling ion implantation process also follow a Gaussian distribution in the second wafer W2, so that the inside of the second wafer W2 automatically The structure is divided into three layers from top to bottom: the semiconductor layer with negligible doping concentration of bubbling ions on the front, the bubbling layer H1 or H2 in the middle, and the semiconductor layer with negligible doping concentration of bubbling ions on the back .

In addition, the bubble ions implanted in the bubble ion implantation process may be any suitable ions, for example, the bubble ions include hydrogen ions and the like. After the bubbling ions are implanted into the second wafer W2, a microcavity will be formed in the implanted part of the second wafer W2 (i.e., the bubbling layers H1, H2). Internal pressure causes foaming (or foaming).

Please refer to (C) in FIG. 5 , in step S3 of this embodiment, a first wafer W1 is first provided, and the material of the first wafer W1 is selected according to the underlying semiconductor material of the semiconductor-on-insulator substrate to be manufactured. , the first wafer W1 may be a bare wafer, or a wafer doped with any other suitable N-type impurity or P-type impurity. Then, the back of the second wafer W2 faces the first wafer W1, and the pre-oxidized layer OX on the back of the second wafer W2 is bonded to the first wafer W1.

Please refer to (D) in FIG. 5 , in step S4 of this embodiment, low-temperature annealing is performed on the first wafer W1 and the second wafer W2 bonded together, and the bubble layers H1 and H2 are Internal pressure is generated in the cavity to cause foaming, and finally the backside portion of the second wafer W2 above the bubble layers H1 , H2 is peeled off at the bubble layers H1 , H2 . Then high-temperature annealing is performed to increase the bonding strength and restore the damage caused by the bubble ion implantation in the remaining second wafer W2, thereby obtaining the desired semiconductor-on-insulator substrate. Wherein, the first wafer W1 is the bottom semiconductor layer of the semiconductor-on-insulator substrate, the remaining second wafer W2 above the first wafer W1 is the top semiconductor layer of the semiconductor-on-insulator substrate, and the first wafer W1 and The pre-oxidation layer OX sandwiched between the remaining second wafers W2 is a pre-buried oxide layer of the semiconductor-on-insulator substrate. Moreover, because the depths of the bubble layers H1 and H2 are different, the remaining thicknesses of the remaining second wafer W2 in the area of the bubble layer H1 and the area of the bubble layer H2 are different, so the top semiconductor layer of the semiconductor-on-insulator substrate obtained is Different regions have different thicknesses.

The manufacturing method of this embodiment is also an improvement to the existing intelligent stripping technology. Compared with the first embodiment, a bubble ion implantation is performed with a layer of the third mask layer Mask3 as a mask to achieve The foaming layers H1 and H2 of two different depths can be formed at the same time, and the process is simpler and the cost is lower.

It should be understood that, in step S2 of the example shown in FIG. 5 , only the formation of bubble layers with two depths is exemplified, which corresponds to the formation of a semiconductor-on-insulator substrate with a top semiconductor layer with two thicknesses, but The technical solution of the present invention is not limited thereto. In another example of this embodiment, please refer to (A) in FIG. 6 , in step S2, by controlling the third mask layer Mask3 to have different thicknesses in at least three different regions of the second wafer W2, Therefore, in the same bubble ion implantation process, at least three different bubble ion implantation selection ratios are provided to the second wafer W2 as a whole, so that through the masking effect of the third mask layer Mask3 and one bubble ion implantation , manufacturing at least three kinds of bubble layers H1, H2, H3 with different depths in the second wafer W2, thereby finally manufacturing a semiconductor-on-insulator substrate with at least three top semiconductor layers with different thicknesses in step S4, such as Shown in (B) in FIG. 6 .

Based on the same inventive concept, an embodiment of the present invention also provides a method for manufacturing a semiconductor device (not shown), which includes: first, using the method for manufacturing a semiconductor-on-insulator substrate according to the present invention to provide a semiconductor-on-insulator substrate Substrate; Next, different components and devices are fabricated based on the semiconductor-on-insulator substrate with different thicknesses of the top-layer semiconductor.

Wherein, the specific process of manufacturing corresponding different components based on the top-layer semiconductor with different thicknesses of the semiconductor-on-insulator substrate can be realized by any suitable process in the field, which can include ion implantation process, gate process, metal interconnection Process etc., will not be described in detail here.

To sum up, the technical solution of the present invention can realize different top-layer semiconductor thicknesses in different regions during the manufacturing stage of the semiconductor-on-insulator substrate, thereby reducing subsequent process steps, saving time, and reducing costs.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures belong to the protection scope of the technical solution of the present invention.

Claims (10)

1. A method for manufacturing a semiconductor-on-insulator substrate, characterized in that, comprising: forming a pre-oxidized layer on the surface of the second wafer; performing bubbling ion implantation with different depths on different regions of the second wafer, so as to form bubbling layers with different depths in the second wafer; bonding the side of the second wafer formed with the pre-oxidized layer to the first wafer; annealing to make the bubble layer bubble, so that the corresponding part of the second wafer is peeled off at the bubble layer, thereby forming a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate having the first A wafer and the remainder of the second wafer bonded thereto. 2. The manufacturing method according to claim 1, wherein the pre-oxidized layer is formed on the surface of the second wafer by a thermal oxidation process or a deposition process. 3. The manufacturing method according to claim 1, wherein the pre-oxidized layer covers at least the front side of the second wafer, and bubble ion implantation is performed on the front side of the second wafer, and The pre-oxidized layer on the front side of the second wafer is bonded to the first wafer. 4. The manufacturing method according to claim 1, wherein the step of performing bubble ion implantation of different depths to different regions of the second wafer comprises: Form a first mask layer on the pre-oxidation layer, and use the first mask layer as a mask to perform bubble ion implantation into the second wafer with the first implantation energy, so as to forming a bubble layer in the first depth of the second wafer; removing the first mask layer, and forming a second mask layer on the pre-oxidation layer, the region defined by the second mask layer is different from the region defined by the first mask layer; performing bubble ion implantation into the second wafer with a second implantation energy using the second mask layer as a mask, so as to form a bubble layer in a second depth of the second wafer, the The second depth is different from the first depth. 5. The manufacturing method according to claim 4, wherein the sidewall of at least one of the first mask layer and the second mask layer is an inclined sidewall, so that the starting point of the first depth is Adjacent sides of the foam layer and the second depth of foam layer meet or overlap. 6. The manufacturing method according to claim 4, wherein the same mask plate is used to expose the positive photoresist and the negative photoresist respectively coated on the pre-oxidized layer successively to form The first mask layer and the second mask layer. 7. The manufacturing method according to claim 1, wherein the step of performing bubble ion implantation of different depths to different regions of the second wafer comprises: forming a third mask layer on the pre-oxidation layer; Bubble ion implantation is performed on the second wafer with the third mask layer as a mask, and the third mask layer provides different bubble ion implantation for different regions of the second wafer The selection ratio enables the formation of bubbling layers with different depths in different regions of the second wafer. 8. The manufacturing method according to claim 7, wherein the sidewalls of the third mask layer corresponding to the junctions of different regions are sloped sidewalls, so that the adjacent sides of the bubble layers in adjacent regions are in phase with each other. connect or overlap. 9. The manufacturing method according to any one of claims 1-8, wherein the bubbling ions implanted into the second wafer include hydrogen ions. 10. A method for manufacturing a semiconductor device, comprising: Using the method for manufacturing a semiconductor-on-insulator substrate according to any one of claims 1-9, a semiconductor-on-insulator substrate is provided; Different components and devices are fabricated based on top layer semiconductors of different thicknesses of the semiconductor-on-insulator substrate.

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